DETAILED ACTION
This Office action is in response to the amendment submitted on March 27, 2026.
Claims 1, 4-7, 11, and 12 are pending.
Claims 1, 4-7, 11, and 12 are currently amended.
Claims 2, 3, and 8-10 are canceled.
The objection to the title of the invention is withdrawn in view of the Applicant’s amendments to the title of the invention.
The objections to Claims 1-8, 11, and 12 are withdrawn in view of the Applicant’s amendments to the claims or cancellation of the claims.
The 35 U.S.C. § 112(b) rejections of Claims 2-8 and 12 are withdrawn in view of the Applicant’s amendments to the claims or cancellation of the claims.
The 35 U.S.C. § 101 rejections of Claims 1, 4-7, 11, and 12 are maintained in view of the Applicant’s arguments and amendments to the claims and further explained hereinafter. The 35 U.S.C. § 101 rejections of Claims 2, 3, and 8-10 are withdrawn in view of the Applicant’s cancellation of the claims.
In the interest of facilitating compact prosecution, the Examiner kindly asks the Applicant’s representative to authorize Internet communications with the Examiner by submitting Form PTO/SB/439 using Patent Center.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Claim Objections
Claims 1, 4-6, and 12 are objected to because of the following informalities:
Claim 1 recites “the at least one parameter processor set” in the “receiving” step. It should read -- the parameter processor set --.
Claim 1 recites “the at least one parameter processor set” in the first “determining” step. It should read -- the parameter processor set --.
Claim 1 recites “the at least one parameter processor in the at least one parameter processor” in the first “starting” step. It should read -- the at least one parameter processor --.
Claim 4 recites “the plurality of a plurality of target parameter processors.” It should read -- the plurality of target parameter processors --.
Claim 5 contains a typographical error: the word “and” at the beginning of the second “determining” step should be deleted and added after the semicolon (;) of the “inputting” step.
Claim 6 contains a typographical error: the word “and” at the beginning of the “selecting” step should be deleted and added after the semicolon (;) of the “determining” step.
Claim 12 recites “handle type.” It should read -- a handle type --.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 4-7, 11, and 12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 1 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 1 is directed to a method, which is a process (a series of steps or acts), and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 1 recites the limitations:
(a) determining, from the at least one parameter processor set, a target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor, to obtain a processing result;
(b) determining, according to the processing result, a processing command corresponding to the target instruction […];
(c) wherein the step of determining the target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor, to obtain the processing result comprises:
(d) starting from a first target instruction parameter in the target instruction parameter vector, and traversing each parameter processor in the at least one parameter processor in the at least one parameter processor, and determining the target parameter processor from the at least one parameter processor based on the preset to-be-matched command parameter vector of each parameter processor in the at least one parameter processor;
(e) processing the target instruction parameter matching the target parameter processor by using the first preset anonymous function in the target parameter processor;
(f) wherein the step of starting from the first target instruction parameter in the target instruction parameter vector, traversing each parameter processor in the at least one parameter processor, and determining the target parameter processor from the at least one parameter processor based on the preset to-be-matched command parameter vector of each parameter processor in the at least one parameter processor, comprises:
(g) determining a number of elements in the preset to-be-matched command parameter vector corresponding to each parameter processor in the at least one parameter processor;
(h) starting from the first target instruction parameter, and determining whether preceding target instruction parameters match elements at corresponding positions in the preset to-be- matched command parameter vector, a number of preceding target instruction parameters is the number of elements, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector, determining the at least one parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor;
(i) starting from the first target instruction parameter that does not match the target parameter processor in a target parameter vector, and determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector again, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector, determining the at least one parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor, until matched parameter processors are determined for all target instruction parameters.
The recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting, in the preamble:
(1) […] applicable in an electronic device […].
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human evaluating a parameter processor set using observation, evaluation, judgment, and opinion to determine a target parameter processor. And the limitation (b) in the context of the claim encompasses a human evaluating a processing result using observation, evaluation, judgment, and opinion to determine a processing command. And the limitations (c) to (i) in the context of the claim encompass a human evaluating a target instruction parameter using observation, evaluation, judgment, and opinion to parse the target instruction parameter. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional element, in the preamble:
(1) […] applicable in an electronic device […].
The additional element (1) is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the judicial exception using generic computer components. The electronic device is used as a tool to perform the various steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional elements:
(2) […] processing the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(3) […] executing the processing command.
The additional elements (2) and (3) fail to meaningfully limit the claim because they do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). The additional elements recite only the idea of processing a target instruction parameter and executing a processing command without details on how they are accomplished. The claim omits any details as to how the processing of the target instruction parameter and the executing of the processing command solve a technical problem, and instead recites only the idea of a solution or outcome. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not integrate a judicial exception into a practical application because these types of recitations are equivalent to the words “apply it.”
Also, the claim recites the additional element:
(4) receiving a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the at least one parameter processor set comprises at least one parameter processor, and the at least one parameter processor consists of a preset to-be-matched command parameter vector and a first preset anonymous function.
The additional element (4) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05(g).
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed above with respect to integration of the abstract idea into a practical application, the claim recites the additional element, in the preamble:
(1) […] applicable in an electronic device […].
The additional element (1) amounts to no more than mere instructions to apply the judicial exception using generic computer components. The analysis under Step 2A, Prong Two is carried through to Step 2B. The use of a computer or other machinery in its ordinary capacity does not integrate a judicial exception into a practical application or provide significantly more.
Also, the claim recites the additional elements:
(2) […] processing the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(3) […] executing the processing command.
The additional elements (2) and (3) do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. The analysis under Step 2A, Prong Two is carried through to Step 2B. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not provide significantly more because these types of recitations are equivalent to the words “apply it.”
Also, the claim recites the additional element:
(4) receiving a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the at least one parameter processor set comprises at least one parameter processor, and the at least one parameter processor consists of a preset to-be-matched command parameter vector and a first preset anonymous function.
The additional element (4) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive a target instruction and a parameter processor set. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components, only the idea of a solution or outcome, and an insignificant extra-solution activity, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 4-7, 11, and 12 are dependent on Claim 1, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 1.
Claim 4 recites the limitations:
(a) wherein the step of determining the at least one parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor comprises:
(b) in response to that a plurality of parameter processors are a plurality of target parameter processors, selecting, to be the target parameter processor, the at least one parameter processor having a largest number of matched target instruction parameters among the plurality of a plurality of target parameter processors.
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Claim 5 recites the limitations:
(a) wherein the step of determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector in the preset to-be-matched command parameter vector, comprises:
(b) determining a second preset anonymous function corresponding to each element in the preset to-be-matched command parameter vector;
(c) inputting the preceding target instruction parameters of which the number is the number of elements into second preset anonymous functions corresponding to the elements at the corresponding positions in the preset to-be-matched command parameter vector, and acquiring return values returned by the second preset anonymous functions according to input target instruction parameters;
(d) and determining, according to the return values, whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector.
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Claim 6 recites the limitations:
(a) wherein the step of determining the second preset anonymous function corresponding to each element in the preset to-be-matched command parameter vector, comprises:
(b) determining a plurality of third preset anonymous functions;
(c) and selecting a preset number of third preset anonymous functions from the plurality of third preset anonymous functions, and performing logical operation on the preset number of third preset anonymous functions from the plurality of third preset anonymous functions, to obtain the second preset anonymous function, wherein the logical operation comprises at least one of logical and operation, logical or operation, and logical not operation.
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Claim 7 recites the limitations:
(a) wherein the step of determining the at least one parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor, comprises:
(b) determining whether there is an abnormal instruction parameter in the preceding target instruction parameters of which the number is the number of elements, wherein the abnormal instruction parameter is an instruction parameter that does not match any parameter processor; and
(c) in response to that there is an abnormal instruction parameter, deleting the abnormal instruction parameter, re-selecting preceding target instruction parameters of which the number is the number of elements, determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the preset to-be-matched command parameter vector, determining, to be the target parameter processor, the at least one parameter processor corresponding to the preset to-be-matched command parameter vector.
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Claim 11 recites the limitation:
(a) wherein the target instruction comprises a command name and a number of command parameters.
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Claim 12 recites the limitation:
(a) wherein the first preset anonymous function in the at least one parameter processor is an anonymous function of handle type, and the preset to-be-matched command parameter vector is a pre-registered vector.
Claims 4-7, 11, and 12 recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract (see MPEP § 2106.04(a)(2)(III)).
Thus, Claims 4-7, 11, and 12 do not add any steps or additional elements, when considered both individually and as a combination, that would convert Claim 1 into patent-eligible subject matter.
Therefore, Claims 1, 4-7, 11, and 12 are not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
Allowable Subject Matter
Claims 1, 4-7, 11, and 12 are allowable over the cited prior art. However, the Applicant must overcome any corresponding objections and/or rejections of these claims set forth hereinabove in order to place these claims in condition for allowance.
Response to Arguments
Applicant’s arguments submitted on March 27, 2026 have been fully considered, but they are not persuasive.
In the Remarks, the Applicant argues:
While not necessarily agreeing with the Examiner, but rather in an effort to advance prosecution, Applicants have amended claim 1. As amended, claim 1 explicitly recites an electronic device as the execution subject of the claimed method. The claimed solution is therefore implemented by relying on a hardware entity, which falls within the statutory category of patentable subject matter. This definition directly specifies that the solution shall be implemented based on the hardware of the electronic device, and it is not an abstract idea that can be performed solely through human mental activity or pen-and-paper deduction, nor is it a vague expression simply involving the application of an abstract idea. Instead, it constructs a practical application scenario based on a physical device, satisfies the basic category requirements for patentable subject matter under patent law, and consolidates the foundation for patent eligibility from the perspective of the execution subject.
(See Remarks – pages 13.)
Examiner’s response:
Examiner disagrees. With respect to the Applicant’s assertion that “[…] claim 1 explicitly recites an electronic device as the execution subject of the claimed method. The claimed solution is therefore implemented by relying on a hardware entity, which falls within the statutory category of patentable subject matter,” the Examiner respectfully submits that the Applicant’s argument is not commensurate in scope with the claim language. Specifically, amended Claim 1 explicitly recites “[a] method […] applicable in an electronic device.” Contrary to the Applicant’s assertion, the claim does not require that the method is executed by the electronic device. Under the broadest reasonable interpretation (BRI), the scope of the term “applicable” is not limited to execution. The claim only requires that the method can be applied in the electronic device. In other words, the electronic device is capable of applying the method, but does not necessarily has to.
Furthermore, should there be further prosecution and the Applicant decides to change “applicable in an electronic device” to “executable/executed in an electronic device” in an attempt to overcome the § 101 rejection, the Examiner would like to point out that such amendment would still not integrate the abstract idea into a practical application. The limitation “executable/executed in an electronic device” would still be treated under Step 2A, Prong Two of the 2019 Revised Patent Subject Matter Eligibility Guidance (2019 PEG) as an additional element that amounts to no more than mere instructions to apply the judicial exception using generic computer components. This limitation would further be treated under Step 2B of the 2019 PEG as an additional element that does not amount to an inventive concept (a.k.a. “significantly more” than the judicial exception).
Therefore, for at least the reasons set forth above, the rejections made under 35 U.S.C. § 101 with respect to Claims 1, 4-7, 11, and 12 are proper and therefore, maintained.
In the Remarks, the Applicant argues:
Additionally, claim 1 recites a specific implementation process of parameter processing and refines the complete operational logic, including counting parameter vector elements, position-wise matching, and iterative rematching until adaptation of all parameter processors is completed. This parameter processing process is neither a highly generalized operation nor a simple data processing act with no substantive meaning; rather, it is an exclusive technical means designed for the scenario of instruction parameter parsing and adaptation, which constitutes substantive technical features that amount to significantly more than a judicial exception. The entire solution relies on the electronic device to execute this exclusive parameter processing process and can achieve accurate adaptation between target instruction parameters and the corresponding parameter processors. Claim 1 constitutes a technical improvement with practical application value in the field of computer technology, and the overall solution fully complies with the requirements for patent eligibility without any issue of ineligibility.
(See Remarks – pages 13.)
Examiner’s response:
Examiner disagrees. With respect to the Applicant’s assertion that “[t]he entire solution relies on the electronic device to execute this exclusive parameter processing process and can achieve accurate adaptation between target instruction parameters and the corresponding parameter processors,” the Examiner respectfully submits that the use of the electronic device in the Applicant’s solution to execute the exclusive parameter processing process does not negate the mental nature of the Applicant’s solution. Furthermore, the Examiner respectfully submits the relevant portions of MPEP § 2106.04(a)(2)(III)(C) with emphasis added for purposes of convenience in discussion and illustration:
MPEP § 2106.04(a)(2)(III)(C) A Claim That Requires a Computer May Still Recite a Mental Process
Claims can recite a mental process even if they are claimed as being performed on a computer. The Supreme Court recognized this in Benson, determining that a mathematical algorithm for converting binary coded decimal to pure binary within a computer’s shift register was an abstract idea. The Court concluded that the algorithm could be performed purely mentally even though the claimed procedures “can be carried out in existing computers long in use, no new machinery being necessary.” 409 U.S at 67, 175 USPQ at 675. See also Mortgage Grader, 811 F.3d at 1324, 117 USPQ2d at 1699 (concluding that concept of “anonymous loan shopping” recited in a computer system claim is an abstract idea because it could be “performed by humans without a computer”).
1. Performing a mental process on a generic computer. An example of a case identifying a mental process performed on a generic computer as an abstract idea is Voter Verified, Inc. v. Election Systems & Software, LLC, 887 F.3d 1376, 1385, 126 USPQ2d 1498, 1504 (Fed. Cir. 2018). In this case, the Federal Circuit relied upon the specification in explaining that the claimed steps of voting, verifying the vote, and submitting the vote for tabulation are “human cognitive actions” that humans have performed for hundreds of years. The claims therefore recited an abstract idea, despite the fact that the claimed voting steps were performed on a computer. 887 F.3d at 1385, 126 USPQ2d at 1504. Another example is Versata, in which the patentee claimed a system and method for determining a price of a product offered to a purchasing organization that was implemented using general purpose computer hardware. 793 F.3d at 1312-13, 1331, 115 USPQ2d at 1685, 1699. The Federal Circuit acknowledged that the claims were performed on a generic computer, but still described the claims as “directed to the abstract idea of determining a price, using organizational and product group hierarchies, in the same way that the claims in Alice were directed to the abstract idea of intermediated settlement, and the claims in Bilski were directed to the abstract idea of risk hedging.” 793 F.3d at 1333; 115 USPQ2d at 1700-01.
2. Performing a mental process in a computer environment. An example of a case identifying a mental process performed in a computer environment as an abstract idea is Symantec Corp., 838 F.3d at 1316-18, 120 USPQ2d at 1360. In this case, the Federal Circuit relied upon the specification when explaining that the claimed electronic post office, which recited limitations describing how the system would receive, screen and distribute email on a computer network, was analogous to how a person decides whether to read or dispose of a particular piece of mail and that “with the exception of generic computer-implemented steps, there is nothing in the claims themselves that foreclose them from being performed by a human, mentally or with pen and paper”. 838 F.3d at 1318, 120 USPQ2d at 1360. Another example is FairWarning IP, LLC v. Iatric Sys., Inc., 839 F.3d 1089, 120 USPQ2d 1293 (Fed. Cir. 2016). The patentee in FairWarning claimed a system and method of detecting fraud and/or misuse in a computer environment, in which information regarding accesses of a patient’s personal health information was analyzed according to one of several rules (i.e., related to accesses in excess of a specific volume, accesses during a pre-determined time interval, or accesses by a specific user) to determine if the activity indicates improper access. 839 F.3d. at 1092, 120 USPQ2d at 1294. The court determined that these claims were directed to a mental process of detecting misuse, and that the claimed rules here were “the same questions (though perhaps phrased with different words) that humans in analogous situations detecting fraud have asked for decades, if not centuries.” 839 F.3d. at 1094-95, 120 USPQ2d at 1296.
3. Using a computer as a tool to perform a mental process. An example of a case in which a computer was used as a tool to perform a mental process is Mortgage Grader, 811 F.3d. at 1324, 117 USPQ2d at 1699. The patentee in Mortgage Grader claimed a computer-implemented system for enabling borrowers to anonymously shop for loan packages offered by a plurality of lenders, comprising a database that stores loan package data from the lenders, and a computer system providing an interface and a grading module. The interface prompts a borrower to enter personal information, which the grading module uses to calculate the borrower’s credit grading, and allows the borrower to identify and compare loan packages in the database using the credit grading. 811 F.3d. at 1318, 117 USPQ2d at 1695. The Federal Circuit determined that these claims were directed to the concept of “anonymous loan shopping”, which was a concept that could be “performed by humans without a computer.” 811 F.3d. at 1324, 117 USPQ2d at 1699. Another example is Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. The Federal Circuit determined that these claims were directed to mental processes of parsing and comparing data, because the steps were recited at a high level of generality and merely used computers as a tool to perform the processes. 881 F.3d at 1366, 125 USPQ2d at 1652-53.
According to the relevant portions of the MPEP provided hereinabove, the Examiner would like to point out that amended Claim 1 recites limitations describing how an instruction is parsed. This is analogous to how a person parses an instruction (in the human mind alone or with the aid of pen and paper) by determining and traversing instruction parameters and that, with the exception of the generic electronic device and execution step, there is nothing in the claim itself that forecloses it from being performed by a human mind alone or with the aid of pen and paper. The claim therefore recites an abstract idea, despite the fact that the claimed steps pertaining to parsing an instruction could be performed on an electronic device.
Therefore, for at least the reason set forth above, the rejections made under 35 U.S.C. § 101 with respect to Claims 1, 4-7, 11, and 12 are proper and therefore, maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Qing Chen whose telephone number is 571-270-1071. The Examiner can normally be reached on Monday through Friday from 9:00 AM to 5:00 PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, the Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at https://www.uspto.gov/ interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Qing Chen/
Primary Examiner, Art Unit 2191
Prosecution Insights