DETAILED ACTION
This is the initial Office action based on the preliminary amendment submitted on January 24, 2024.
Claims 1-8, 11, and 12 are pending.
Claim 8 is currently amended.
Claims 9 and 10 are canceled.
Claims 11 and 12 are added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Interpretation Under 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) ELEMENT IN CLAIM FOR A COMBINATION.—An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitations use a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a receiving component, configured to […],” “a processing component, configured to […],” and “an execution component, configured to […]” recited in Claim 8.
Because these claim limitations are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If the Applicant does not intend to have these limitations interpreted under 35 U.S.C. 112(f), the Applicant may: (1) amend the claim limitations to avoid them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitations recite sufficient structure to perform the claimed function so as to avoid them being interpreted under 35 U.S.C. 112(f).
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INSTRUCTION PARSING IN A GENERAL-PURPOSE SOFTWARE DRAWING MODULE.
Claim Objections
Claims 1-8, 11, and 12 are objected to because of the following informalities:
Claims 1, 3, 4, 7, 8, and 12 recite “the parameter processor.” It should read -- the at least one parameter processor --.
Claim 2 contains a typographical error: the word “and” should be added after the “starting” step.
Claims 2 and 3 recite “each parameter processor.” It should read -- each parameter processor in the at least one parameter processor --.
Claim 3 contains a typographical error: the word “and” should be added after the “starting from the first target instruction parameter, determining […]” step.
Claims 3 and 5-7 recite “the to-be-matched command parameter vector.” It should read -- the preset to-be-matched command parameter vector --.
Claim 4 recites “target parameter processors.” It should read -- a plurality of target parameter processors --.
Claim 4 recites “the largest number of matched target instruction parameters.” It should read -- a largest number of matched target instruction parameters --.
Claim 5 recites “the corresponding positions.” It should read -- the corresponding positions in the preset to-be-matched command parameter vector --.
Claim 5 contains a typographical error: the word “and” should be added after the “inputting” step.
Claims 5 and 7 recite “wherein the step: determining.” It should read -- wherein the step of determining --.
Claim 6 contains a typographical error: the word “and” should be added after the “determining” step.
Claim 6 recites “the preset number of third preset anonymous functions.” It should read -- the preset number of third preset anonymous functions from the plurality of third preset anonymous functions --.
Claims 11 and 12 recite “parsing instruction.” It should read -- parsing an instruction --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2-8 and 12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 recites the limitation “the first target instruction parameter.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “a first target instruction parameter” for the purpose of further examination.
Claims 3-7 depend on Claim 2. Therefore, Claims 3-7 suffer the same deficiency as Claim 2.
Claim 3 recites the limitation “the number of preceding target instruction parameters.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “a number of preceding target instruction parameters” for the purpose of further examination.
Claims 4-7 depend on Claim 3. Therefore, Claims 4-7 suffer the same deficiency as Claim 3.
Claim 3 recites the limitation “the target parameter vector.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “a target parameter vector” for the purpose of further examination.
Claims 4-7 depend on Claim 3. Therefore, Claims 4-7 suffer the same deficiency as Claim 3.
Claim 5 recites the limitation “the second preset anonymous functions.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “preset anonymous functions” for the purpose of further examination.
Claim 6 depends on Claim 5. Therefore, Claim 6 suffers the same deficiency as Claim 5.
Claim 5 recites the limitation “the input target instruction parameters.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “the preceding target instruction parameters” for the purpose of further examination.
Claim 6 depends on Claim 5. Therefore, Claim 6 suffers the same deficiency as Claim 5.
Claim 8 recites the limitation “the parameter processors.” There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “the parameter processor set” for the purpose of further examination.
Claim 12 recites the limitation “an anonymous function of which the type is handle.” The claim is rendered vague and indefinite because of the awkward claim language used. In the interest of compact prosecution, the Examiner subsequently interprets this limitation as reading “an anonymous function stored as a type of variable” for the purpose of further examination.
Claim limitations “a receiving component, configured to […],” “a processing component, configured to […],” and “an execution component, configured to […]” recited in Claim 8 invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Applicant’s disclosure does not provide any associations between the structures and the functions. For example, Figure 3 of the Applicant’s drawings and its corresponding description in the specification are devoid of any structures that perform the functions in the claim. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If the Applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, the Applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8, 11, and 12 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 1 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 1 is directed to a method, which is a process (a series of steps or acts), and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 1 recites the limitations:
(a) determining, from the parameter processor set, a target parameter processor matching the target instruction parameter in the target instruction parameter vector […]; and
(b) determining, according to the processing result, a processing command corresponding to the target instruction […].
The recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human observing a parameter processor set using observation, evaluation, judgment, and opinion to determine a target parameter processor. And the limitation (b) in the context of the claim encompasses a human observing a processing result using observation, evaluation, judgment, and opinion to determine a processing command. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional element:
(1) receiving a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the parameter processor set comprises at least one parameter processor, and the parameter processor consists of a preset to- be-matched command parameter vector and a first preset anonymous function.
The additional element (1) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05.
Also, the claim recites the additional elements:
(2) […] processing the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(3) […] executing the processing command.
The additional elements (2) and (3) fail to meaningfully limit the claim because they do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). The additional elements recite only the idea of processing a target instruction parameter and executing a processing command without details on how they are accomplished. The claim omits any details as to how the processing of the target instruction parameter and the executing of the processing command solve a technical problem, and instead recites only the idea of a solution or outcome. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not integrate a judicial exception into a practical application because these types of recitations are equivalent to the words “apply it.”
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed hereinabove with respect to integration of the abstract idea into a practical application, the claim recites the additional element:
(1) receiving a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the parameter processor set comprises at least one parameter processor, and the parameter processor consists of a preset to- be-matched command parameter vector and a first preset anonymous function.
The additional element (1) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive a target instruction and a parameter processor set. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Also, the claim recites the additional elements:
(2) […] processing the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(3) […] executing the processing command.
The additional elements (2) and (3) do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. The analysis under Step 2A, Prong Two is carried through to Step 2B. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not provide significantly more because these types of recitations are equivalent to the words “apply it.”
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent an insignificant extra-solution activity and only the idea of a solution or outcome, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 2-7, 11, and 12 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated hereinabove.
Claim 2 recites the limitations:
wherein the step of determining the target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor, to obtain the processing result comprises:
(a) starting from the first target instruction parameter in the target instruction parameter vector, traversing each parameter processor in the at least one parameter processor, and determining the target parameter processor from the at least one parameter processor based on the preset to-be-matched command parameter vector of each parameter processor;
(b) processing the target instruction parameter matching the target parameter processor by using the first preset anonymous function in the target parameter processor.
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Claim 3 recites the limitations:
wherein the step of starting from the first target instruction parameter in the target instruction parameter vector, traversing each parameter processor in the at least one parameter processor, and determining the target parameter processor from the at least one parameter processor based on the preset to-be-matched command parameter vector of each parameter processor, comprises:
(a) determining a number of elements in the preset to-be-matched command parameter vector corresponding to each parameter processor;
(b) starting from the first target instruction parameter, determining whether preceding target instruction parameters match elements at corresponding positions in the to-be-matched command parameter vector, the number of preceding target instruction parameters is the number of elements, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to- be-matched command parameter vector, determining the parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor;
(c) starting from the first target instruction parameter that does not match the target parameter processor in the target parameter vector, determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to-be-matched command parameter vector again, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to-be-matched command parameter vector, determining the parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor, until matched parameter processors are determined for all target instruction parameters.
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Claim 4 recites the limitation:
wherein the step of determining the parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor comprises:
(a) in response to that a plurality of parameter processors are target parameter processors, selecting, to be the target parameter processor, the parameter processor having the largest number of matched target instruction parameters among the plurality of target parameter processors.
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Claim 5 recites the limitations:
wherein the step: determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to-be-matched command parameter vector, comprises:
(a) determining a second preset anonymous function corresponding to each element in the to-be-matched command parameter vector;
(b) inputting the preceding target instruction parameters of which the number is the number of elements into the second preset anonymous functions corresponding to the elements at the corresponding positions, and acquiring return values returned by the second preset anonymous functions according to the input target instruction parameters;
(c) determining, according to the return values, whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions.
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Claim 6 recites the limitations:
wherein the step of determining the second preset anonymous function corresponding to each element in the to-be-matched command parameter vector, comprises:
(a) determining a plurality of third preset anonymous functions;
(b) selecting a preset number of third preset anonymous functions from the plurality of third preset anonymous functions, and performing logical operation on the preset number of third preset anonymous functions, to obtain the second preset anonymous function, wherein the logical operation comprises at least one of logical and operation, logical or operation, and logical not operation.
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Claim 7 recites the limitations:
wherein the step: determining the parameter processor corresponding to the preset to-be-matched command parameter vector to be the target parameter processor, comprises:
(a) determining whether there is an abnormal instruction parameter in the preceding target instruction parameters of which the number is the number of elements, wherein the abnormal instruction parameter is an instruction parameter that does not match any parameter processor; and
(b) in response to that there is an abnormal instruction parameter, deleting the abnormal instruction parameter, re-selecting preceding target instruction parameters of which the number is the number of elements, determining whether the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to-be-matched command parameter vector, and in response to that the preceding target instruction parameters of which the number is the number of elements match the elements at the corresponding positions in the to-be-matched command parameter vector, determining, to be the target parameter processor, the parameter processor corresponding to the preset to-be-matched command parameter vector.
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Claim 11 recites the limitation:
(a) wherein the target instruction comprises a command name and a number of command parameters.
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Claim 12 recites the limitation:
(a) wherein the first preset anonymous function in the parameter processor is an anonymous function of which the type is handle, and the preset to-be-matched command parameter vector is a pre-registered vector.
These claims are dependent on Claim 1, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 1. For instance, Claims 2-7, 11, and 12 either recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract (see MPEP § 2106.04(a)(2)(III)) or additional elements that do not integrate the judicial exception into a practical application of the judicial exception because: 1) they are mere instructions to apply the judicial exception using generic computer components (see MPEP § 2106.05(f)); 2) they are mere data gathering/transmitting/outputting recited at a high level of generality, and thus are insignificant extra-solution activities (see MPEP § 2106.05(g)); or 3) they do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception (see MPEP § 2106.05(f)), and thus, are not significantly more than the abstract idea. Thus, Claims 2-7, 11, and 12 do not add any steps or additional elements, when considered both individually and as a combination, that would convert Claim 1 into patent-eligible subject matter.
Therefore, Claims 1-7, 11, and 12 are not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
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Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 8 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 8 is directed to a device, which is a machine and/or manufacture, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 8 recites the limitations:
(a) […] determine, from the parameter processors, a target parameter processor matching the target instruction parameter in the target instruction parameter vector […]; and
(b) […] determine, according to the processing result, a processing command corresponding to the target instruction […].
The recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting:
(1) [a] device for parsing an instruction, comprising:
(2) a receiving component, configured to […];
(3) a processing component, configured to […]; and
(4) an execution component, configured to […].
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human observing parameter processors using observation, evaluation, judgment, and opinion to determine a target parameter processor. And the limitation (b) in the context of the claim encompasses a human observing a processing result using observation, evaluation, judgment, and opinion to determine a processing command. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
(1) [a] device for parsing an instruction, comprising:
(2) a receiving component, configured to […];
(3) a processing component, configured to […]; and
(4) an execution component, configured to […].
The additional elements (1) to (4) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer software components. The receiving, processing, and execution components of the device are used as tools to perform the determining steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional element:
(5) […] receive a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the parameter processor set comprises at least one parameter processor, and the parameter processor consists of a preset to-be-matched command parameter vector and a first preset anonymous function.
The additional element (5) is mere data gathering recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amounts to necessary data gathering. See MPEP § 2106.05.
Also, the claim recites the additional elements:
(6) […] process the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(7) […] execute the processing command.
The additional elements (6) and (7) fail to meaningfully limit the claim because they do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. See MPEP § 2106.05(f). The additional elements recite only the idea of processing a target instruction parameter and executing a processing command without details on how they are accomplished. The claim omits any details as to how the processing of the target instruction parameter and the executing of the processing command solve a technical problem, and instead recites only the idea of a solution or outcome. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not integrate a judicial exception into a practical application because these types of recitations are equivalent to the words “apply it.”
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed above with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
(1) [a] device for parsing an instruction, comprising:
(2) a receiving component, configured to […];
(3) a processing component, configured to […]; and
(4) an execution component, configured to […].
The additional elements (1) to (4) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional element:
(5) […] receive a target instruction and a parameter processor set, wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter, the parameter processor set comprises at least one parameter processor, and the parameter processor consists of a preset to-be-matched command parameter vector and a first preset anonymous function.
The additional element (5) simply appends a well-understood, routine, and conventional activity previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer functions of storing and retrieving information in memory and receiving or transmitting data over a network, e.g., using the Internet to gather data as well‐understood, routine, and conventional computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as an insignificant extra-solution activity. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to receive a target instruction and a parameter processor set. Therefore, the additional element remains an insignificant extra-solution activity even upon reconsideration and does not amount to significantly more.
Also, the claim recites the additional elements:
(6) […] process the target instruction parameter by using the target parameter processor, to obtain a processing result; and
(7) […] execute the processing command.
The additional elements (6) and (7) do not require any particular application of the judicial exception and are, at best, the equivalent of merely adding the words “apply it” (or an equivalent) to the judicial exception. The analysis under Step 2A, Prong Two is carried through to Step 2B. Therefore, the additional elements attempt to cover any solution to the identified problem of processing the target instruction parameter and executing the processing command with no restriction on how the processing and the executing are accomplished and no description of the mechanisms for accomplishing the processing and the executing, and do not provide significantly more because these types of recitations are equivalent to the words “apply it.”
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components, an insignificant extra-solution activity, and only the idea of a solution or outcome, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0091849 (hereinafter “Wang”) in view of US 2008/0301702 (hereinafter “Gibbs”).
[Examiner’s Remarks: In order for a reference to be proper for use in an obviousness rejection under 35 U.S.C. 103, the reference must be analogous art to the claimed invention. In re Bigio, 381 F.3d 1320, 1325, 72 USPQ2d 1209, 1212 (Fed. Cir. 2004). A reference is analogous art to the claimed invention if: (1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); or (2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention).
Note that the claimed invention is generally directed to parsing an instruction (specification, page 1). As for the “same field of endeavor” test, Wang is generally directed to an operation module, which is applicable to execute operations according to an extension instruction (Wang, paragraph [0007]). As for the “reasonably pertinent” test, Gibbs is generally directed to automated generation of different script versions (Gibbs, paragraph [0012]). Thus, Wang and Gibbs are both analogous art to the claimed invention (even if it addresses a different problem or even if it is not in the same field of endeavor as the claimed invention). See MPEP § 2141.01(a)(I).]
As per Claim 1, Wang discloses:
A method (paragraph [0006], “There is provided an operation module and a method thereof, which can realize a purpose that a variety of operations can be achieved by employing a single-strip operation instruction, thereby facilitating the operation module to reduce the operation overhead and the power consumption (emphasis added).”) for parsing an instruction, comprising:
[Examiner’s Remarks: Note that the limitation “parsing an instruction” in the preamble of the claim is not given any patentable weight because it is merely a statement of purpose or intended use of the claimed invention. See MPEP § 2111.02.]
receiving a target instruction and a parameter processor set (paragraph [0215], “In block S601, the operation module obtains an extension instruction [receiving a target instruction].”; paragraph [0217], “In block S602, the operation module parses the extension instruction to acquire and parse the extension instruction, so as to obtain the first operation instruction, the second operation instruction, the input data address of the first operation instruction, the output data address of the first operation instruction, the input data index of the first operation instruction, and the input data of the second operation instruction [receiving {…} a parameter processor set].”), wherein the target instruction comprises a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter (paragraph [0138], “For example, in the case that the first operation instruction is a vector instruction, and the input data in the vector instruction is a vector [a target instruction parameter vector, a composition element of the target instruction parameter vector is a target instruction parameter] or a matrix, the instruction adds a function of scaling the input data, that is, adding an operand indicating a scaling coefficient in the opcode domain.”), the parameter processor set comprises at least one parameter processor (paragraph [0217], “In block S602, the operation module parses the extension instruction to acquire and parse the extension instruction, so as to obtain the first operation instruction, the second operation instruction, the input data address of the first operation instruction, the output data address of the first operation instruction, the input data index of the first operation instruction, and the input data of the second operation instruction [at least one parameter processor].”), and the parameter processor consists of a preset to-be-matched command parameter vector (paragraph [0138], “For example, in the case that the first operation instruction is a vector instruction, and the input data in the vector instruction is a vector [a preset to-be-matched command parameter vector] or a matrix, the instruction adds a function of scaling the input data, that is, adding an operand indicating a scaling coefficient in the opcode domain.”);
determining, from the parameter processor set, a target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor, to obtain a processing result (paragraph [0223], “In block S603, the operation module converts an expression mode of the input data index of the first operation instruction, so as to obtain an input data index of the first operation instruction in a default index expression mode. The operation module screens the input data of the first operation instruction according to the input data index of the first operation instruction in the default index expression mode, so as to obtain the input data processed of the first operation instruction [determining, from the parameter processor set, a target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor]. The operation module executes the first operation instruction and the second operation instruction for the input data processed of the first operation instruction and the input data of the second operation instruction respectively according to the execution sequence, so as to obtain an operation result (emphasis added).”); and
determining, according to the processing result, a processing command corresponding to the target instruction, and executing the processing command (paragraph [0223], “In block S603, the operation module converts an expression mode of the input data index of the first operation instruction, so as to obtain an input data index of the first operation instruction in a default index expression mode. The operation module screens the input data of the first operation instruction according to the input data index of the first operation instruction in the default index expression mode, so as to obtain the input data processed of the first operation instruction [determining, according to the processing result, a processing command corresponding to the target instruction]. The operation module executes the first operation instruction and the second operation instruction for the input data processed of the first operation instruction and the input data of the second operation instruction respectively according to the execution sequence, so as to obtain an operation result (emphasis added).”).
Wang does not explicitly disclose:
and the parameter processor consists of a first preset anonymous function.
However, Gibbs discloses:
and a parameter processor consists of a first preset anonymous function (paragraph [0053], “In response to the received indication method 300 includes an act of automatically parsing the script to identify any anonymous functions (act 303). For example, parser 132 can parse script instructions 113 to identify anonymous functions 114 and 115 [a first preset anonymous function].”).
As pointed out hereinabove, Wang and Gibbs are both analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Gibbs into the teaching of Wang to include “and the parameter processor consists of a first preset anonymous function.” The modification would be obvious because one of ordinary skill in the art would be motivated to identify an anonymous function presented during debugging, testing, etc. to indicate the location within a script where an error, test data, etc. was generated (Gibbs, paragraph [0041]).
As per Claim 2, the rejection of Claim 1 is incorporated; and Wang further discloses:
wherein the step of determining the target parameter processor matching the target instruction parameter in the target instruction parameter vector, and processing the target instruction parameter by using the target parameter processor, to obtain the processing result (see 35 U.S.C. 103 rejection of Claim 1 hereinabove) comprises:
starting from a first target instruction parameter in the target instruction parameter vector, traversing each parameter processor in the at least one parameter processor, and determining the target parameter processor from the at least one parameter processor based on the preset to-be-matched command parameter vector of each parameter processor (paragraph [0223], “In block S603, the operation module converts an expression mode of the input data index of the first operation instruction, so as to obtain an input data index of the first operation instruction in a default index expression mode. The operation module screens the input data of the first operation instruction according to the input data index of the first operation instruction in the default index expression mode, so as to obtain the input data processed of the first operation instruction. The operation module executes the first operation instruction and the second operation instruction for the input data processed of the first operation instruction and the input data of the second operation instruction respectively according to the execution sequence, so as to obtain an operation result.”);
processing the target instruction parameter matching the target parameter processor by using the first preset anonymous function in the target parameter processor (paragraph [0223], “In block S603, the operation module converts an expression mode of the input data index of the first operation instruction, so as to obtain an input data index of the first operation instruction in a default index expression mode. The operation module screens the input data of the first operation instruction according to the input data index of the first operation instruction in the default index expression mode, so as to obtain the input data processed of the first operation instruction. The operation module executes the first operation instruction and the second operation instruction for the input data processed of the first operation instruction and the input data of the second operation instruction respectively according to the execution sequence, so as to obtain an operation result.”).
Claim 8 is a device claim corresponding to the method claim hereinabove (Claim 1). Therefore, Claim 8 is rejected for the same reason set forth in the rejection of Claim 1.
As per Claim 12, the rejection of Claim 1 is incorporated; and Wang further discloses:
and the preset to-be-matched command parameter vector is a pre-registered vector (paragraph [0138], “For example, in the case that the first operation instruction is a vector instruction, and the input data in the vector instruction is a vector or a matrix, the instruction adds a function of scaling the input data, that is, adding an operand indicating a scaling coefficient in the opcode domain.”).
Wang does not explicitly disclose:
wherein the first preset anonymous function in the parameter processor is an anonymous function stored as a type of variable.
However, Gibbs discloses:
wherein a first preset anonymous function in a parameter processor is an anonymous function stored as a type of variable (paragraph [0053], “In response to the received indication method 300 includes an act of automatically parsing the script to identify any anonymous functions (act 303). For example, parser 132 can parse script instructions 113 to identify anonymous functions 114 and 115.”; paragraph [0065], “Within the third code example, the script is compacted to minimize size, local variables are renamed to minimize size, comments are stripped out, and no parameter validation[.]”).
As pointed out hereinabove, Wang and Gibbs are both analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Gibbs into the teaching of Wang to include “wherein the first preset anonymous function in the parameter processor is an anonymous function stored as a type of variable.” The modification would be obvious because one of ordinary skill in the art would be motivated to identify an anonymous function presented during debugging, testing, etc. to indicate the location within a script where an error, test data, etc. was generated (Gibbs, paragraph [0041]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Gibbs as applied to Claim 1 above, and further in view of US 2018/0357051 (hereinafter “Puszkiewicz”) (cited in the IDS submitted on 06/11/2025).
[Examiner’s Remarks: In order for a reference to be proper for use in an obviousness rejection under 35 U.S.C. 103, the reference must be analogous art to the claimed invention. In re Bigio, 381 F.3d 1320, 1325, 72 USPQ2d 1209, 1212 (Fed. Cir. 2004). A reference is analogous art to the claimed invention if: (1) the reference is from the same field of endeavor as the claimed invention (even if it addresses a different problem); or (2) the reference is reasonably pertinent to the problem faced by the inventor (even if it is not in the same field of endeavor as the claimed invention).
Note that the claimed invention is generally directed to parsing an instruction (specification, page 1). As for the “same field of endeavor” test, Puszkiewicz is generally directed to command line parsing (Puszkiewicz, paragraph [0004]). Thus, Puszkiewicz is an analogous art to the claimed invention (even if it addresses a different problem). See MPEP § 2141.01(a)(I).]
As per Claim 11, the rejection of Claim 1 is incorporated; and the combination of Wang and Gibbs does not explicitly disclose:
wherein the target instruction comprises a command name and a number of command parameters.
However, Puszkiewicz discloses:
wherein a target instruction comprises a command name and a number of command parameters (paragraph [0266], “The command line itself 204 contains at least one command 206, with zero or more command arguments 208. Command arguments of particular interest here include subcommands 210, which may have zero or more of their own subcommand arguments 212.”).
As pointed out hereinabove, Puszkiewicz is an analogous art to the claimed invention. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Puszkiewicz into the combined teachings of Wang and Gibbs to include “wherein the target instruction comprises a command name and a number of command parameters.” The modification would be obvious because one of ordinary skill in the art would be motivated to parse command lines, including subcommands which are arguments to a command and which have their own respective subcommand arguments, without requiring difficult-to-maintain and error-prone boilerplate command line parsing code (Puszkiewicz, paragraph [0005]).
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim under 35 U.S.C. 103, but would be allowable over the cited prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and overcome any corresponding objections and/or rejections set forth hereinabove.
Conclusion
The prior art made of record and not relied upon is considered pertinent to the Applicant’s disclosure. They are as follows:
US 2009/0006429 (hereinafter “Champion”) discloses data parsing to facilitate both clear code specification and efficient execution.
US 2009/0313604 (hereinafter “Miceli”) discloses parsing declarations in preprocessor conditional directive branches.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Qing Chen whose telephone number is 571-270-1071. The Examiner can normally be reached on Monday through Friday from 9:00 AM to 5:00 PM ET.
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If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Wei Mui, can be reached at 571-272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Qing Chen/
Primary Examiner, Art Unit 2191