DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 40-46 recites the limitation "the plurality of test terminals " in line 2. There is insufficient antecedent basis for this limitation in the claim. It appears that claim 40 should have been dependent on claim 38 and will be treated as such.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 28-29 and 34-36 is/are rejected under 35 U.S.C. 102(a)(b) as being anticipated by CN 114241960 A (CHEN, Wei-xiong et al.)
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Per claim 28, Chen teaches a display substrate [100], comprising: a base substrate [“array substrate”] comprising a display region [103] and a bezel region on at least one side of the display region [102]; a plurality of test sub-terminals in the bezel region [see description of figure 2: “AT Pad signal line comprises SW (total switch) signal line, Gate (gate) signal line, an SD (source) signal line and a Vcom (common electrode) signal line. SW (general switch) signal line is used for realizing transmission of all data. Gate (gate) signal line is the bus of all the gate lines in the display panel 100”], comprising a common voltage test sub- terminal [Vcom] and a plurality of non-common voltage test sub-terminals [SW,Gate,SD]; and a first electrostatic ring in the bezel region [1], through which the plurality of non-common voltage test sub-terminals are arranged in series and/or grounded [see figure 2 and the disclosure: “the first end of each electrostatic ring circuit 1 and one end of the second end of the electrostatic ring circuit 1, electrically connected with one signal line; the first end of the electrostatic ring circuit 1 and the other end of the second end of the electrostatic ring circuit 1, electrically connected with the other signal line or reference electrode wiring”]
Per claim 29, Chen teaches the display substrate according to claim 28, wherein the first electrostatic ring is electrically connected between two adjacent ones of the plurality of non-common voltage test sub-terminals [see figures 1-2].
Per claim 34, Chen teaches the display substrate according to claim 28, further comprising a plurality of first transfer terminals, each of which is electrically connected to one of the test sub-terminals [see the lines connected from the test terminals to the panel in figure 2].
Per claim 35, Chen teaches the display substrate according to claim 34, wherein the first electrostatic ring is electrically connected to the non-common voltage test sub-terminals through the first transfer terminals [inherent as the transfer terminals are between each test sub-terminal].
Per claim 36, Chen teaches the display substrate according to claim 28, further comprising a ground line in the bezel region, wherein each of the non-common voltage test sub-terminals is electrically connected to the ground line through the first electrostatic ring [see GND].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 114241960 A (CHEN, Wei-xiong et al.) in view of CN 112530937 A (LI, YU-ZHI).
Per claim 30, Chen teaches the display substrate according to claim 28, further comprising a second electrostatic ring electrically connected between the common voltage test sub-terminal and one of the plurality of non-common voltage test sub-terminals adjacent to the common voltage test sub- terminal [see the static ring between Vcom and SD in figure 2]; wherein the second electrostatic ring and the first electrostatic ring each comprise a plurality of transistors electrically connected to each other [see transistors M1-M4].
Chen lacks a transistor in the second electrostatic ring has a channel width-to-length ratio smaller than a transistor in the first electrostatic ring. However, Li’s “Specific implementation examples” teaches the following.
Through the analysis and research of the prior art, as shown in FIG. 1, under the condition of not changing the specific structure of the TFT, the TFT in the electrostatic protection circuit is connected to the form of a diode pair (diode pair), equivalently increasing the channel width-length ratio of the TFT; so as to reach the purpose of adjusting the leakage current of the static protection circuit. If the channel width of the TFT is increased in the ESD circuit, then the electrostatic protection circuit will increase the leakage current under the low voltage and high voltage. In the prior art, because the leakage current Ioff of the a-Si product TFT is high, the GOA signal line has more charge releasing channel, the width-length ratio of the TFT in the electrostatic protection circuit can be designed to a relatively small level, even can cancel the electrostatic protection circuit; However, the leakage current Ioff of the oxide TFT such as IGZO is low, the charge is difficult to release under the off-state condition, therefore, the electrostatic protection circuit needs strong ability of releasing charge, obviously using the electrostatic protection circuit of the form of the diode to increase the width-length ratio of the TFT; increasing the leakage current of the electrostatic protection circuit, but also lifting the load of the GOA signal line, affecting the normal driving of the GOA circuit.
Therefore, the present solution is intended to be an electrostatic protection circuit in which a TFT connected by a TFT is used as a first voltage reference unit 1, and a plurality of thin film field effect transistors connected in series are used as a second voltage reference unit 2; not only by reasonably setting the first voltage reference unit 1 in the TFT arrangement mode to equivalently adjust the TFT width-length ratio, the electrostatic protection circuit under the condition of low voltage, has a small load, does not affect the GOA circuit normal work, but also can have large charge releasing capability under the higher voltage; avoiding the GOA input signal line generating static, so as to improve the reliability of the display panel.
Therefore, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine Li with Chen.
Claim(s) 37 and 47 is/are rejected under 35 U.S.C. 103 as being unpatentable over CN 114241960 A (CHEN, Wei-xiong et al.)
Per claim 37, Chen lacks an intermediate substrate, comprising a plurality of display substrates each being the display substrate according to claim 28. However, official notice is hereby taken that it was common knowledge to incorporate a plurality of display substrates in order to improve manufacturing yield. Therefore, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art.
Per claim 47, Chen teaches an electronic paper display apparatus, but lacks a display substrate and an opposite substrate opposite to each other, and an electrophoretic layer between the display substrate and the opposite substrate; wherein the display substrate is the display substrate according to claim 28. However, official notice is hereby taken that it was common knowledge to incorporate a display comprising a display substrate and an opposite substrate opposite to each other, and an electrophoretic layer between the display substrate and the opposite substrate; wherein the display substrate is the display substrate according to claim 28. Using an electrophoretic type display would have resulted in reduced power consumption and thus would have been an expected benefit. Therefore, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art.
Allowable Subject Matter
Claims 31-33 and 38-39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Per claim 31, the prior art teaches the display substrate according to claim 28. In combination with the limitations above, the prior art does not teach the first electrostatic ring comprises a first connection end and a second connection end; the first electrostatic ring comprises four transistors, wherein a gate of a first transistor, a first electrode of the first transistor, and a first electrode of a second transistor are electrically connected together to serve as the first connection end; a second electrode of the first transistor, a second electrode of the second transistor, a gate of the second transistor, a gate of a third transistor, a first electrode of the third transistor, and a first electrode of a fourth transistor are electrically connected together; a gate of the fourth transistor, a second electrode of the fourth transistor, and a second electrode of the third transistor are electrically connected together to serve as the second connection end.
Per claim 38, the prior art teaches the intermediate substrate according to claim 37. In combination with the limitations above, the prior art does not teach the first electrostatic ring further comprising a plurality of test terminals and a third electrostatic ring on a side of a region where the plurality of display substrates are located, wherein the plurality of test terminals comprise a common voltage test terminal and a non-common voltage test terminal, the common voltage test terminal is electrically connected to the common voltage test sub-terminal, the non-common voltage test terminal is electrically connected to one of the non-common voltage test sub-terminals, and the third electrostatic ring is electrically connected between the common voltage test terminal and the non-common voltage test terminal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES A DUDEK whose telephone number is (571)272-2290. The examiner can normally be reached Monday-Thursday 6:30-4:30 MT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES A DUDEK/Primary Examiner, Art Unit 2871