Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
1. This Office Action is responsive to the communication filed 6/15/2026.
Claim Status
2. Claims 1 and 5-6 have currently been amended.
Response to Arguments
3. The applicant's arguments have been taken into consideration, but are moot in view of the new grounds of rejection.
In response to the applicant's argument that the cited prior art fails to teach or suggest the grouped round functions encrypting one data block:
The examiner maintains that the parallel mode of operation including encryption of one block (as disclosed in col. 3, lines 12-14 of Gueron et al) is obvious in light of the grouped round functions encrypting one data block because this feature, along with the function of round operations processing a plurality of block in parallel (disclosed in col. 10, lines 29-32 of Gueron et al) provides the option of using the round functions for processing a singular block, as well as multiple blocks in parallel.
Claim Rejections - 35 USC 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-8 are rejected under 35 USC 103 as being unpatentable over Shibuya et al (JP 2012/215816 A) in view of Gueron et al (US 8,194,854), further in view of Wassenberg et al (US 2020/0401375).
Regarding claim 1, Shibuya et al teaches an encryption device that implements an encryption scheme in which Advanced Encryption Standard (AES) round functions (pg. 3, lines 1-10, which discloses scheduling encryption round functions in an environment using AES and other encryption standards) are executed multiple times in order to update each of multiple internal states of a defined bit length (pg. 10, lines 1-20 and pg. 17, lines 1-15, which disclose adjusting bit length-related data upon executing several encryption rounds).
Shibuya et al does not explicitly teach a processor that, by calling a single prescribed instruction, collectively processing a group of the round functions that are executed in parallel; and wherein the grouped round functions are executed in parallel by calling the single prescribed instruction.
However, Gueron et al teaches a processor that, by calling a single prescribed instruction, collectively processing a group of the round functions that are executed in parallel (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations), the group of the round functions encrypting one data block (col. 3, lines 12-14, which discloses a parallel mode of operation in which one block is encrypted independently from other blocks); and
wherein the grouped round functions are executed in parallel by calling the single prescribed instruction (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations, upon execution of an AES round instruction).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Gueron et al within the disclosure of Shibuya et al in order to provide the predictive result of reducing latency in an AES provisioning system by performing cryptographic operations on data blocks in parallel (as disclosed in col. 4, lines 43-52 of Gueron et al), via allowing for processing of data blocks to be performed in parallel by dispatching an AES round instruction in every cycle, without waiting for the previous instruction to be completed.
Shibuya et al and Gueron et al do not explicitly teach wherein the instruction has an upper limit on a number of bits that are processable, and the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called.
However, Wassenberg et al teaches wherein the instruction has an upper limit on a number of bits that are processable (fig. 3, '306/'308, which discloses each round function being executed for a plurality of branches of 128 bits), and
the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called (par [0028], lines 1-3, which discloses parallel processing of round functions for a reduction in latency).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al in order to provide the predictive result of improving security by preventing potential adversaries from accessing data correlating to previous data samples that may be used to predict future data patterns that may be used to decrypt secure cryptographic data (as disclosed in par [0020] of Wassenberg et al).
Regarding claim 2, Shibuya et al does not explicitly teach wherein, among the multiple round functions, those for which subsequent operations are of the same type are grouped.
However, Gueron et al teaches wherein, among the multiple round functions, those for which subsequent operations are of the same type are grouped (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations, upon execution of an AES round instruction).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Gueron et al within the disclosure of Shibuya et al according to the motivation disclosed regarding claim 1.
Regarding claim 3, Shibuya et al and Gueron et al do not explicitly teach wherein, among the multiple round functions, those for which input values to subsequent operations are at least partially the same are grouped.
However, Wassenberg et al teaches wherein, among the multiple round functions, those for which input values to subsequent operations are at least partially the same are grouped (par [0027], lines 27-32).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al according to the motivation disclosed regarding claim 1.
Regarding claim 4, Shibuya et al and Gueron et al do not explicitly teach wherein the round functions are grouped by multiple instructions having different upper limits on the number of bits that are processable.
However, Wassenberg et al teaches wherein the round functions are grouped by multiple instructions having different upper limits on the number of bits that are processable (par [0028], lines 5-8, "8 branches of 32-bits each").
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al according to the motivation disclosed regarding claim 1.
Regarding claim 5, Shibuya et al teaches encryption method performed when a computer implements an encryption scheme in which AES round functions (pg. 3, lines 1-10, which discloses scheduling encryption round functions in an environment using AES and other encryption standards) are executed multiple times in order to update each of multiple internal states of a defined bit length (pg. 10, lines 1-20 and pg. 17, lines 1-15, which disclose adjusting bit length-related data upon executing several encryption rounds).
Shibuya et al does not explicitly teach collectively processing, by calling a single prescribed instruction, a group of the round functions that are executed in parallel; wherein the instruction has an upper limit on a number of bits that are processable, and the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called; and wherein the grouped round functions are executed in parallel by calling the single prescribed instruction.
However, Gueron et al teaches collectively, by calling a single prescribed instruction, a group of the round functions that are executed in parallel (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations), the group of the round functions encrypting one data block (col. 3, lines 12-14, which discloses a parallel mode of operation in which one block is encrypted independently from other blocks); and
wherein the grouped round functions are executed in parallel by calling the single prescribed instruction (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations, upon execution of an AES round instruction).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Gueron et al within the disclosure of Shibuya et al in order to provide the predictive result of reducing latency in an AES provisioning system by performing cryptographic operations on data blocks in parallel (as disclosed in col. 4, lines 43-52 of Gueron et al), via allowing for processing of data blocks to be performed in parallel by dispatching an AES round instruction in every cycle, without waiting for the previous instruction to be completed.
Shibuya et al and Gueron et al do not explicitly teach wherein the instruction has an upper limit on a number of bits that are processable, and the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called.
However, Wassenberg et al teaches wherein the instruction has an upper limit on a number of bits that are processable (fig. 4, '306/'308, which discloses each round function being executed for a plurality of branches of 128 bits), and
the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called (par [0028, lines 1-3, which discloses parallel processing of round functions for a reduction in latency).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al in order to provide the predictive result of improving security by preventing potential adversaries from accessing data correlating to previous data samples that may be used to predict future data patterns that may be used to decrypt secure cryptographic data (as disclosed in par [0020] of Wassenberg et al).
Regarding claim 6, Shibuya et al teaches non-transitory computer recording medium storing an encryption program (pg. 28, lines 20-30) for making a computer function as an encryption device that implements an encryption scheme in which Advanced Encryption Standard (AES) round functions (pg. 3, lines 1-10, which discloses scheduling encryption round functions in an environment using AES and other encryption standards) are executed multiple times in order to update each of multiple internal states of a defined bit length (pg. 10, lines 1-20 and pg. 17, lines 1-15, which disclose adjusting bit length-related data upon executing several encryption rounds).
Shibuya et al does not explicitly teach collectively processing, by calling a single prescribed instruction, a group of the round functions that are executed in parallel; wherein the instruction has an upper limit on a number of bits that are processable, and the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called; and wherein the grouped round functions are executed in parallel by calling the single prescribed instruction.
However, Gueron et al teaches collectively processing, by calling a single prescribed instruction, a group of the round functions that are executed in parallel (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations); and
wherein the grouped round functions are executed in parallel by calling the single prescribed instruction (col. 10, lines 29-32, which discloses parallel processing of a sequence of AES round operations, upon execution of an AES round instruction), the group of the round functions encrypting one data block (col. 3, lines 12-14, which discloses a parallel mode of operation in which one block is encrypted independently from other blocks).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Gueron et al within the disclosure of Shibuya et al in order to provide the predictive result of reducing latency in an AES provisioning system by performing cryptographic operations on data blocks in parallel (as disclosed in col. 4, lines 43-52 of Gueron et al), via allowing for processing of data blocks to be performed in parallel by dispatching an AES round instruction in every cycle, without waiting for the previous instruction to be completed.
Shibuya et al and Gueron et al do not explicitly teach wherein the instruction has an upper limit on a number of bits that are processable, and the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called.
However, Wassenberg et al teaches wherein the instruction has an upper limit on a number of bits that are processable (fig. 4, '306/'308, which discloses each round function being executed for a plurality of branches of 128 bits), and
the round functions are grouped to minimize a processing load in accordance with a number of times the instruction is called (par [0028, lines 1-3, which discloses parallel processing of round functions for a reduction in latency).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al in order to provide the predictive result of improving security by preventing potential adversaries from accessing data correlating to previous data samples that may be used to predict future data patterns that may be used to decrypt secure cryptographic data (as disclosed in par [0020] of Wassenberg et al).
Regarding claim 7, Shibuya et al and Gueron et al do not explicitly teach wherein, the upper limit on the number of bits for the prescribed instruction is 256 bits, and wherein the grouped round functions include two round functions executed in parallel by calling the single prescribed instruction.
However, Wassenberg et al teaches wherein, the upper limit on the number of bits for the prescribed instruction is 256 bits (par [0028], lines 5-8), and wherein the grouped round functions include two round functions executed in parallel by calling the single prescribed instruction (par [0028-0029]).
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al according to the motivation disclosed regarding claim 1.
Regarding claim 8, Shibuya et al and Gueron et al do not explicitly teach wherein, the upper limit on the number of bits for the prescribed instruction is 512 bits, and wherein the grouped round functions include four round functions executed in parallel by calling the single prescribed instruction.
However, Wassenberg et al teaches wherein, the upper limit on the number of bits for the prescribed instruction is 512 bits (par [0027], lines 27-28, which discloses executing 4 128-bit round functions in parallel), and wherein the grouped round functions include four round functions executed in parallel by calling the single prescribed instruction (par [0028], "total of four round functions").
It would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to be motivated to combine the teachings of Wassenberg et al within the disclosure of Shibuya et al and Gueron et al according to the motivation disclosed regarding claim 1.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Randy A. Scott whose telephone number is (571) 272-3797. The examiner can normally be reached on Monday-Thursday 7:30 am-5:00 pm, second Fridays 7:30 am-4pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Luu Pham can be reached on (571) 270-5002. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RANDY A SCOTT/
Primary Examiner, Art Unit 2439
20260624
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