DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28 May 2026 has been entered.
Information Disclosure Statement
The information disclosure statement submitted on 28 May 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to Claims 1-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 9 is objected to because of the following informalities:
Claim 9, line 2: the limitation “by current” should be changed to “current by”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Stone (US 20120126765 A1) in view of Tapadia (US 20180251036 A1).
Regarding Claim 1, Stone teaches half-bridge power converter (Fig 7) comprising: direct current (DC) voltage terminals (Vin and ground, Fig 7) including a positive DC terminal (Vin, Fig 7) and a negative DC terminal (ground, Fig 7), the DC voltage terminals located on a DC side of the power converter (Vin and ground are on the DC side, Fig 7); a power switching element pair (510 & 512, Fig 7) including a high side power switching element coupled to the positive DC terminal (510, Fig 7) and a low side power switching element coupled to the negative DC terminal (512, Fig 7), wherein the high side power switching element and the low side power switching element are coupled together at a midpoint node (510 & 512 coupled at node 703, Fig 7); interface terminals (ground and the node between 720 and 722, Fig 7) including a positive interface terminal (node between 720 and 722, Fig 7) and a negative interface terminal (ground, Fig 7), the interface terminals located on a second interface side of the power converter (right side of 702, Fig 12); wherein the negative interface terminal is coupled to the negative DC terminal (ground is the negative, Fig 7); an LC filter (514, 716, and 718, Fig 7) including a first end of a switch-side inductor coupled to the midpoint node and to a second-end coupled to a filter node (514 connected to the node between 510 and 512 and the other end connected to the node between 716 and 718, Fig 7), wherein the positive interface terminal is coupled to the filter node (node between 720 and 722 is connected to the node between 716 and 718, Fig 7), a lower capacitor coupled between the filter node and the negative DC terminal (718, Fig 7); and an upper capacitor coupled between the filter node and the positive DC terminal (716, Fig 7), and providing a capacitive coupling between the DC voltage terminals and the interface terminals (716 and 718 provide capacitive coupling between Vin and ground and the node between 720 and 722 and ground, Fig 7).
Stone does not disclose a DC link capacitor coupled across the positive DC terminal and the negative DC terminal.
Tapadia teaches a conventional DC Link capacitor for use with a DC-DC converter (see Fig 1) including a DC link capacitor coupled across the positive DC terminal and the negative DC terminal (DC link capacitor 48 is coupled across top and bottom of DC link 20 that is connected to bidirectional DC-DC converter 14, Fig 1, [0030 & 0039]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the DC link capacitor in Stone, as taught by Tapadia, as it provides the advantage of reducing ripple to improve the efficiency of the converter ([0004] of Tapadia).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Stone (US 20120126765 A1) in view of Tapadia (US 20180251036 A1), further in view of Tang ("Decoupling of Fluctuating Power in Single-Phase Systems Through a Symmetrical Half-Bridge Circuit").
Regarding Claim 2, the combination of Stone and Tapadia discloses all of the limitations of Claim 1.
The combination of Stone and Tapadia does not disclose wherein the upper capacitor reduces ripple current of the converter by providing a path for ripple currents to propagate between the DC terminals and the interface terminals and cancel at least a portion of differential mode current ripple between the DC terminals and the interface terminals.
Tang teaches a conventional upper capacitor for use in a half bridge converter (see Fig 2) including wherein the upper capacitor (C1, Fig 2) reduces ripple current of the converter by providing a path for ripple currents to propagate between the DC terminals and the interface terminals ("the two dc-link capacitors can provide the fluctuating power that can be used to cancel those propagated from the ac grid side, and the voltage of the upper capacitor has π/4 phase shift with the grid voltage", pg 1856, last paragraph) and cancel at least a portion of differential mode current ripple between the DC terminals and the interface terminals ("the dc-link capacitors may not only provide a high-voltage dc bus to support ac/dc or dc/ac conversion, but can also absorb the system ripple power.", pg 1856, paragraph 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the upper capacitor in Stone, as taught by Tang, as it provides the advantage of reducing ripple current and improving the efficiency of the converter (pg 1856 of Tang).
Claims 3-5, 7 & 48-49 are rejected under 35 U.S.C. 103 as being unpatentable over Stone (US 20120126765 A1) in view of Tapadia (US 20180251036 A1), further in view of Agrawal ("Variable-Frequency Critical Soft-Switching of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters").
Regarding Claim 3, the combination of Stone and Tapadia discloses all of the limitations of Claim 1.
The combination of Stone and Tapadia does not disclose further comprising: a controller including a processor, the controller configured to: drive the power switching element pair with variable-frequency critical soft switching control signals.
Agrawal teaches a conventional microcontroller for use in a converter (see Fig 1) including a controller including a processor (microcontroller, pg 6102), the controller configured to: drive the power switching element pair with variable-frequency critical soft switching control signals (microcontroller uses "variable-frequency critical soft switching control method" to drive M1-2, Fig 1, abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 4, the combination of Stone and Tapadia discloses all of the limitations of Claim 1, and further discloses wherein the DC voltage terminals are configured to receive an input DC voltage (Vin and ground, Fig 7 of Stone); wherein the controller is configured to drive the power switching element pair to convert the input DC voltage to an intermediate output voltage at the midpoint node (701 controls 510 & 512 to convert input voltage to intermediate voltage at midpoint 703, Fig 7 of Stone).
The combination of Stone and Tapadia does not disclose a controller including a processor, wherein the LC filter is configured to filter the intermediate output voltage and provide a filtered output voltage at the interface terminals, the filtered output voltage being either AC voltage or DC voltage; and wherein current ripple at the switch-side inductor is at least 200% of average current through the inductor.
Agrawal teaches a conventional microcontroller for use in a converter (see Fig 1) including a controller including a processor (microcontroller, pg 6102); wherein the LC filter is configured to filter the intermediate output voltage and provide a filtered output voltage at the interface terminals (L and output capacitor provide filtered output voltage to Vout + and - terminals, Fig 1), the filtered output voltage being either AC voltage or DC voltage (DC output in this DC-DC converter, Fig 1); and wherein current ripple at the switch-side inductor is at least 200% of average current through the inductor (the ripple current is 220-300% of the average current through the inductor L, Fig 1, Pg 6090, Paragraph 5).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 5, the combination of Stone and Tapadia discloses all of the limitations of Claim 1.
The combination of Stone and Tapadia does not disclose wherein, to drive the power switching element pair to convert the input DC voltage to the intermediate output voltage, the controller is configured to drive the power switching element pair with variable-frequency critical soft switching control signals.
Agrawal teaches a conventional microcontroller for use in a converter (see Fig 1) including wherein, to drive the power switching element pair to convert the input DC voltage to the intermediate output voltage, the controller is configured to drive the power switching element pair with variable-frequency critical soft switching control signals (M1-2 convert Vin to an intermediate voltage using a variable frequency critical soft switching control method, Fig 1, abstract).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 7, the combination of Stone and Tapadia discloses all of the limitations of Claim 1.
The combination of Stone and Tapadia does not disclose further comprising: an upper drain-source capacitor coupled across a drain terminal and a source terminal of the high side power switching element, and a lower drain-source capacitor coupled across a drain terminal and a source terminal of the low side power switching element.
Agrawal teaches conventional drain source capacitors for use with transistors (see Fig 1) including further comprising: an upper drain-source capacitor coupled across a drain terminal and a source terminal of the high side power switching element (CDS,ext of M1, Fig 1), and a lower drain-source capacitor coupled across a drain terminal and a source terminal of the low side power switching element (CDS,ext of M2, Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 48, the combination of Stone, Tapadia, and Agrawal discloses all of the limitations of Claim 7, and further discloses wherein the upper drain-source capacitor adds a capacitance of at least 150 picofarads (pF) between the drain terminal and the source terminal of the high side power switching element, which is in addition to intrinsic capacitance of the high side power switching element between the drain terminal and the source terminal of the high side power switching element ("Fig. 14 shows the variation in the turn-off losses with use of an additional capacitance between zero to 430 pF across both the FETs" and "Fig. 14. Reduction in the turn-off losses using the analytical model and in experiment (with and without effect of current in the FET inherent parasitic capacitance) with addition of external capacitance across FET terminals.", Fig 14, pg 6101-2 of Agrawal).
Regarding Claim 49, the combination of Stone, Tapadia, and Agrawal discloses all of the limitations of Claim 48, and further discloses wherein the lower drain-source capacitor adds a capacitance of at least 150 picofarads (pF) between the drain terminal and the source terminal of the low side power switching element, which is in addition to intrinsic capacitance of the low side power switching element between the drain terminal and the source terminal of the low side power switching element ("Fig. 14 shows the variation in the turn-off losses with use of an additional capacitance between zero to 430 pF across both the FETs" and "Fig. 14. Reduction in the turn-off losses using the analytical model and in experiment (with and without effect of current in the FET inherent parasitic capacitance) with addition of external capacitance across FET terminals.", Fig 14, pg 6101-2 of Agrawal).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Stone (US 20120126765 A1) in view of Tapadia (US 20180251036 A1), further in view of Ye (US 20150180330 A1) and Agrawal ("Variable-Frequency Critical Soft-Switching of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters").
Regarding Claim 6, the combination of Stone and Tapadia discloses all of the limitations of Claim 1, and further discloses the LC filter (514, 716, and 718, Fig 7).
The combination of Stone and Tapadia does not disclose further comprising: a controller including a processor; wherein the interface terminals are configured to receive an AC input voltage; wherein the LC filter is configured to filter the AC input voltage and provide a filtered voltage at the midpoint node; wherein current ripple at the switch-side inductor is at least 200% of average current through the inductor; wherein the controller is configured to drive the power switching element pair to convert the filtered voltage to a DC output voltage; and wherein the DC voltage terminals are configured to output the DC output voltage.
Agrawal teaches a conventional microcontroller for use in a DC-DC converter (see Fig 1) including a controller including a processor (microcontroller, pg 6102); a wherein current ripple at the switch-side inductor is at least 200% of average current through the inductor (Pg 6090, Paragraph 5 the ripple current is 220-300% of the average current through the inductor L in Figure 1); wherein the controller is configured to drive the power switching element pair to convert the filtered voltage to a DC output voltage (M1-2 convert to DC output voltage, Fig 1); and wherein the DC voltage terminals are configured to output the DC output voltage (DC output voltage provided to Vout + and - terminals, Fig 1).
Agrawal does not teach wherein the interface terminals are configured to receive an AC input voltage; wherein the LC filter is configured to filter the AC input voltage and provide a filtered voltage at the midpoint node.
Ye teaches a conventional AC-DC converter (see Fig 1) including wherein the controller is configured to drive the power switching element pair to convert the filtered voltage to a DC output voltage (Q1-2 convert to DC output voltage, Fig 1); and wherein the DC voltage terminals are configured to output the DC output voltage (DC on terminals of load 6, Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the AC-DC converter in Stone, as taught by Ye, as it provides the advantage of the versatility to use the same half bridge switch structure to operate with an AC input.
Claims 8 & 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Agrawal ("Variable-Frequency Critical Soft-Switching of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters") in view of Tapadia (US 20180251036 A1), further in view of Stone (US 20120126765 A1).
Regarding Claim 8, Agrawal teaches a method of power conversion comprising: receiving an input DC voltage at direct current (DC) voltage terminals (Vin is a battery with DC voltage, Fig 1), the DC voltage terminals including a positive DC terminal (Vin, Fig 1) and a negative DC terminal (ground, Fig 1) located on a DC side of the power converter (Vin and ground are on the DC side, Fig 1); driving, by a controller (controller inherent in the converter to control M1-2, Fig 1), a power switching element pair (M1-2, Fig 1) to convert the input DC voltage to an intermediate output voltage at a midpoint node (M1-2 convert input voltage to an intermediate output voltage at the node between them, Fig 1), the power switching element pair including a high side power switching element coupled to the positive DC terminal (M1 coupled to Vin, Fig 1) and a low side power switching element coupled to the negative DC terminal (M2 coupled to ground, Fig 1), wherein the high side power switching element and the low side power switching element are coupled together at the midpoint node (M1-2 coupled together at node SW, Fig 4a); filtering, by an LC filter (L and output capacitor, Fig 1), the intermediate output voltage to provide a filtered output voltage at interface terminals (output terminals on right side of converter, Fig 1), the filtered output voltage being either AC voltage or DC voltage (DC output in this DC-DC converter, Fig 1), the interface terminals including a positive interface terminal (+ output terminal, Fig 1) and a negative interface terminal (- output terminal, Fig 1) located on a second interface side of the power converter (right side of power converter, Fig 1), and the LC filter including: a first end of a switch-side inductor coupled to the midpoint node and a second end coupled to a filter node (L coupled between node SW and top of the output capacitor, Fig 4a), wherein the positive interface is coupled to the filter node (top of the output capacitor is coupled to the top/positive output terminal, Fig 4a), a lower capacitor coupled between the filter node and the negative DC terminal (output capacitor, Fig 4a), wherein the negative interface terminal is coupled to the negative DC terminal (- output terminal is connected to ground, Fig 1).
Agrawal does not teach reducing ripples in the received input DC voltage via a DC link capacitor coupled across the positive DC terminal and the negative DC terminal, and an upper capacitor coupled between the filter node and the positive DC terminal, and providing a capacitive coupling between the DC voltage terminals and the interface terminals.
Tapadia teaches a conventional DC Link capacitor for use with a DC-DC converter (see Fig 1) including reducing ripples in the received input DC voltage via a DC link capacitor coupled across the positive DC terminal and the negative DC terminal (DC link capacitor 48 is coupled across positive and negative rails of bidirectional DC-DC converter 14 and "a DC link capacitor is required to absorb current ripple", Fig 1, [0004, 0030 & 0039]).
Tapadia does not teach an upper capacitor coupled between the filter node and the positive DC terminal, and providing a capacitive coupling between the DC voltage terminals and the interface terminals.
Stone teaches a conventional upper capacitor for use with a half bridge converter (see Fig 7) including an upper capacitor coupled between the filter node and the positive DC terminal (716, Fig 7), and providing a capacitive coupling between the DC voltage terminals and the interface terminals (716 and 718 provide capacitive coupling between Vin and ground and the node between 720 and 722 and ground, Fig 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the DC link capacitor in Agrawal, as taught by Tapadia, as it provides the advantage of reducing ripple to improve the efficiency of the converter ([0004] of Tapadia).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the DC link capacitor in Agrawal, as taught by Stone, as it would have a reasonable expectation of success in alleviating Agrawal's problem of high current handling requirements (pg 6094 of Agrawal) by adding an additional capacitive path to share the switching currents as is known in Kirchoff's law.
Regarding Claim 10, the combination of Agrawal, Tapadia, and Stone discloses all of the limitations of claim 8, and further discloses wherein current ripple at the switch-side inductor is at least 200% of average current through the switch-side inductor (the ripple current is 220-300% of the average current through the inductor L, Fig 1, pg 6090, paragraph 5 of Agrawal).
Regarding Claim 11, the combination of Agrawal, Tapadia, and Stone discloses all of the limitations of claim 8, and further discloses wherein driving the power switching element pair to convert the input DC voltage to the intermediate output voltage includes: driving, by the controller, the power switching element pair with variable-frequency critical soft switching control signals (microcontroller uses "variable-frequency critical soft switching control method" to drive M1-2 to an intermediate voltage, Fig 1, abstract of Agrawal).
Regarding Claim 12, the combination of Agrawal, Tapadia, and Stone discloses all of the limitations of claim 8, and further discloses further comprising: reducing, by an upper drain-source capacitor coupled across a drain terminal and a source terminal of the high side power switching element capacitor (CDS,ext of M1, Fig 1 of Agrawal), a rate of drain-source voltage increase across the drain terminal and the source terminal of the high side power switching element ("By adding external capacitors, the effective switching capacitance can be increased. Thus, the increasing rate of the drain-source voltage, dVDS/dt = ICDS/Coss, can be slowed down.", pg 6097 of Agrawal); and reducing, by a lower drain-source capacitor coupled across a drain terminal and a source terminal of the low side power switching element (CDS,ext of M2, Fig 1 of Agrawal), a rate of drain-source voltage increase across the drain terminal and the source terminal of the high side power switching element ("By adding external capacitors, the effective switching capacitance can be increased. Thus, the increasing rate of the drain-source voltage, dVDS/dt = ICDS/Coss, can be slowed down.", pg 6097 of Agrawal).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Agrawal ("Variable-Frequency Critical Soft-Switching of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters") in view of Tapadia (US 20180251036 A1), further in view of Stone (US 20120126765 A1) and further in view of Tang ("Decoupling of Fluctuating Power in Single-Phase Systems Through a Symmetrical Half-Bridge Circuit").
Regarding Claim 9, further comprising: reducing, by the upper capacitor, ripple by current providing a path for ripple currents to propagate between the DC terminals and the interface terminals ("the two dc-link capacitors can provide the fluctuating power that can be used to cancel those propagated from the ac grid side, and the voltage of the upper capacitor has π/4 phase shift with the grid voltage", pg 1856, last paragraph) and cancel at least a portion of differential mode current ripple between the DC terminals and the interface terminals ("the dc-link capacitors may not only provide a high-voltage dc bus to support ac/dc or dc/ac conversion, but can also absorb the system ripple power.", pg 1856, paragraph 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the upper capacitor in Agrawal, as taught by Tang, as it provides the advantage of reducing ripple current and improving the efficiency of the converter (pg 1856 of Tang).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ye (US 20150180330 A1) in view of Tapadia (US 20180251036 A1), further in view of Stone (US 20120126765 A1).
Regarding Claim 13, Ye teaches a method of power conversion comprising: receiving an AC input voltage at interface terminals (AC source 4 at positive input 4a and negative input 4b, Fig 1), the interface terminals including a positive interface terminal (4a, Fig 1) and a negative interface terminal (4b, Fig 1) located on an interface side of a power converter (left side of power converter 2, Fig 1); filtering, by an LC filter, the AC input voltage to provide a filtered voltage at a midpoint node (AC flows through L to provide filtered voltage to the first internal node 3, Fig 1), and the LC filter including: a first end of a switch-side inductor coupled at the midpoint node (right side of L to first internal node 3, Fig 1), driving, by a controller (8, Fig 1), a power switching element (Q1-2, Fig 1) to convert the filtered voltage to a DC output voltage at the DC terminals (5a-b, Fig 1), the power switching element pair including a high side power switching element coupled to the positive DC terminal of the DC terminals (Q1, Fig 1) and a low side power switching element coupled to the negative DC terminal of the DC terminals (Q2, Fig 1), wherein the high side power switching element and the low side power switching element are coupled together at the midpoint node (Q1-2 coupled together, Fig 1).
Ye does not teach a lower capacitor coupled between a second end of the of the switch-side inductor and a negative DC terminal of DC terminals, and an upper capacitor coupled between the second end of the switch-side inductor and a positive DC terminal of the DC terminals, and reducing ripples in the DC output voltage via a DC link capacitor coupled across the positive DC terminal and the negative DC terminal.
Tapadia teaches a conventional DC Link capacitor for use with a DC-DC converter (see Fig 1) including reducing ripples in the received input DC voltage via a DC link capacitor coupled across the positive DC terminal and the negative DC terminal (DC link capacitor 48 is coupled across positive and negative rails of bidirectional DC-DC converter 14 and "a DC link capacitor is required to absorb current ripple", Fig 1, [0004, 0030 & 0039]).
Tapadia does not teach an upper capacitor coupled between the filter node and the positive DC terminal, and providing a capacitive coupling between the DC voltage terminals and the interface terminals.
Stone teaches a conventional upper capacitor for use with a half bridge converter (see Fig 7) including an upper capacitor coupled between the filter node and the positive DC terminal (716, Fig 7), and providing a capacitive coupling between the DC voltage terminals and the interface terminals (716 and 718 provide capacitive coupling between Vin and ground and the node between 720 and 722 and ground, Fig 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the upper capacitor in Ye, as taught by Stone, as it provides the advantage of improving the filter performance.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the DC link capacitor in Ye, as taught by Tapadia, as it provides the advantage of reducing ripple to improve the efficiency of the converter ([0004] of Tapadia).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ye (US 20150180330 A1) in view of Tapadia (US 20180251036 A1), further in view of Stone (US 20120126765 A1) and Tang ("Decoupling of Fluctuating Power in Single-Phase Systems Through a Symmetrical Half-Bridge Circuit").
Regarding Claim 14, the combination of Ye, Tapadia, and Stone discloses all of the limitations of claim 13.
The combination of Ye, Tapadia, and Stone does not disclose further comprising: reducing, by the upper capacitor, ripple current of the converter by providing a path for ripple currents to propagate between the DC terminals and the interface terminals and cancel at least a portion of differential mode current ripple between the DC terminals and the interface terminals.
Tang teaches a conventional upper capacitor for use in a half bridge converter (see Fig 2) including reducing, by the upper capacitor, ripple current of the converter by providing a path for ripple currents to propagate between the DC terminals and the interface terminals (Pg 1856, Last Paragraph "the two dc-link capacitors can provide the fluctuating power that can be used to cancel those propagated from the ac grid side, and the voltage of the upper capacitor has π/4 phase shift with the grid voltage") and cancel at least a portion of differential mode current ripple between the DC terminals and the interface terminals (Pg 1856, Paragraph 3 "the dc-link capacitors may not only provide a high-voltage dc bus to support ac/dc or dc/ac conversion, but can also absorb the system ripple power.").
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the upper capacitor in Stone, as taught by Tang, as it provides the advantage of reducing ripple current and improving the efficiency of the converter (pg 1856 of Tang).
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ye (US 20150180330 A1) in view of Tapadia (US 20180251036 A1), further in view of Stone (US 20120126765 A1) and Agrawal ("Variable-Frequency Critical Soft-Switching of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters").
Regarding Claim 15, the combination of Ye, Tapadia, and Stone discloses all of the limitations of claim 13.
The combination of Ye, Tapadia, and Stone does not disclose wherein current ripple at the switch-side inductor is at least 200% of average current through the switch-side inductor.
Agrawal teaches a conventional microcontroller for use in a power converter (see Fig 1) including wherein current ripple at the switch-side inductor is at least 200% of average current through the switch-side inductor (the ripple current is 220-300% of the average current through the inductor L, Fig 1, pg 6090, paragraph 5 of Agrawal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 16, the combination of Ye, Tapadia, and Stone discloses all of the limitations of claim 13.
The combination of Ye, Tapadia, and Stone does not disclose wherein driving the power switching element pair to convert the filtered voltage to the DC output voltage includes: driving, by the controller, the power switching element pair with variable-frequency critical soft switching control signals.
Agrawal teaches a conventional microcontroller for use in a power converter (see Fig 1) including wherein driving the power switching element pair to convert the filtered voltage to the DC output voltage includes: driving, by the controller, the power switching element pair with variable-frequency critical soft switching control signals (microcontroller uses "variable-frequency critical soft switching control method" to drive M1-2 to an intermediate voltage, Fig 1, abstract of Agrawal).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Regarding Claim 17, the combination of Ye, Tapadia, and Stone discloses all of the limitations of claim 13.
The combination of Ye, Tapadia, and Stone does not disclose further comprising: reducing, by an upper drain-source capacitor coupled across a drain terminal and a source terminal of the high side power switching element, a rate of drain-source voltage increase across the drain terminal and the source terminal of the high side power switching element; andreducing, by a lower drain-source capacitor coupled across a drain terminal and a source terminal of the low side power switching element, a rate of drain-source voltage increase across the drain terminal and the source terminal of the low side power switching element.
Agrawal teaches conventional drain source capacitors for use with transistors (see Fig 1) including further comprising: an upper drain-source capacitor coupled across a drain terminal and a source terminal of the high side power switching element (CDS,ext of M1, Fig 1), and a lower drain-source capacitor coupled across a drain terminal and a source terminal of the low side power switching element (CDS,ext of M2, Fig 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the microcontroller in Stone, as taught by Agrawal, as it provides the advantage of reducing turn off losses (pg 6097 of Agrawal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER C CAULK whose telephone number is (571)270-0623. The examiner can normally be reached M-F 8:30-5:30, every other Fri off.
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/J.C.C./Examiner, Art Unit 2838
/GARY L LAXTON/Primary Examiner, Art Unit 2838 6/11/2026
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