DETAILED ACTION
Election/Restrictions
Applicants election without traverse of the invention of Group I, Claims 1 through 15 in the reply filed on September 23, 2026 is acknowledged.
Claims 16, 17, 19, 20 and 24 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 23, 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --Wiring Harness Production Method--.
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
The abstract of the disclosure is objected to because of the use of phrases which can be implied, e.g. two occurrents of “The present disclosure…”. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 through 7, 11, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication 2004/0244186 to Umeda (hereinafter “Umeda”) in view of U.S. Publication 2004/0103808 to Lochun et al (hereinafter “Lochun”).
Claim 1: Umeda discloses a wiring harness production method (e.g. Figs. 7 to 9), comprising:
Step S20: preparing a substrate (e.g. 2);
Step S30: printing conductive ink (e.g. 5) onto the substrate (e.g. ¶ [0031]);
Step S40: inherently coagulating (solidifying) the conductive ink to form a conductive loop (e.g. 5, ¶¶ [0032], [0036]); and
Step S50: forming an insulating protective layer (e.g. 7, Fig. 8) around the conductive loop and on a surface thereof (e.g. ¶ [0037]).
Claim 5: Umeda discloses the wiring harness production method according to claim 1, wherein in Step S30 multiple printing is used [to form top conductive loop 5 and bottom conductive loop 5, on substrate 2].
Claim 12: Umeda discloses the wiring harness production method according to claim 1, wherein one conductive layer (e.g. 5, in Fig. 8) formed in Steps S30 and S40 comprises a plurality of the conductive loops (e.g. antenna circuit), which are electrically connected to each other in the same conductive layer (e.g. top layer 5, Fig. 8).
Claim 14: Umeda discloses the wiring harness production method according to claim 1, further comprising Step S15 performed after Step S10, wherein Step S15 comprises providing an insulating layer (e.g. either top or bottom protective layer 7, Fig. 8) on a surface of the substrate.
Umeda does not teach Step S10, preparing a printing plate; and that within Step S30, the printing of the conductive ink onto the substrate is done by the printing plate.
Lochun discloses an art-recognized equivalent wiring harness production method that includes providing a substrate (e.g. 110, Fig. 1B), printing a conductive ink (e.g. 120) onto the substrate, and coagulating (solidifying/drying) the conductive ink to form a conductive loop (e.g. 120, Fig. 1A). In printing the conductive ink, Lochun first prepares a printing plate (e.g. letterpress plate, ¶ [0018]), then subsequently the printing is carried out by using the printing plate (e.g. ¶¶ [0020], [0040], [0041]).
Regarding Claim 11, Lochun further teaches that coagulation (solidifying/drying) of the conductive ink can be done by infrared radiation drying (e.g. ¶ [0053]).
Lochun teaches that the use of the printing plate to print the conductive ink and the infrared radiation drying, has several associated advantages within the manufacturing process, e.g. formation of conductive loops with a higher resolution, faster set-up and production run times, improved cross-linking between the conductive ink and substrate, etc. (e.g. ¶¶ [0019], [0032], [0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Umeda by utilizing the printing plate and infrared coagulation within the processes taught by Lochun, for anyone, or all, of the associated advantages taught by Lochun.
Regarding Claims 6 and 7, both Umeda and Lochun teach a spatial wiring harness based on the conductive ink forming spaced conductive loops. Lochun further teaches that an alternative printing process in printing the conductive ink can be done by flexographic printing where a flexographic printing plate can be used in lieu of a letterpress printing plate (e.g. ¶¶ [0021] to [0023]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the flexographic printing plate for the letterpress printing plate, as taught by Lochun, to use achieve the very same process of printing a conductive ink onto the substrate having the same purpose.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Lochun, as applied to Claim 1 above, and further in view of U.S. Publication 2016/0111795 to Ishikawa (hereinafter “Ishikawa”).
Umeda, as modified by Lochun, discloses the claimed wiring harness production method as relied upon above in Claim 1. The modified Umeda method does not teach that the method further comprises Step S60, where Step S60 is performed after Step S50, wherein Step S60 comprises printing the conductive ink onto the insulating protective layer by the printing plate; and Step S60, Step S40 and Step S50 are alternately performed one or more times in sequence.
Ishikawa discloses a wiring harness product method where a conductive loop (e.g. standard coil, Fig. 6B) is formed on an insulating protective layer (e.g. first layer, Fig. 6B), which is alternately performed multiple times in sequence to form a stacked wiring harness (e.g. first layer, small coil, second layer, standard coil, etc., ¶¶ [0113] to [0120). The benefit of such a wiring harness provides additional applications where the harness can transmit and receive data wirelessly (e.g. ¶ [0002]).
Ishikawa is analogous to Umeda in that each form art-recognized equivalent conductive loops (e.g. antenna circuits). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have repeated the processes of Umeda of utilizing the printing plate and insulating protective layers multiple times to print additional conductive ink (conductive loops) and insulative protective layers, as taught by Ishikawa, to provide the wiring harness with at least the application of transmitting and receiving data wirelessly.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Lochun, as applied to Claim 1 above, and further in view of U.S. Publication 2019/0042907 to Buyukkalender et al (hereinafter “Buyukkalender”).
Umeda, as modified by Lochun, discloses the claimed wiring harness production method as relied upon above in Claim 1. The modified Umeda method does not teach Step S90 that is performed after Step S50, wherein Step S90 comprises welding connecting terminals at a tail end of the conductive loop.
Umeda does teach that the wiring harness includes a component (e.g. 14, Fig. 14) that is electrically connected to a tail end of the conductive loop to form an integrated circuit. Buyukkalender teaches a Step S90 where connecting terminals of a component (e.g. capacitor, Fig. 5B) are welded to a tail end of a conductive loop (e.g. S1, Fig. 5C) to complete the integrated circuit (e.g. ¶¶ [0065], [0066]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Umeda by adding S90 after a component is mounted on the insulative protective layer to connect the terminals of the component by welding the terminals to the tail end of the conductive loop, as taught by Buyukkalender, to completed the integrated circuit with the component.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Lochun, as applied to Claim 1 above, and further in view of U.S. Publication 2017/0155185 to Hong et al (hereinafter “Hong”).
Umeda, as modified by Lochun, discloses the claimed wiring harness production method as relied upon above in Claim 1. The modified Umeda method does not teach Step S110 that comprises providing a heat sink on the insulating protective layer.
Hong discloses a method of making a wiring harness that includes an art-recognized conductive loop (e.g. 210, Fig. 2A). Hong teaches providing a heat sink (e.g. Fig. 2A) onto an insulating protective layer (e.g. 200, ¶ [0054]) to dissipate heat from the wiring harness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Umeda by adding a heat sink after forming the insulating protective layer, or on the insulative protective layer, as taught by Hong, to positively dissipate heat from the wiring harness.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Lochun, as applied to Claim 1 above, and further in view of U.S. Publication 2017/0295651 to Kanehara et al (hereinafter “Kanehara”).
Umeda, as modified by Lochun, discloses the claimed wiring harness production method as relied upon above in Claim 1. The modified Umeda method does not teach that within Step S10, machining is used to process and manufacture the printing plate.
Kanehara discloses a method of making a printing plate (e.g. 11, Fig. 1) by chemical machining (e.g. irradiation, curing, molding, etc.) to provide the plate with the necessary shape in printing conductive inks (e.g. ¶¶ [0046] to [0048]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Umeda by forming the printing plate with chemical machining, as taught by Kanehara, to positively shape the printing plate for forming conductive ink.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Umeda in view of Lochun, as applied to Claim 1 above, and further in view of U.S. Patent 6,353,420 to Chung (hereinafter “Chung”).
Umeda, as modified by Lochun, discloses the claimed wiring harness production method as relied upon above in Claim 1. The modified Umeda method does not teach within Step S50, how the insulating protective layer is specifically formed.
Chung teaches that a protective layer (e.g. 58, Fig. 6) of electrically insulating materials that is formed around and on a surface of a conductive loop, can be formed by coating (e.g. roll coating, col. 11, lines 1-15) to cover and protect the conductive loop.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to formed the insulating protective layer of Umeda by one process of coating, as taught by Chung, to accurately pattern the insulating materials over the conductive loop.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter.
Regarding Claim 3, Umeda does teach punching a hole (e.g. 3) in the substrate. However, neither Umeda, nor the prior art, discloses punching a hole in the insulating protective layer or the conductive loop.
Regarding Claim 4, the prior art does not teach printing a lower shielding layer or upper shielding layer.
Regarding Claim 9, the prior art does not teach providing sheaths at a tail end of the conductive loop.
Moreover, it would not have been obvious to modify Umeda by adding any of the features to Umeda’s wiring harness production method because to do so would destroy the overall structure of the substrate and conductive loop.
Accordingly, Claims 3, 4 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a) Japanese Patent Publication, JP 2016-101669 discloses a wiring harness production method (e.g. Figs. 1, 2) that includes printing and coagulating conductive ink with a printing plate (e.g. 2, see SOLUTION).
b) Non-Patent Literature IEEE Publication to Furukawa, T., entitled "Printing technology for electronics", discloses a wiring harness production method (see entire document) that includes printing and coagulating conductive ink with a printing plate (e.g. Figures 8 and 12).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to A. DEXTER TUGBANG whose telephone number is (571)272-4570. The examiner can normally be reached Mon - Fri 8:00 am to 5:00 pm.
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/A. DEXTER TUGBANG/ Primary Examiner
Art Unit 2896