DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the limitation "The time-register circuit arrangement according to Claim 1" in line 1. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this examination, this limitation will be interpreted as “The circuit arrangement according to Claim 1”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Powell et al. (US 10,673,383 B1).
Regarding Claim 1 and equivalent method Claim 19, Powell et al. teaches in Figure 7 a circuit arrangement configured to:
discard charges from a capacitive circuit element of the circuit arrangement based on a width of one or more signal pulses of an input signal being provided to the circuit arrangement (using capacitor 112), with the rate at which the charges are discarded being dependent on at least one control signal being provided to the circuit arrangement (using control signals at switches S1 and S2; using tuning signal to further adjust capacitor 112); and
provide an output signal flank having a delay relative to a readout signal flank being provided to the circuit arrangement (to an input of comparator 118), with the delay being based on the charges stored in the capacitive circuit element at the time the readout signal flank is provided to the circuit arrangement (where comparator 118 is based on input, including from capacitor 112).
Regarding Claim 2, Powell et al. further teaches the time-register circuit arrangement, wherein the capacitive circuit element is a tunable capacitive circuit element (Col. 13, lines 12-13: “variable capacitor 112”),
wherein the circuit arrangement is configured to vary the rate at which the charges are discarded by controlling a capacitance of the tunable capacitive circuit element based on the at least one control signal (using control signals at switches S1 and S2; using a tuning signal to further adjust capacitor 112).
Regarding Claim 3, Powell et al. further teaches the circuit arrangement, wherein the charges are discarded via a resistive circuit element of the circuit arrangement (using resistor 114).
Regarding Claim 4, Powell et al. further teaches the circuit arrangement, wherein the resistive circuit element is a tunable resistive circuit element (Col. 13, line 13: “variable resistor 114”), wherein the circuit arrangement is configured to vary the rate at which the charges are discarded by controlling an electrical resistance of the tunable resistive element based on the at least one control signal (using control signals at switches S1 and S2; using a tuning signal to further adjust resistor 114).
Regarding Claim 5, Powell et at. further teaches the circuit arrangement, comprising an output circuit element (comparator 118), wherein the output circuit element is configured to provide the output signal flank having the delay relative to the readout signal (based on the inputs including from capacitor 112).
Regarding Claim 6, Powell et al. further teaches the circuit arrangement, wherein the circuit arrangement is configured to discard the charges remaining in the capacitive circuit element in response to the readout signal flank (based on control signals at switches S1 and S2),
wherein the output circuit element is a comparator circuit (comparator 118), configured to trigger the output signal flank when a voltage representing the charges remaining in the capacitive circuit element reaches a voltage threshold (based on the signals inputted into comparator 118).
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (“A Type-II Analog PLL with Time-Domain Processing”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 22, 2021, 5 pages), as cited in the IDS 01/30/2024.
Regarding Claim 20, Yin et al. teaches in Figure 3(a) a method for operating a Time-mode Arithmetic Unit, TAU, circuit arrangement, comprising:
converting a time-mode input signal comprising at least a first pair of input signal flanks to a first and a second input signal (converting CLK_REF and CLK_FB to UP and DW signals),
the first and second input signals each comprising at least a first signal pulse having a pulse width being based on a delay between the flanks of the first pair of input signal flanks (using the flip-flop delay between CLK_REF and UP and using the flip-flop delay between CLK_FB and DW);
discarding charges from a first capacitive circuit element based on a width of at least the first pulse of the first input signal (where Figure 2(b) further details the time adder includes capacitor C1 within the time register TR1 is based on the first input signal (see V_C1 of Figure 2(c));
discarding charges from a second capacitive circuit element based on a width of at least the first pulse of the second input signal (where Figure 2(b) further details the time adder includes capacitor C1 within the time register TR2 is based on the first input signal (see V_C1 of Figure 2(c));
providing a flank of a pair of output signal flanks (OUTA) having a delay (Delta To, TR) relative to a readout signal flank (RPC), with the delay being based on the charges stored in the first capacitive circuit element at the time the readout signal flank is provided (as based on capacitor C1 of time register TR1 (see Figure 2(b));
providing the other flank of the pair of output signal flanks (OUTB) having a delay (Delta To, TR) relative to the readout signal flank (RPC), with the delay being based on the charges stored in the second capacitive circuit element at the time the readout signal flank is provided (as based on capacitor C1 of time register TR2 (see Figure 2(b));
providing a time-mode output signal comprising the pair of output signal flanks (OUTA, OUTB).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. (“A Type-II Analog PLL with Time-Domain Processing”, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May 22, 2021, 5 pages), as cited in the IDS 01/30/2024, and further in view of Powell et al. (US 10,673,383 B1), as applied to Claim 1 above.
Regarding Claim 7, Yin et al. teaches in Figure 3(a) a Time-mode Arithmetic Unit, TAU, circuit arrangement, comprising:
at least a first and a second circuit arrangement (U1, U4 and U2, U3); and
control circuitry (Phase detector) configured to:
convert a time-mode input signal comprising at least a first pair of input signal flanks to a first and a second input signal (converting CLK_REF and CLK_FB to UP and DW signals),
the first and second input signal each comprising at least a first signal pulse having a pulse width being based on a delay between the flanks of the first pair of input signal flanks (using the flip-flop delay between CLK_REF and UP and using the flip-flop delay between CLK_FB and DW),
provide the first and second input signal to the first and second circuit arrangement (where UP signal is received at U1 + U4 arrangement and where DW signal is received at U2 + U3 arrangement), and
provide a time-mode output signal comprising a pair of output signal flanks based on respective output signals of the first and second circuit arrangements (as outputted by U4 and U3);
but does not explicitly teach at least a first and a second circuit arrangement according to claim 1.
Powell et al. teaches the circuit arrangement according to Claim 1 (see Claim 1 rejection).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the circuit arrangement of Powell et al. with each of the first and second circuit arrangements in Yin et al. for the purpose of providing easier design and simpler frequency calibration. Powell et al. Col. 13, lines 64-65.
Regarding Claim 8, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control circuitry is configured to provide, if the time-mode input signal further comprises at least one further pair of input signal flanks, each of the first and second input signals with at least one further signal pulse having a pulse width being based on a delay between the signal flanks of the at least one further pair of input signal flanks (as based on the feedback delay from the AND gate and inverter to each of the reset nodes R on each flip-flop).
Regarding Claim 9, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the TAU circuit arrangement is configured to perform a time-mode summation of the delay between the signal flanks of the first pair of input signal flanks and the delay between the signal flanks of the at least one further pair of input signal flanks, with the delay between the pair of output signal flanks representing the result of the time-mode summation (as based on the feedback delay from the AND gate and inverter to each of the reset nodes R on each flip-flop; see also signal generator circuit arrangement).
Regarding Claim 10, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control circuitry is configured to provide at least one control signal to the first and second circuit arrangement (inputs to U1 and U2, as outputted by signal generator), the at least one control signal being configured to control the rate at which charges are being discarded from a capacitive circuit element of the respective circuit arrangements (where each circuit arrangement is further taught by Powell to include an adjustable capacitor 112, which charges and discharges based in part on S1 and S2).
Regarding Claim 11, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control circuitry is configured to provide the control signal during at least a first time interval and a final time interval, the first time interval encompassing the first signal pulses being provided as part of the first and second input signal and the final time interval encompassing a time between the readout signal flank and the provision of the pair of output signal flanks of the output signal (using the phase detector and signal generator circuit configuration).
Regarding Claim 12, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control circuitry is configured to provide the control signal further during at least one further time interval between the first and the final time interval (using the phase detector and signal generator circuit configuration),
the at least one further time interval encompassing at least one further signal pulse being provided as part of each of the first and second input signal (as based on the feedback delay from the AND gate and inverter to each of the reset nodes R on each flip-flop; see also signal generator circuit arrangement).
Regarding Claim 13, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, where Yin et al. further teaches the TAU circuit arrangement, wherein the control signal provided during the first and at least one further time intervals acts as weighting factor, influencing the amount of charges being discarded in response to the first and at least one further signal pulses included in the first and second input signal (using the phase detector and signal generator circuit configuration, wherein the phase detector generates signals based on at least CLK_REF and CLK_FB).
Regarding Claim 14, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the TAU circuit arrangement is configured to perform a time-mode weighted summation of the delay between the signal flanks of the first pair of input signal flanks and the delay between the signal flanks of the at least one further pair of input signal flanks, weighted by the weighting factor, with the delay between the pair of output signal flanks representing the result of the time-mode weighted summation (using the phase detector and signal generator circuit configuration).
Regarding Claim 15, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control signal provided during the final time interval acts as scaling factor, influencing a time delay between the pair of output signal flanks, wherein the TAU circuit arrangement is configured to perform a time-mode summation of the delay between the signal flanks of the first pair of input signal flanks and the delay between the signal flanks of the at least one further pair of input signal flanks, with the delay between the pair of output signal flanks representing the result of the time-mode summation, multiplied by the scaling factor (using the phase detector and signal generator circuit configuration).
Regarding Claim 16, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the TAU circuit arrangement, wherein the control circuitry is configured to switch between generating signal pulses having a wider pulse width for the first input signal and generating signal pulses having a wider pulse width for the second input signal based on a sign setting signal being provided to the TAU circuit arrangement (based in part on the inputted signals to the phase detector).
Regarding Claim 17, Yin et al. and Powell et al. as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches an All-Digital Phase-Locked Loop, ADPLL, circuit arrangement comprising the TAU circuit arrangement (see Figure 7).
Regarding Claim 18, Yin et al. and Powell et al., as a whole, teach all the limitations of the present invention, wherein Yin et al. further teaches the ADPLL circuit arrangement, wherein the TAU circuit arrangement is configured to capture an offset between an oscillator signal and a signal flank of a reference signal of the ADPLL circuit arrangement (using CLK_REF and CLK_FB signals).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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/DIANA J. CHENG/ Primary Examiner, Art Unit 2849