DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/30/24 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 recites the limitation "the change mode of data" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim 11 recites the limitation "the change mode of data" in line 11. There is insufficient antecedent basis for this limitation in the claim.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Regarding claim 1,
a first means – Evaluation line, data extraction. The specification explicitly describes extracting brightness or other data along an evaluation line crossing the chip boundary, and refers to this as 'first means' (see [0040], [0077]). The extraction process and its implementation (e.g., HSV conversion, line selection) are described in sufficient detail.,
a second means – Edge detection, pulse width, optimal image selection
The specification details the process for evaluating the change mode (sharpness, edge detection, pulse width after binarization/differentiation) and selecting the optimal image, and labels this as 'second means' ([0046], [0078]).
a third means – Comparison to standard image, feature extraction, similarity, deep learning option. The specification describes comparing the optimal image to a standard/reference image, using feature extraction, similarity metrics, and potentially deep learning, and labels this as 'third means' ([0050]–[0052], [0079])
Regarding claim 11,
a first step - Evaluation line, data extraction. The specification explicitly describes extracting brightness or other data along an evaluation line crossing the chip boundary, and refers to this as 'first means' (see [0040], [0077]). The extraction process and its implementation (e.g., HSV conversion, line selection) are described in sufficient detail.,
a second means – Edge detection, pulse width, optimal image selection
The specification details the process for evaluating the change mode (sharpness, edge detection, pulse width after binarization/differentiation) and selecting the optimal image, and labels this as 'second means' ([0046], [0078])
a third means – Comparison to standard image, feature extraction, similarity, deep learning option. The specification describes comparing the optimal image to a standard/reference image, using feature extraction, similarity metrics, and potentially deep learning, and labels this as 'third means' ([0050]–[0052], [0079])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voges et al US 9062859 in view of Satake et al US 20040248329.
Regarding claim 1, Voges et al teaches an apparatus for determining a semiconductor chip, the apparatus comprising:
an imaging device that reciprocates obliquely above the semiconductor chip disposed on a light-reflective mounting surface to capture an image of the semiconductor chip's end surface (Sensor 120, being located above the wafer W and directed generally downward, may capture an image of resist layer 133. Sensor 120 may be arranged such that an optical axis thereof is substantially normal to the surface of the wafer W or inclined at an oblique angle (column, lines 5-12), and a determination device that determines the quality of the semiconductor chip based on the image captured by the imaging device (illumination are used to identify different types of defects or features on a wafer W. Brightfield illumination, involves directing light onto a surface being imaged in such a manner that the light, upon specular reflection, will be directed into or collected by the imager. Under brightfield illumination conditions, contrast in an image is obtained through the scattering of incident light onto optical paths that are not collected by an imager. Accordingly, the object being imaged appears bright and defects or discontinuities that scatter light appear dark, i.e. dark against a bright field (column 5, lines 30-41),
Voges et al fails to teach wherein the determination device comprises:
a first means for extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device;
a second means for identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images;
a third means for determining the quality of the semiconductor chip by assessing the optimal image identified by the second means based on a previously captured standard image;
Satake et al teaches wherein the determination device comprises:
a first means for extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device (Any defects can be detected by comparing the obtained image data to a reference pattern, and further a line width evaluation signal may be extracted by moving the pattern to be evaluated on the wafer 608 to the vicinity of the optical axis of the primary optical system (paragraph 0043);
a second means for identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images (The secondary electrons or the reflected electrons 211 having the information on the pattern image and emanated from the sample 210 are magnified by the lenses 209, 208, and is turned into electric signals, which signals are obtained as a series of images in an image display section 219. Further, said image is compared on time to a plurality of cell images or to a plurality of die images, thereby detecting any defective conditions on a surface of a sample (e.g., a wafer) (paragraph 0051); and
a third means for determining the quality of the semiconductor chip by assessing the optimal image identified by the second means based on a previously captured standard image (This image data may be compared to the reference image data of the sample including no defective portion to detect any defects on the sample 712 (paragraph 0049).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Voges et al to include: wherein the determination device comprises: a first means for extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device;
a second means for identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images;
a third means for determining the quality of the semiconductor chip by assessing the optimal image identified by the second means based on a previously captured standard image;.
The reason of doing so would be to accurately determine the quality of semiconductor chip.
Regarding claim 2, Voges et al in view of Satake et al teaches wherein the imaging device reciprocates at a tilt angle of 200 to 400 with respect to the mounting surface (Voges et al: darkfield illumination can be at any angle and azimuth of incidence upon the wafer W so long as the incident light is not specularly reflected into the sensor being used to image the wafer W (column , lines 27-30).
Regarding claim 3, Voges et al in view of Satake et al teaches wherein the imaging device captures a magnified image of a predetermined magnification (Satake et al: the secondary optical system has magnifying lenses 609, 610, and the secondary electron beams after having passed through those magnifying lenses are formed into an image on a second multi-aperture plate 611 (paragraph 0042).
Regarding claim 5, Voges et al in view of Satake et al wherein the data on the evaluation line is brightness data (detectors 612 converts the received secondary electron beam to an electric signal representing an intensity thereof. The electric signal from each of the detectors 612 is amplified by an amplifier 613 and then converted into an image data in an image processing unit 614. a line width evaluation signal may be extracted by moving the pattern to be evaluated on the wafer 608 to the vicinity of the optical axis of the primary optical system through the registration so as to apply a line scanning thereto (paragraph 0043).
Regarding claim 8, Voges et al in view of Satake et al teaches wherein the imaging device is reciprocally movable on a horizontal plane (Voges et al: the act of focusing the camera 123 at a particular location on the wafer edge 130 involves moving lens 150 along optical axis 125 as indicated by arrow 129 (column 5, lines 4-9).
Regarding claim 9, Voges et al in view of Satake et al teaches wherein the semiconductor chip is arranged in a staggered manner in a plan view, so that a gap in the direction of the illumination light is widely secured (Satake et al: A wafer 53 prepared as a sample is fixedly mounted on the moving stage 55 with the guard ring 54 surrounding the periphery thereof. The guard ring 54 has the same height (thickness) as the wafer 53 by taking into consideration that a small gap 57 between the top end of the differential pumping section 52 and the wafer 53 and guard ring 54 should be kept constant even during the stage being moved (paragraph 0036).
Regarding claim 10, Voges et al in view of Satake et al teaches wherein a plurality of quality determination regions including a standard determination region are specified in the semiconductor chip, an optimal image is selected from the plurality of captured images corresponding to the optimal image of the standard determination region (Voges et al: Baffles 168 are particularly useful where a sensor 120 or 124 is used to image regions 132 or 136 (column 6, lines 30-33). the concatenation process selects those portions of each of a set of registered images that is substantially in focus and places them in the resulting composite image (column 7, lines 25-28).
Regarding claim 11, Voges et al teaches a method for determining a semiconductor chip using an imaging device and a determination device:
the imaging device that reciprocates obliquely above the semiconductor chip disposed on a light-reflective mounting surface to capture an image of the semiconductor chip's end surface (Sensor 120, being located above the wafer W and directed generally downward, may capture an image of resist layer 133. Sensor 120 may be arranged such that an optical axis thereof is substantially normal to the surface of the wafer W or inclined at an oblique angle (column, lines 5-12), the determination device that determines the quality of the semiconductor chip based on the image captured by the imaging device (illumination are used to identify different types of defects or features on a wafer W. Brightfield illumination, involves directing light onto a surface being imaged in such a manner that the light, upon specular reflection, will be directed into or collected by the imager. Under brightfield illumination conditions, contrast in an image is obtained through the scattering of incident light onto optical paths that are not collected by an imager. Accordingly, the object being imaged appears bright and defects or discontinuities that scatter light appear dark, i.e. dark against a bright field (column 5, lines 30-41),
Voges et al fails to teach wherein the method comprises:
a first step of extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device;
a second step of identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images;
a third step of determining the quality of the semiconductor chip by assessing the optimal image identified by the second step based on a previously captured standard image
Satake et al teaches wherein the method comprises:
a first step of extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device (Any defects can be detected by comparing the obtained image data to a reference pattern, and further a line width evaluation signal may be extracted by moving the pattern to be evaluated on the wafer 608 to the vicinity of the optical axis of the primary optical system (paragraph 0043);
a second step of identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images (The secondary electrons or the reflected electrons 211 having the information on the pattern image and emanated from the sample 210 are magnified by the lenses 209, 208, and is turned into electric signals, which signals are obtained as a series of images in an image display section 219. Further, said image is compared on time to a plurality of cell images or to a plurality of die images, thereby detecting any defective conditions on a surface of a sample (e.g., a wafer) (paragraph 0051); and
a third step of determining the quality of the semiconductor chip by assessing the optimal image identified by the second step based on a previously captured standard image (This image data may be compared to the reference image data of the sample including no defective portion to detect any defects on the sample 712 (paragraph 0049).
Therefore, it would have been obvious to one of ordinary skill in the art to modify Voges et al to include: wherein the determination device comprises: wherein the method comprises: a first step of extracting data on an evaluation line continuous inside and outside of the semiconductor chip from each of a plurality of images captured during the movement of the imaging device;
a second step of identifying an optimum image from the plurality of images by evaluating the change mode of data on the evaluation lines for each of said images;
a third step of determining the quality of the semiconductor chip by assessing the optimal image identified by the second step based on a previously captured standard image
The reason of doing so would be to accurately determine the quality of semiconductor chip.
Allowable Subject Matter
Claims 4, 6 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication should be directed to Michael Burleson whose telephone number is (571) 272-7460 and fax number is (571) 273-7460. The examiner can normally be reached Monday thru Friday from 8:00 a.m. – 4:30p.m. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Akwasi Sarpong can be reached at (571) 270- 3438.
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Michael Burleson
Patent Examiner
Art Unit 2681
Michael Burleson
April 4, 2026
/MICHAEL BURLESON/
/AKWASI M SARPONG/ SPE, Art Unit 2681 4/7/2026