DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-19 and 21 are pending.
Response to Amendment
Applicants’ response to the last Office Action, dated Aug. 16, 2026, has been entered and made of record. In view of the Applicant’s amendments of the title, the objection to the specification is expressly withdrawn.
Response to Arguments
Applicant’s Argument has been fully considered, and Examiner respectfully submits that the applicant’s arguments are not persuasive.
As to claim 1, it has been amended to further recite “wherein a width of each of the through holes in the second direction is greater than the width of the clock signal line in the second direction”; and Applicant argues (Remarks, p. 12)
However, as shown in FIG. 5 of Lu, the width of the overlapping portion is not equal to the width of the signal line CK1 in the second direction, and further, Lu does not disclose that the sum of the overlapping areas are the product of the width of the signal line 110 in the second direction, the length of the vent hole in the first direction, and the number of vent holes in the repeating unit. In fact, Lu does not mention anything about the relationship between the width of the vent hold and the width of the signal line.
Examiner respectfully disagrees. Lu does mention “the relationship between the width of the vent hold and the width of the signal line”, and teaches that a width of each of the through holes in the second direction is greater than the width of the clock signal line in the second direction (Lu, FIG. 5, [0059], “the maximum size of the vent hole 131 in the width direction of the first signal line 110 may be greater than the width of any of the first signal lines 110. For example, as shown in FIG. 5, the side length d of the vent hole 131 is greater than the width w of the first signal line 110”).
Accordingly, claim 1 is not allowable.
As to claim 2, it depends from claim 1, and is not allowable at least for the same reason above.
As to claims 3-13, they remain allowable. Please see the allowable subject matter for detailed analysis.
As to claim 14, it has been amended in the same manner as in claim 1 (Remarks, p. 13), and is not allowable for the same reason above. Please see claim 1 for detailed analysis.
As to claim 15, it depends from claim 14, and is not allowable at least for the same reason above.
As to claims 16-19, they remain allowable. Please see the allowable subject matter for detailed analysis.
As to new claim 21, it is persuasive that “the newly added claim 21 includes the limitations in the base claim 1 and the allowable claim 3” (Remarks, p. 13), and is allowed. Please see the allowable subject matter for detailed analysis.
Examiner maintains his decision, and provides succinct explanation as described above.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office Action.
Claims 1-2 and 14-15 are under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2022/0149138 A1).
As to claim 1, Lee discloses a display panel (Lu, FIG. 1, [0033], “OLED display substrate”), comprising a display area (Lu, FIGS. 1-2, [0035], “display area 10”) and a driving circuit area (Lu, FIGS. 1-2, [0035], “peripheral area 20” comprising, e.g., “gate on array (GOA) circuit”) disposed on at least one side of (Lu, see FIGS. 1-2, e.g., on left side) the display area (Lu, FIGS. 1-2, [0035], “display area 10”), and comprising:
a plurality of clock signal lines (Lu, FIGS. 1-3, [0036], e.g., “signal lines 1000 disposed in the source/drain layer 101 generally include … clock signal lines arranged in pairs (a high-level clock signal line CK and a low-level clock signal line CB)”), disposed in the driving circuit area (Lu, FIGS. 1-2, [0035], “peripheral area 20” comprising, e.g., “gate on array (GOA) circuit”) and each extending along a first direction (Lu, see FIGS. 1-3, vertical direction);
a low-potential signal line (Lu, FIG. 3, [0038], “VSS line 130”), disposed in the driving circuit area (Lu, FIGS. 1-2, [0035], “peripheral area 20”), wherein an orthographic projection of the plurality of the clock signal lines (Lu, FIG. 3, [0037], “first signal lines 110” comprising “CK1 CB1” and second signal lines 120” comprising “CK2 CB2”; [0036], “a high-level clock signal line CK and a low-level clock signal line CB”) on the low-potential signal line (Lu, FIG. 3, [0038], “VSS line 130”) is located within the low-potential signal line (Lu, see FIG. 3, [0038], “VSS line 130”);
wherein the low-potential signal line (Lu, see FIG. 3, [0038], “VSS line 130”) is provided with a plurality of through holes (Lu, FIG. 3, [0037], “vent hole 131”) arranged in an array to define a plurality of repeating units (Lu, e.g., see FIGS. 3 and 7);
in each of the repeating units, a number of the through holes (Lu, FIG. 3, [0037], “vent hole 131”) in each column is the same (Lu, e.g., see FIGS. 3 and 7);
for any two of the clock signal lines, an overlapping area of one of the clock signal lines and all corresponding ones of the through holes in one of the repeating units is equal to an overlapping area of the other one of the clock signal lines and all corresponding ones of the through holes in one of the repeating units (Lu, see FIG. 5, [0050], “the overlapping areas between two first signal lines 110 in one pair of first signal lines 110 and the projection pattern of the vent hole may be made equal in a plurality of implementations”), and
an overlapping area of any one of the clock signal lines and corresponding ones of the through holes in one of the repeating units is equal to a product of a width of one of the clock signal lines in a second direction (Lu, e.g., FIG. 5, horizontal direction), a length of one of the through holes in the first direction, and a number of the through holes in one column in one of the repeating units (Lu, FIG. 5, [0059], “the maximum size of the vent hole 131 in the width direction of the first signal line 110 may be greater than the width of any of the first signal lines 110. For example, as shown in FIG. 5, the side length d of the vent hole 131 is greater than the width w of the first signal line 110”), wherein a width of each of the through holes in the second direction is greater than the width of the clock signal line in the second direction (Lu, FIG. 5, [0059], “the maximum size of the vent hole 131 in the width direction of the first signal line 110 may be greater than the width of any of the first signal lines 110. For example, as shown in FIG. 5, the side length d of the vent hole 131 is greater than the width w of the first signal line 110”); and
an angle between the first direction and the second direction (Lu, FIG. 5, horizontal direction) is greater than 0 and less than or equal to 90 degrees (Lu, e.g., see FIG. 5, 90°).
As to claim 2, Lu discloses the display panel according to claim 1, wherein the through holes (Lu, FIG. 3, [0037], “vent hole 131”) in each column are arranged along the first direction, and the through holes in adjacent two rows are spaced in the first direction (Lu, e.g., see FIG. 7).
As to claim 14, it differs from claim 1 only in that it is the display device comprising the display panel of claim 1. It recites substantially the same limitations as in claim 1, and Lu discloses them. Please see claim 1 for detailed analysis.
As to claim 15, it recites substantially the same limitations as in claim 2, and Lu discloses them. Please see claim 2 for detailed analysis.
Allowable Subject Matter
Claims 3-13 and 16-19 remain allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 3, Lu teaches the display panel according to claim 1, wherein a number of columns (Lu, e.g., FIG. 7, # of columns = 4) of the through holes (Lu, FIG. 7, [0037], “vent hole 131”) is equal to a number of the clock signal lines (Lu, e.g., FIG. 7, [0071], # of clock signal lines = 4 (CK1, CB1, CK2, CB2)).
However, the closest known prior art, i.e., Lu et al. (US 2022/0149138 A1), Lu et al. (US 2023/0021618 A1), Lu et al. (US 2024/0423046 A1), Lu et al. (US 2024/0206266 A1), Lee et al. (US 2018/0032189 A1), Bang et al. (US 2021/0118963 A1), Lhee et al. (US 2019/0148469 A1), Kim et al. (US 2018/0033830 A1), Kim et al. (US 2019/0237533 A1), alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “each column of through holes is arranged corresponding to one of the clock signal lines, each of the through holes is arranged symmetrically about a center axis of a corresponding one of the clock signal lines, a distance between an end of each of the through holes corresponding to one of the clock signal lines close to another one of the clock signal lines and the another one of the clock signal lines is greater than or equal to a maximum offset of the through holes, and a width of a portion of each of the through holes beyond the corresponding one of the clock signal lines is greater than or equal to the maximum offset of the through holes”.
As to claims 4-5, they directly or indirectly depend from claim 3, and are allowable at least for the same reason above.
As to claim 6, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “each column of through holes is arranged corresponding to one of the clock signal lines; in each of the repeating units, minimum distances of two ends of each of the through holes from a corresponding one of the clock signal lines are different; for any two of the clock signal lines, a minimum distance between one end of each of the through holes and the corresponding one of the clock signal lines is equal, and a minimum distance between the other end of each of the through holes and the corresponding one of the clock signal lines is equal”.
As to claims 7-8, they directly or indirectly depend from claim 6, and are allowable at least for the same reason above.
As to claim 9, Lu teaches the display panel according to claim 1,wherein the through holes (Lu, FIG. 5, [0072], “vent holes 131”) comprise first through holes (Lu, FIG. 5, [0072], “vent holes 131” on “CK1 and CB1”) each corresponding to two adjacent ones of the clock signal lines (Lu, FIG. 5, [0076], “the leftmost pair of first signal lines 110 and the rightmost pair of first signal lines 110 are configured to be both overlapped with the projections of the same column of vent holes 131”).
However, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “second through holes each corresponding to one of the clock signal lines; along the first direction, for two adjacent columns of the through holes, one end of each of the through holes in one column close to the other column is located on a same straight line as one end of each of the through holes in the other column”.
As to claims 10-13, they directly or indirectly depend from claim 6, and are allowable at least for the same reason above.
As to claims 16-18, they recite substantially the same limitations as in claims 3-5, respectively, and are allowable for the same reasons above. Please see claims 3-5 for detailed analysis.
As to claim 19, it recites substantially the same limitations as in claim 6, and is allowable for the same reasons above. Please see claim 6 for detailed analysis.
New claim 21 is allowed.
The following is an examiner’s statement of reasons for allowance:
As to claim 21, the closest known prior art indicated above, alone or in reasonable combination, fails to teach limitations in consideration of the claims as a whole, specifically with respect to the limitations “each column of through holes is arranged corresponding to one of the clock signal lines, each of the through holes is arranged symmetrically about a center axis of a corresponding one of the clock signal lines, a distance between an end of each of the through holes corresponding to one of the clock signal lines close to another one of the clock signal lines and the another one of the clock signal lines is greater than or equal to a maximum offset of the through holes, and a width of a portion of each of the through holes beyond the corresponding one of the clock signal lines is greater than or equal to the maximum offset of the through holes”.
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant’s disclosure: Lee et al. (US 2020/0264722 A1) teaches the concept of “a circuit layer having a driving circuit layer with a plurality of clock signal lines” (Abs.).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD J HONG whose telephone number is (571) 270-7765. The examiner can normally be reached on 9:00 AM to 6:00 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on (571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Oct. 1, 2026
/RICHARD J HONG/Primary Examiner, Art Unit 2623
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