DETAILED ACTION
This action is responsive to the amendments filed 26 Dec 2025. Claims 1-19 and 21 are pending. Claims 1, 8, and 20 are independent.
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Foreign Priority Claim
Acknowledgment is made of applicant’s claim for foreign priority. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
The Amendment filed 26 Dec 2025 has been entered. Claims 1-19 and 21 are currently pending in the application.
Response to Arguments
Examiner agrees that this amendment has overcome the previous rejection. Applicant’s arguments with respect to the claims have been considered but are moot because the arguments do not apply to the citations being used in the current rejection.
Allowable Subject Matter
Claims 13 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5 – 7 have been rejected under 112(a) (see below). If the 112(b) rejection is successfully overcome by amendment, then it is likely that claims 5-7 would be objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 2-7 is/are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 2 states, “the operating state signal”. However, this limitation has been amended in claim 1 and no longer exists as an antecedent. Therefore, there is insufficient antecedent basis for this limitation in the claim.
Claim 4 states, “an input signal”. This claim is indefinite because it is unclear if this is the same “input signal” from claim 1, or a new, different input signal.
Claim(s) 3-7 depend on rejected claim(s) 2 and/or 4 and are also rejected under 35 U.S.C. 112(b).
Claim Rejections – 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless —
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 4, 8 – 12, 20, and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by BHATI, et al, U.S. Patent Application Publication 2023/0395108 (“BHATI”).
Regarding claim 1, BHATI teaches:
(Currently Amended) A memory device comprising: a command decoder configured to generate a command by decoding an input signal applied to a first pad, (BHATI, fig 2A, 2B, 8A-8E, “[0053] The memory device 200 may include a storage controller 102 and a memory array 202 comprised of a number of memory dies 104a-n, [0097] FIG. 2C is a block diagram of example memory system 200 that depicts more details of one embodiment of memory die 104a. [0181] FIGS. 8A-8E also illustrate a flow of control signals between a storage controller 802 and a memory die 804a. Control signals are transmitted from a memory interface circuit 834 to a I/O circuit 822, and may be implemented to enable or disable memory dies of the memory array 801.”; a memory device with a I/O circuit 634 (i.e. first pad), with storage controller 602 with CE multiplexor 639 (i.e. operating state controllers); and decoding block 642 (i.e. command decoder). Note: The Storage Controller 602 and I/O circuit 634 can be attached to multiple memory die 604a-n).
wherein whether the command decoder is to be disabled is selected based on whether an operating state signal is activated; (BHATI, fig 8A-8E, “[0196] The ALEx pin 816 and CEnx pin 812 generate ALE signal 865 and CLE signal 870, which are directed to the CE multiplexer 839… The CE multiplexer 839 generates a signal 880, gated by the die status signal 875, that activates or enables each of the I/O[0:n]x pins 826 and WEnx pin 821 of the memory die 804a. … Otherwise, the die stat signal 875 at logic LOW level indicates the memory die 804a is not enabled and the CE multiplexer 839 generates signal 880 at logic LOW level, which disables or deactivates the I/O[0:n]x pins 826 and WEnx pins 821. Disabling or deactivating the I/O[0:n]x pins 826 and WEnx pins 821 ensures that the memory die 804a is in a standby state and power is not consumed…. [0199] Conversely, if the modified CEN signal 894 is asserted at logic LOW level, then the decoding block 842 is disabled.”; paragraphs 0196-0204 which outline how the ALE, CE, and CLE signals are combined to activate or deactivate a die function, that when the “modified CEN signal” is LOW, then the normal decoding block 842 is disabled; conversely Bhatia teaches that decoding block 842 is turned on if the CEN signal is high).
an operating state controller configured to switch an operating state of the memory device from an activation state to a deactivation state and thereafter from the deactivation state to the activation state, in response to a set signal applied to the first pad; and (BHATI, fig 2A, 2B, 8A-8E, “[0186] Upon generating the CEn signal 805, the memory die 804a activates or otherwise enables the CLEx pin 812 and the ALEx pin 816… (In FIG. 8B)… When the storage controller 802 asserts the ALE signal 803c and the CLE signal 803b at logic HIGH level, the memory die 804a is instructed that the idle current saving mode is enabled, the die enable decoder block 846 is enabled, and that address data (e.g., an address code) is included in I/O data encoded on the DQ signals…. [0192] The CHPSA signal 850 may be an active-high signal, according to various embodiments, for enabling or disabling the pins of the memory die 804a. For example, the CHPSA signal 850 may be asserted by the die enable decoder block 846 at logic HIGH level in a case where the memory die identified by the CADD (e.g., CADD signal 845) matches a memory die identified by the address data encoded in the DQ signals (e.g., from signal 840).”; that a combination of CEn, CLEx and ALEx signals are sent to the different memory die; that the combination of these signals when at HIGH level enable a particular memory die (in this case 804a) to operate; that the CHPSA signal 850 is used to enable or disable the memory die functions; that the “Die Enable Decoder Block 846” receives ALL of the incoming signals to enable the Die “normal command decoder” to function).
an internal operation execution circuit configured to perform a set internal operation in response to the command. (BHATI, fig 8D, “[0194] Referring to FIG. 8D, after storing the CHPSA signal 850 in the status register 848, the storage controller 834 transmits control signals 855 to initiate a command/ address sequencing. … In one example, control signals 855 may correspond to command/address sequencing as part of a data operation (e.g., read, write, program, etc.) associated immediately following the die switch opcode 803.”; that normal chip operations are executed after the particular die is enabled; that this “operation” comprises transmitting control signals to initiate a command & address sequence).
Regarding claim 2, BHATI teaches The memory device of claim 1, wherein the command decoder is disabled while the operating state signal stays activated. (BHATI, fig 8A-8E, “ [0199] Conversely, if the modified CEN signal 894 is asserted at logic LOW level, then the decoding block 842 is disabled. [0193] Thus, each memory die of the memory array 801 comprises a CHPSA signal 850 latched into a respective status register 848 as a respective die status state. As noted above, a first one or more memory dies may have a die status state at logic HIGH level indicating that the first one or more memory dies are enabled for subsequent data operations, while a second one or more memory dies may have die status state at a logic LOW level indicating that the second one or more memory dies are disabled for subsequent operations.”; the command decoder 842 is disabled when the CEN signal is LOW; the die has a “Die Enable Decoder Block 846” which interprets the CEN signals to determine the memory die operation status of enabled or disabled).
Regarding claim 3, BHATI teaches (Currently Amended) The memory device of claim 2, wherein the operating state controller is configured to keep an activated operating state signal activated and keep a deactivated operating state signal deactivated in response to remaining signals except for the set signal. (BHATI, fig 8A-8E, “[0193] As noted above, a first one or more memory dies may have a die status state at logic HIGH level indicating that the first one or more memory dies are enabled for subsequent data operations, while a second one or more memory dies may have die status state at a logic LOW level indicating that the second one or more memory dies are disabled for subsequent operations. [0184] Referring to FIG. 8A, to initiate a data operation on the memory die 804a, the storage controller 802 transmits a die switch opcode 803. The die switch opcode 803 comprises a CEn signal 803a, CLE signal 803b, ALE signal 803c, and a WEn signal 803d,”; that the controller 802 transmits a signal to all respective memory die using the interface circuit 834; that each of the die receive the signal at their respective interface; that the signal is interpreted by the “Die Enable” block; that some of the memory dies can be enabled while other dies are disabled by the particular 803 signal).
Regarding claim 4, BHATI teaches:
(Currently Amended) The memory device of claim 3, further comprising: a detection circuit configured to detect a logic level of an input signal applied to a second pad at a time point when the operating state signal becomes activated; and (BHATI, fig 8A-8E, “[0186] When the storage controller 802 asserts the ALE signal 803c and the CLE signal 803b at logic HIGH level, the memory die 804a is instructed that the idle current saving mode is enabled, the die enable decoder block 846 is enabled, and that address data (e.g., an address code) is included in I/O data encoded on the DQ signals.”; that each die can receive “an input signal”. As stated above, it is indefinite as to whether this is a different or the same “input signal” that reaches the first pad).
a signal transfer circuit configured to: transfer, to the internal operation execution circuit while the deactivated operating state signal stays deactivated, the input signal applied to the second pad, and transfer, to the internal operation execution circuit while the activated operating state signal stays activated, a signal having the logic level detected by the detection circuit. (BHATI, fig 8A-8E, “[0193] The above signal flow shown in FIGS. SA-SC is performed in each memory die of the memory array 801, where memory die 804a is provide as an illustrative example. Thus, each memory die of the memory array 801 comprises a CHPSA signal 850 latched into a respective status register 848 as a respective die status state. As noted above, a first one or more memory dies may have a die status state at logic HIGH level indicating that the first one or more memory dies are enabled for subsequent data operations, while a second one or more memory dies may have die status state at a logic LOW level indicating that the second one or more memory dies are disabled for subsequent operations.”; that each die can have its own “pad” that accepts commands to drive that memory die; that after activation the second die using the second pad is either enabled or disabled).
Regarding claim 8, BHATI teaches:
(Currently Amended) A memory device comprising: a first die including a first pad connected to a first line and configured to: (BHATI, fig 2A, 2B, 8A-8E, “[0053] The memory device 200 may include a storage controller 102 and a memory array 202 comprised of a number of memory dies 104a-n, [0097] FIG. 2C is a block diagram of example memory system 200 that depicts more details of one embodiment of memory die 104a. [0181] FIGS. 8A-8E also illustrate a flow of control signals between a storage controller 802 and a memory die 804a. Control signals are transmitted from a memory interface circuit 834 to a I/O circuit 822, and may be implemented to enable or disable memory dies of the memory array 801.”; a memory device with a I/O circuit 634 (i.e. first pad), with storage controller 602 with CE multiplexor 639 (i.e. operating state controllers); and decoding block 642 (i.e. command decoder). Note: The Storage Controller 602 and I/O circuit 634 can be attached to multiple memory die 604a-n).
block, during a first set mode, signals except a first set signal for controlling the first die to exit from the first set mode, and (BHATI, fig 8A-8E, “[0196] The ALEx pin 816 and CEnx pin 812 generate ALE signal 865 and CLE signal 870, which are directed to the CE multiplexer 839… The CE multiplexer 839 generates a signal 880, gated by the die status signal 875, that activates or enables each of the I/O[0:n]x pins 826 and WEnx pin 821 of the memory die 804a. … Otherwise, the die stat signal 875 at logic LOW level indicates the memory die 804a is not enabled and the CE multiplexer 839 generates signal 880 at logic LOW level, which disables or deactivates the I/O[0:n]x pins 826 and WEnx pins 821. Disabling or deactivating the I/O[0:n]x pins 826 and WEnx pins 821 ensures that the memory die 804a is in a standby state and power is not consumed…. [0199] Conversely, if the modified CEN signal 894 is asserted at logic LOW level, then the decoding block 842 is disabled.”; paragraphs 0196-0204 which outline how the ALE, CE, and CLE signals are combined to activate or deactivate a die function, that when the “modified CEN signal” is LOW, then the normal decoding block 842 is disabled; conversely Bhatia teaches that decoding block 842 is turned on if the CEN signal is high).
perform, during a mode other than the first set mode, a first set internal operation in response to an input signal applied to the first pad; and (BHATI, fig 2A, 2B, 8A-8E, “[0186] Upon generating the CEn signal 805, the memory die 804a activates or otherwise enables the CLEx pin 812 and the ALEx pin 816… (In FIG. 8B)… When the storage controller 802 asserts the ALE signal 803c and the CLE signal 803b at logic HIGH level, the memory die 804a is instructed that the idle current saving mode is enabled, the die enable decoder block 846 is enabled, and that address data (e.g., an address code) is included in I/O data encoded on the DQ signals…. [0192] The CHPSA signal 850 may be an active-high signal, according to various embodiments, for enabling or disabling the pins of the memory die 804a. For example, the CHPSA signal 850 may be asserted by the die enable decoder block 846 at logic HIGH level in a case where the memory die identified by the CADD (e.g., CADD signal 845) matches a memory die identified by the address data encoded in the DQ signals (e.g., from signal 840).”; that a combination of CEn, CLEx and ALEx signals are sent to the different memory die; that the combination of these signals when at HIGH level enable a particular memory die (in this case 804a) to operate; that the CHPSA signal 850 is used to enable or disable the memory die functions; that the “Die Enable Decoder Block 846” receives ALL of the incoming signals to enable the Die “normal command decoder” to function).
a second die including a second pad connected to the first line and configured to: block, during the second set mode, signals except a second set signal for controlling the second die to exit from the second set mode, and perform, during a mode other than the second set mode, a second set internal operation in response to an input signal applied to the second pad, wherein the memory device is configured to switch the first die and the second die from a perform state to a block state and thereafter from the block state to the perform state, in response respectively to the input signal applied to the first pad and the input signal applied to the second pad. (BHATI, fig 8A-8E, “[0193] The above signal flow shown in FIGS. SA-SC is performed in each memory die of the memory array 801, where memory die 804a is provide as an illustrative example. Thus, each memory die of the memory array 801 comprises a CHPSA signal 850 latched into a respective status register 848 as a respective die status state. As noted above, a first one or more memory dies may have a die status state at logic HIGH level indicating that the first one or more memory dies are enabled for subsequent data operations, while a second one or more memory dies may have die status state at a logic LOW level indicating that the second one or more memory dies are disabled for subsequent operations.”; that each die can have its own “pad” that accepts commands to drive that memory die; that after activation the second die using the second pad is either enabled or disabled).
Regarding claim 9, BHATI teaches The memory device of claim 8, wherein: the first die is further configured to enter or exit from the first set mode in response to the first set signal applied to the first pad, and the second die is further configured to enter or exit from the second set mode in response to the second set signal applied to the second pad. (BHATI, fig 8A-8E, 12A-B, “[0221] Figs 12A and 12B … Diagrams 1210 and 1220 provide illustrative visualizations of switching enabling/disabling of memory dies l204a-n (e.g., where memory die 804a is an example implementation) in a memory array 1202 (e.g., memory array 801), for example, based on a die switch opcodes 1212 and 1222, respectively, from a storage controller ( e.g., storage controller 802).”; that each die can have its own “pad” that accepts commands to drive that memory die; that after activation the second die using the second pad is either enabled or disabled; that the storage controller 802 can send a set of signals which enable particular dies while disabling other memory dies).
Regarding claim 10, BHATI teaches:
(Currently Amended) The memory device of claim 9,wherein the first die comprises: a first command decoder enabled during the mode other than the first set mode and disabled during the first set mode and configured to generate a first command by decoding an input signal applied to the first pad; (BHATI, fig 12A-B, “[0221] As illustrated in FIGS. 12A and 12B, 1202 comprises eight memory dies l204a-n labeled as Die0 through Die7. However, any number of memory dies 1204a-n may be used, and eight dies are shown in FIGS. 12A and 12B as an illustrative example. [0222] Referring to FIG. 12A, the die switch opcode 1212 may include at least an ALE signal and CLE signal asserted at logic HIGH level (or, in another example, a DSO signal asserted at logic HIGH level) and accompanied by an address code 1214. The address code 1214 may be encoded in a DQ signal as a bit pattern indicative of one or more memory dies to be selected. Table 2 above illustrates example bit patterns.”; that the various memory dies are individually selectable using controller 802).
a first operating state controller configured to activate or deactivate a first operating state signal in response to the first set signal applied to the first pad; and a first internal operation execution circuit configured to perform the first internal operation in response to the first command, and wherein the first operating state signal stays activated during the first set mode and stays deactivated during the mode other than the first set mode. (BHATI, fig 12A-B, “In the example of Fig 12A, the address code 1214 may indicate Die0 is selected. Responsive to the address code 1214 and the die switch opcode 1212, Die0 is enabled and Diel through Die7 are disabled.”; that different “opcodes” are used to enable or disable operations at different dies, as shown above, the signals sent to the Block 846 interpret the incoming codes).
Regarding claim 11, BHATI teaches:
(Currently Amended) The memory device of claim 10,wherein the second die comprises: a second command decoder enabled during the mode other than the second set mode and disabled during the second set mode and configured to generate a second command by decoding an input signal applied to the second pad; (BHATI, fig 8A-8E, 12A-B, “[0221] Figs 12A and 12B … Diagrams 1210 and 1220 provide illustrative visualizations of switching enabling/disabling of memory dies l204a-n (e.g., where memory die 804a is an example implementation) in a memory array 1202 (e.g., memory array 801), for example, based on a die switch opcodes 1212 and 1222, respectively, from a storage controller ( e.g., storage controller 802).”; that each die can have its own “pad” that accepts commands to drive that memory die; that after activation the second die using the second pad is either enabled or disabled; that the storage controller 802 can send a set of signals which enable particular dies while disabling other memory dies).
a second operating state controller configured to activate or deactivate a second operating state signal in response to the second set signal applied to the second pad; and (BHATI, fig 12A-B, “[0221] As illustrated in FIGS. 12A and 12B, 1202 comprises eight memory dies l204a-n labeled as Die0 through Die7. However, any number of memory dies 1204a-n may be used, and eight dies are shown in FIGS. 12A and 12B as an illustrative example. [0222] Referring to FIG. 12A, the die switch opcode 1212 may include at least an ALE signal and CLE signal asserted at logic HIGH level (or, in another example, a DSO signal asserted at logic HIGH level) and accompanied by an address code 1214. The address code 1214 may be encoded in a DQ signal as a bit pattern indicative of one or more memory dies to be selected. Table 2 above illustrates example bit patterns.”; that the various memory dies are individually selectable using controller 802).
a second internal operation execution circuit configured to perform the second internal operation in response to the second command, and wherein the second operating state signal stays activated during the second set mode and stays deactivated during the mode other than the second set mode. (BHATI, fig 12A-B, “In the example of Fig 12A, the address code 1214 may indicate Die0 is selected. Responsive to the address code 1214 and the die switch opcode 1212, Die0 is enabled and Diel through Die7 are disabled.”; that different “opcodes” are used to enable or disable operations at different dies, as shown above, the signals sent to the Block 846 interpret the incoming codes; that when activated, any of the dies can then execute the associated command to read, write, etc).
Regarding claim 12, BHATI teaches:
(Currently Amended) The memory device of claim 11, wherein: the first operating state controller is configured to keep an activated first operating state signal activated and keep a deactivated first operating state signal deactivated in response to the first set signal among input signals applied to the first pad, and (BHATI, fig 8A-8E, “[0186] When the storage controller 802 asserts the ALE signal 803c and the CLE signal 803b at logic HIGH level, the memory die 804a is instructed that the idle current saving mode is enabled, the die enable decoder block 846 is enabled, and that address data (e.g., an address code) is included in I/O data encoded on the DQ signals.”; that each die can receive “an input signal”. As stated above, it is indefinite as to whether this is a different or the same “input signal” that reaches the first pad).
the second operating state controller is configured to keep an activated second operating state signal activated and keep a deactivated second operating state signal deactivated in response to the second set signal among input signals applied to the second pad. (BHATI, fig 8A-8E, “[0193] The above signal flow shown in FIGS. SA-SC is performed in each memory die of the memory array 801, where memory die 804a is provide as an illustrative example. Thus, each memory die of the memory array 801 comprises a CHPSA signal 850 latched into a respective status register 848 as a respective die status state. As noted above, a first one or more memory dies may have a die status state at logic HIGH level indicating that the first one or more memory dies are enabled for subsequent data operations, while a second one or more memory dies may have die status state at a logic LOW level indicating that the second one or more memory dies are disabled for subsequent operations. [0178] Table 2 below provides example bit patterns for addresses of memory dies in an 8 die array (or stack). Table 2 also illustrates example, chip address (CADD) used for die mapping.”; that each die can have its own “pad” that accepts commands to drive that memory die; that after activation the second die using the second pad is either enabled or disabled, that the different dies have different mapping to receive the “HIGH” or LOW signals for enabling or disabling the individual memory die and associated decoders).
Regarding claim 21, BHATI teaches:
(Currently Amended) The memory device of claim 1, wherein the set signal is a freeze signal of entering a freeze mode that blocks the input signal applied to the first pad in an entry interval of the freeze mode, and (BHATI, fig 8, “[0178] Table 2 below provides example bit patterns for addresses of memory dies in an 8 die array (or stack). Table 2 also illustrates example, chip address (CADD) used for die mapping, which are unchanged as shown below. In various embodiments, the CADD may be hard coded into each memory die, for example, as 3-bit wide bit pattern that identifies memory die within the memory array.”; that each memory die has it’s own chip address).
the memory device, in response to the freeze signal, enters the deactivation state. (BHATI, fig 8A-8E, “[0196] The ALEx pin 816 and CEnx pin 812 generate ALE signal 865 and CLE signal 870, which are directed to the CE multiplexer 839… The CE multiplexer 839 generates a signal 880, gated by the die status signal 875, that activates or enables each of the I/O[0:n]x pins 826 and WEnx pin 821 of the memory die 804a. … Otherwise, the die stat signal 875 at logic LOW level indicates the memory die 804a is not enabled and the CE multiplexer 839 generates signal 880 at logic LOW level, which disables or deactivates the I/O[0:n]x pins 826 and WEnx pins 821. Disabling or deactivating the I/O[0:n]x pins 826 and WEnx pins 821 ensures that the memory die 804a is in a standby state and power is not consumed…. [0199] Conversely, if the modified CEN signal 894 is asserted at logic LOW level, then the decoding block 842 is disabled.”; paragraphs 0196-0204 which outline how the ALE, CE, and CLE signals are combined to activate or deactivate any of the die functions, that when the “modified CEN signal” is LOW on a die (as perhaps shown in table 2), then the normal decoding block 842 is disabled; conversely Bhatia teaches that decoding block 842 is turned on if the CEN signal is high (again as shown in table 2)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONALD H.B. BRASWELL whose telephone number is (469)295-9119. The examiner can normally be reached on 7-5 Central Time (Dallas).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Donald HB Braswell/ Primary Examiner, Art Unit 2825