DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/10/2026 is in compliance with the provisions on 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Amendments
Acknowledgment of receiving amendments to the claims, which were received by the Office on 06/15/2026.
Response to Arguments
Applicant's arguments filed 06/15/2026 have been fully considered but they are not persuasive.
In that remarks, applicant argues in substance:
Applicant argues: “In Takado, the pattern of VO/V1 connections does differ per row. Takado teaches that "the pixels 110 to which the fixed voltage VO is supplied and the pixels 111 to which the fixed voltage V1, which is different from the fixed voltage VO, is supplied are arranged in a matrix according to a particular pattern" where "the pattern of the fixed voltages applied to the pixels 110 and 111 is different in accordance with the row for the vertical scanning."2 However, Takado never teaches that this pattern corresponds to an address signal. Instead, Takado compares actual output values to "expected values" based on the connection settings of the fixed voltages.3 The "expected values" in Takado are not address signals, the expected values are predetermined output values based on the voltage pattern.
In Engelbrecht, the row address ROM stores unique values corresponding to row addresses, where "each row of row address ROM may correspond to a row of pixel array 101 and may store a unique value that identifies the corresponding row" using "transistors 206 may be placed to determine which bits of a unique value are logic one."4 However, Engelbrecht uses static transistor placements in a separate ROM structure, not dummy circuits with different voltage supply line connections.5 The combination proposed by the Office grafts Engelbrecht's "compare to address signal" concept onto Takado's existing dummy pixel structure, but does not teach or suggest that the arrangement of dummy circuits coupled to different voltage supply lines should be configured to differ between pixel lines such that the resulting line identification information corresponds to the address signal. There is no teaching or suggestion in either reference to configure the voltage supply line connections of the dummy circuits to encode address information.”
Examiner’s Response: Examiner respectfully disagrees. The combination of Takado and Engelbrecht uses the row address as a voltage pattern as seen in Engel as the voltage pattern (connections of the first and second voltage supply lines) of Takado. As seen in Engelbrecht, Figure 6, and paragraph 0039, the row address and unique value that identifies the corresponding row are the same and increase sequentially.
By using the row address pattern as the voltage pattern of Takado, the expected values would similarly correspond to the respective address signals.
Therefore, the combination of Takado and Engelbrecht is seen to disclose “wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals”.
Applicant argues: “Regarding the alternative rejection of claim 1 as allegedly obvious over Wada in view of Engelbrecht, Applicant respectfully traverses this rejection as well. Similar to Takado, Wada teaches that "the pixels 20B supplied with a constant voltage VO (denoted as 'VO' in FIG. 7) and the pixels 20B supplied with a constant voltage V1 (denoted as 'V1' in FIG. 7) that is different from the constant voltage VO are arranged in a matrix according to a particular pattern" where "the constant voltage pattern applied to the pixels 20B is different depending on the row of the pixel array unit 10."7 However, like Takado, Wada never teaches that this pattern corresponds to an address signal. Engelbrecht does not cure this deficiency for the same reasons discussed above. Thus, the combination of Wada and Engelbrecht fails to establish a prima facie case of obviousness with respect to amended claim 1 because Wada and Engelbrecht, alone or in any combination, fail to disclose or suggest all of the features of amended claim 1, and provide no apparent reason for modification to include such features.”
Examiner’s Response: Examiner respectfully disagrees. The combination of Wada and Engelbrecht uses the row address as a voltage pattern as seen in Engel as the voltage pattern (connections of the first and second voltage supply lines) of Wada. As seen in Engelbrecht, Figure 6, and paragraph 0039, the row address and unique value that identifies the corresponding row are the same and increase sequentially.
By using the row address pattern as the voltage pattern of Wada, the expected values would similarly correspond to the respective address signals.
Therefore, the combination of Wada and Engelbrecht is seen to disclose “wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 7, 9-10 and 24-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/0098012 A1) in view of Engelbrecht et al. (US 2015/0245019 A1).
Regarding claim 1, Takado et al. (hereafter referred as Takado), teaches an imaging device (Takado, Fig. 1) comprising:
a scanning circuit (Takada, Fig. 1, vertical scanning circuit 102);
a readout circuit (Takada, Fig. 1, column circuit 103);
a plurality of circuits including a plurality of pixel lines, each pixel line (Takado, Fig. 1) including
a first plurality of dummy circuits (Takado, Fig. 1-2, pixel 110), each of the first plurality of dummy circuits has a first amplifier transistor with a first gate (Takado, Fig. 2, amplifier transistor M3 of pixel 110, Paragraph 0040) coupled to a first voltage supply line that supplies a first voltage (Takado, Figs. 1-2, voltage supply line 112, Voltage V0, Paragraph 0024), each dummy circuit of the first plurality of dummy circuits is configured to output a first signal (Takado, Paragraph 0040),
a second plurality of dummy circuits (Takado, Fig. 1-2, pixel 111), each of the second plurality of dummy circuits has a second amplifier transistor with a second gate (Takado, Fig. 2, amplifier transistor M3 of pixel 111, Paragraph 0040) coupled to a second voltage supply line (Takado, Figs. 1-2, voltage supply line 113, Voltage V1, Paragraph 0024) different from the first voltage supply line, each dummy circuit of the second plurality of dummy circuits is configured to output a second signal (Takado, Paragraph 0041), and
a first plurality of pixel circuits (Takado, Fig. 1-2, pixel 105, Paragraph 0023), each of the first plurality of pixel circuits has a third amplifier transistor with a third gate coupled to a first light-receiving element (Takado, Fig. 2, amplifier transistor M3 of pixel 105, Paragraph 0039); and
a controller configured to control the each pixel line of the plurality of pixel lines to output first signals including the first signal and second signals including the second signal (Takado, Fig. 1, Control Unit 107, Paragraphs 0028 and 0103),
receive the first signals and the second signals for the each pixel line, determine, from the first signals and the second signals for the each pixel line, line identification information for the each pixel line (Takado, Fig. 8, Paragraph 0105, actual output values are the line identification information.),
wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines (Takado, Fig. 1), and
perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to expected values (Takado, Fig. 8, Paragraphs 0104-0107, Performing the failure detection operation on an entire frame is seen to teach detecting an operational malfunction on the each pixel line of the plurality of pixel lines.),
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the expected values (Takado, Fig. 8, Paragraphs 0104-0107).
However, Takado does not teach the controller configured to generate respective address signals regarding the plurality of pixel lines, output the respective address signals to control the each pixel line of the plurality of pixel lines to output first signals, the difference between the plurality of pixel lines differs such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals, and perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to a corresponding portion of the respective address signals, detects an operational malfunction indicated by a failure of correspondence between the line identification information and the corresponding portion of the respective address signals.
In reference to Engelbrecht et al. (here after referred as Engel), Engel teaches a controller (Engel, Fig. 2, control circuit 106, Fig. 4, “row address”, Paragraph 0029 and 0033) configured to
generate respective address signals regarding the plurality of pixel lines, output the respective address signals to control the each pixel line of the plurality of pixel lines to output signals (Engel, Fig. 2, control circuit 106, Paragraph 0029 and 0033),
receive the signals for the each pixel line, determine, from the signals for the each pixel line, line identification information for the each pixel line (Engel, Fig. 6A, Paragraphs 0039 and 0042),
wherein an arrangement of values differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals (Engel, Fig. 6, Paragraph 0039), and
perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to a corresponding portion of the respective address signals (Engel, Paragraphs 0038-0040 and 0042).
detects an operational malfunction indicated by a failure of correspondence between the line identification information and the corresponding portion of the respective address signals (Engel, Paragraphs 0038-0040 and 0042).
These arts are analogous since they are both related to error detection of image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado with the teaching of using the row address as a voltage pattern as seen in Engel since it is a known pattern for use in determining image sensor errors and would provide similar and expected results for providing unique patterns for performing the diagnosis process. Further, by using the row address pattern as the voltage pattern of Takado, the limitation “wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals” is met.
Regarding claim 3, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising:
a conversion circuit (Takado, Fig. 1, column circuit 103 and output circuit 115, Paragraph 0031) configured to generate first digital codes by performing analog-to-digital (AD) conversion based on the first signals (Takado, Paragraph 0031, AD conversion of the first signal produces a first digital signal which is a first digital code.), and generate second digital codes by performing AD conversion based on the second signals (Takado, Paragraph 0031, AD conversion of the second signal produces a second digital signal which is a second digital code.), and
the controller configured to determine the line identification information based on the first digital codes and the second digital codes (Takado, Fig. 8, Step S840, Paragraphs 0104-0106),
wherein the line identification information is derived from a combination of the first signals and the second signals output by the first plurality of dummy circuits and the second plurality of dummy circuits based on their respective connections to the first voltage supply line and the second voltage supply line (Takado, Fig. 8, Step S840, Paragraphs 0104-0106).
Regarding claim 5, the combination of Takado and Engel teaches the imaging device according to claim 3 (see claim 3 analysis), wherein
the controller is further configured to
determine line identification information of the each pixel line of the plurality of pixel lines based on a corresponding one of the first digital codes and a corresponding one of the second digital codes (Takado, Fig. 8, Step S840, Paragraph 0104-0106, The actual output values are considered to be line identification information.).
Regarding claim 7, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the first voltage supply line and the second voltage supply line extend in a first direction (Takado, Fig. 1, voltage supply lines 112 and 113 extend in the vertical direction. The first direction may be the vertical direction. Alternately, a section of the voltage supply lines 112 and 113 extend in the horizontal direction. The first direction may be the horizontal direction.),
wherein the plurality of circuits includes a second plurality of pixel circuits (Takado, Fig. 1, pixel 106) that has a fourth amplifier transistor with a fourth gate (Takado, Fig. 2, amplifier transistor M3 of pixel 106, Paragraph 0039) coupled to a second light-receiving element (Takado, Fig. 2, photoelectric converter PD) shielded from light (Takado, Fig. 2, photoelectric converter PD, Paragraph 0023), and
the first plurality of dummy circuits, the second plurality of dummy circuits, the first plurality of pixel circuits and the second plurality of pixel circuits are disposed in the first direction (Takado, Fig. 1).
Regarding claim 9, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising: a driving unit (Takado, Fig. 1, Vertical scanning circuit 102, Paragraph 0026 and 0028) coupled to the first plurality of dummy circuits, the second plurality of dummy circuits, and the first plurality of pixel circuits via a control signal line (Takado, Fig. 1, control line 109, Paragraph 0026),
wherein the first plurality of pixel circuits is disposed between the driving unit and the first plurality of dummy circuits along the control signal line (Takado, Fig. 11, Pixels 105 are between dummy pixels 110 and the Vertical scanning circuit 102.).
Regarding claim 10, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), further comprising: a communication interface configured to communicate with a vehicular electronic control unit (ECU) (Takado, Fig. 7A, main control unit 713, Paragraph 0093-0096).
Regarding claim 24, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), wherein
the controller is further configured to fix and set information regarding the each pixel line by using the first plurality of dummy circuits and the second plurality of dummy circuits as mask read only memory (ROM) (Takado, Fig. 1, Dummy pixels V0 and V1 are fixed and set to respective voltage lines. A row address input to corresponds to a respective pixel row with expected dummy circuit outputs. Therefore, the first plurality of dummy circuits and the second plurality of dummy circuits are seen to act as mask read only memory (see conclusion for details of a mask read only memory).).
Regarding claim 25, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the operational malfunction is one malfunction selected from a group consisting of:
a connection malfunction between the controller (Takada, Fig. 1, Control Unit 107) and the scanning circuit (Takada, Fig. 1, vertical scanning circuit 102),
a malfunction of the scanning circuit,
a connection malfunction between the scanning circuit and one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a malfunction of the one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a connection malfunction between the readout circuit (Takada, Fig. 1, column circuit 103) and the one of the first plurality of dummy circuits or the second plurality of dummy circuits,
a connection malfunction between the readout circuit and the controller, and
a malfunction of the readout circuit (Takada, Fig. 8, Steps S820-S870, Paragraphs 0104-0106, Any malfunction that causes the output expected values and the actual output values of the pixels 110 and 111 to not match would be detected. Therefore, a malfunction in any of the listed group causing the output expected values and the actual output values to not match would be detected as an operation malfunction.).
Regarding claim 26, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line corresponds to an ordinal number of the each pixel line expressed as a binary number (Engel, Fig. 6, Paragraph 0039, The row addresses are sequential and represented in binary.), and wherein the controller is configured to perform the diagnosis process in parallel with a normal imaging operation using the first plurality of pixel circuits (Takado, Fig. 8, Paragraphs 0104-0106, Step S860 is seen to be a normal imaging operation and occurs during the diagnosis process which is considered to be all steps of Figure 8. Therefore, the normal imaging operation is considered to be parallel with the diagnosis process.) .
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/009012 A1) in view of Engelbrecht et al. (US 2015/0245019 A1) in view of Shimizu et al. (US 2020/0059620 A1).
Regarding claim 4, the combination of Takado and Engel teaches the imaging device according to claim 1 (see claim 1 analysis). However, the combination of Takado and Engel does not teach wherein the first voltage supply line, the second voltage supply line, the plurality of pixel circuits, and the first light-receiving element are formed on a first semiconductor substrate, and a portion of the controller is formed on a second semiconductor substrate, the second semiconductor substrate bonded to the first semiconductor substrate.
In reference to Shimizu et al. (hereafter referred as Shimizu) Shimizu teaches wherein the plurality of pixel circuits (Shimizu, Fig. 1, Pixel Array 12), and the first light-receiving element (Shimizu, Figs. 1 and 5, photodiodes 300, Paragraph 0096) are formed on a first semiconductor substrate (Shimizu, Figs. 1 and 5, first semiconductor substrate 10), and
a portion of the controller (Shimizu, Fig. 1, Control circuit 27 and vertical scanner 21, Paragraph 0053 and 0060) is formed on a second semiconductor substrate, the second semiconductor substrate bonded to the first semiconductor substrate (Shimizu, Fig. 1 and 5, second semiconductor substrate 20, Paragraphs 0051 and 0103).
These arts are analogous since they are all related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Takado and Engel with the teaching of using separate substrates for the pixel array and the peripheral circuitry as seen in Shimizu to increase the proportion of the imaging area to the chip size, and a downsizing of the chip (Shimizu, Paragraph 0015). Further, since the first voltage supply line and the second voltage supply line are part of the pixel array, it would have been obvious to one of ordinary skill in the art to form the first voltage supply line and the second voltage supply line in the first semiconductor substrate since the semiconductor substrate contains the pixel array. Alternatively,
"A person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense" KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007).
It would have been obvious to a person of ordinary skill, when pursuing the known options within his or her technical grasp (See KSR International Co. v. Teleflex Inc., 550 U.S. _, 82 USPQ2d 1385 (2007)), modify the combination of Takado and Engel to form the first voltage supply line and the second voltage supply line in the first semiconductor substrate since there is a finite number of identified, predictable potential solutions to the placement of the first voltage supply line and the second voltage supply line (either placed on the first substrate or placed on the second substrate). Therefore, it would have been obvious to try placing the first voltage supply line and the second voltage supply line in the first semiconductor substrate since it would provide the predicted results of supplying the voltages to the pixel array.
Claim(s) 1 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2018/0197907 A1) in view of Engelbrecht et al. (US 2015/0245019 A1).
Regarding claim 1, Wada et al. (hereafter referred as Wada), teaches an imaging device (Wada, Fig. 7) comprising:
a scanning circuit (Wada, Fig. 7, vertical scanning circuit 30);
a readout circuit (Wada, Fig. 7, column circuit 40);
a plurality of circuits (Wada, Fig. 7) including
a first plurality of dummy circuits (Wada, Fig. 7, pixel 20B (V1), Paragraph 0067), each of the first plurality of dummy circuits has a first amplifier transistor with a first gate (Wada, Fig. 2, amplifier transistor M3B, Paragraph 0037) coupled to a first voltage supply line that supplies a first voltage (Wada, Figs. 7, voltage supply line 19, Voltage V1, Paragraph 0067-0068), each dummy circuit of the first plurality of dummy circuits is configured to output a first signal (Wada, Paragraph 0040),
a second plurality of dummy circuits (Wada, Fig. 7, pixel 20B (V0), Paragraph 0067) each of the second plurality of dummy circuits has a second amplifier transistor with a second gate (Wada, Fig. 2, amplifier transistor M3B, Paragraph 0037) coupled to a second voltage supply line (Wada, Figs. 7, voltage supply line 19, Voltage V0, Paragraph 0067-0068) different from the first voltage supply line (Wada, Paragraph 0028, “Note that the voltage supply line 19 on each column may include a plurality of voltage supply lines connected to the pixels 20B that are different from each other”), each dummy circuit of the second plurality of dummy circuits is configured to output a second signal (Wada, Paragraph 0040), and
a first plurality of pixel circuits (Wada, Figs. 7, Pixel 20A) each of the first plurality of pixel circuits has a third amplifier transistor with a third gate coupled to a first light-receiving element (Wada, Fig. 2, amplifier transistor M3A, Paragraph 0036); and
a controller configured to control the each pixel line of the plurality of pixel lines to output first signals including the first signal and second signals including the second signal (Wada, Fig. 7, Control Unit 80, Paragraphs 0029 and 0034),
receive the first signals and the second signals for the each pixel line, determine, from the first signals and the second signals for the each pixel line, line identification information for the each pixel line (Wada, Fig. 14, Paragraph 0118, The line identification information is the output value of pixels 20B.)
wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines (Wada, Fig. 7), and
perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to expected values (Wada, Paragraphs 0029-0030 and 0073-0074, Fig. 14, Paragraphs 0119-0122, Performing the failure detection operation on an entire frame is seen to teach detecting an operational malfunction on the each pixel line of the plurality of pixel lines.),
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the expected values (Wada, Fig. 14, Paragraphs 0119-0122).
However, Wada does not teach the controller configured to generate respective address signals regarding the plurality of pixel lines, output the respective address signals to control the each pixel line of the plurality of pixel lines to output first signals, and perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to a corresponding portion of the respective address signals, detects an operational malfunction indicated by a failure of correspondence between the line identification information and the corresponding portion of the respective address signals.
In reference to Engelbrecht et al. (here after referred as Engel), Engel teaches a controller (Engel, Fig. 2, control circuit 106, Fig. 4, “row address”, Paragraph 0029 and 0033) configured to
generate respective address signals regarding the plurality of pixel lines, output the respective address signals to control the each pixel line of the plurality of pixel lines to output signals (Engel, Fig. 2, control circuit 106, Paragraph 0029 and 0033),
receive the signals for the each pixel line, determine, from the signals for the each pixel line, line identification information for the each pixel line (Engel, Fig. 6A, Paragraphs 0039 and 0042),
wherein an arrangement of values differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals (Engel, Fig. 6, Paragraph 0039), and
perform a diagnosis process on the each pixel line of the plurality of pixel lines by comparing the line identification information that is determined for the each pixel line to a corresponding portion of the respective address signals (Engel, Paragraphs 0038-0040 and 0042).
detects an operational malfunction indicated by a failure of correspondence between the line identification information and the corresponding portion of the respective address signals (Engel, Paragraphs 0038-0040 and 0042).
These arts are analogous since they are both related to error detection of image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Wada with the teaching of using the row address as a voltage pattern as seen in Engel since it is a known pattern for use in determining image sensor errors and would provide similar and expected results for providing unique patterns for performing the diagnosis process. Further, by using the row address pattern as the voltage pattern of Wada, the limitation “wherein an arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line differs between the plurality of pixel lines such that the line identification information for the each pixel line corresponds to the corresponding portion of the respective address signals” is met.
Regarding claim 26, the combination of Wada and Engel teaches the imaging device according to claim 1 (see claim 1 analysis), wherein the arrangement of the first plurality of dummy circuits coupled to the first voltage supply line and the second plurality of dummy circuits coupled to the second voltage supply line corresponds to an ordinal number of the each pixel line expressed as a binary number (Engel, Fig. 6, Paragraph 0039, The row addresses are sequential and represented in binary.), and wherein the controller is configured to perform the diagnosis process in parallel with a normal imaging operation using the first plurality of pixel circuits (Wada, Fig. 14, Paragraphs 0119-0122, Step S860 is seen to be a normal imaging operation and occurs during the diagnosis process which is considered to be all steps of Figure 14. Therefore, the normal imaging operation is considered to be parallel with the diagnosis process.) .
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2018/0197907 A1) ) in view of Engelbrecht et al. (US 2015/0245019 A1) in view of Sohn (US 2014/0368710 A1).
Regarding claim 6, the combination of Wada and Engel teaches the imaging device according to claim 1 (see claim 1 analysis). However, the combination of Wada and Engel does not teach wherein a first terminal of the third amplifier transistor is coupled to the second voltage supply line.
In reference to Sohn, Sohn teaches wherein a fixed voltage supply line is connected to the amplifier transistor (Sohn, Fig. 3C, Paragraph 0048).
These arts are analogous since they are both related to imaging devices with reference pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Wada and Engel with the teaching of using the pixel power line as a fixed reference voltage as seen in Sohn since it is a known power supply line for providing a fixed voltage and would provide similar and expected results for providing a fixed reference voltage and reduce the number of power supply lines to the pixel array. Therefore, the limitation “wherein a first terminal of the third amplifier transistor is coupled to the second voltage supply line” is met since the second voltage supply line is the pixel power line (VDD).
Claim(s) 11, 13-15, 19-21 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/009012 A1) in view of Engelbrecht et al. (US 2015/0245019 A1) in view of Sohn (US 2014/0368710 A1).
Regarding claim 11, Takado teaches an imaging device (Takado, Fig. 1) comprising:
a scanning circuit (Takada, Fig. 1, vertical scanning circuit 102);
a readout circuit (Takada, Fig. 1, column circuit 103);
a pixel array comprising a plurality of pixel circuits (Takado, Fig. 1), the pixel array comprising:
a dummy circuit region (Takado, Fig. 1, second region 11, Paragraph 0022) including a first dummy circuit configured to output a first signal (Takado, Fig. 1-2, pixel 110) and a second dummy circuit configured to output a second signal (Takado, Fig. 1-2, pixel 111, Paragraph 0024 and 0040), wherein the first dummy circuit and the second dummy circuit do not include any light-receiving element;
a normal pixel region including a first pixel circuit that includes a first light-receiving element (Takado, Fig. 1, region of pixels 105, Paragraph 0023, Fig. 2, PD of pixel 105, Paragraph 0039);
a light-shielded pixel region including a second pixel circuit that includes a second light-receiving element different from the first light-receiving element, the second light-receiving element being shielded from light (Takado, Fig. 1, pixels 106, Paragraph 0023, Fig. 2, PD of pixel 106, Paragraph 0039);
a first voltage supply line coupled to the first dummy circuit, the first voltage supply line extending in a first direction and supplying a first voltage (Takado, Figs. 1-2, voltage supply line 112, Voltage V0, Paragraph 0024, A section of the voltage supply lines 112 and 113 extend in the horizontal direction. The first direction may be the horizontal direction.);
a second voltage supply line coupled to the second dummy circuit, the second voltage supply line different from the first voltage supply line, the second voltage supply line extending in the first direction and supplying a second voltage (Takado, Figs. 1-2, voltage supply line 113, Voltage V1, Paragraph 0024); and
a controller (Takado, Fig. 1, Control Unit 107, Paragraphs 0028) configured to
output a signal to control the first dummy circuit to output the first signal and control the second dummy circuit to output the second signal (Takado, Paragraphs 0103),
receive the first signal and the second signal (Takado, Fig. 8, Paragraph 0105)
determine, from the first signal and the second signal, line identification information (Takado, Fig. 8, Paragraph 0105, actual output values are the line identification information.),
wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information (Takado, Fig. 1, Paragraphs 0104), and
perform a diagnosis process by comparing the line identification information to expected values (Takado, Fig. 8, Step S840, Paragraphs 0104-0107),
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the expected values (Takado, Fig. 8, Paragraphs 0104-0107).
However, Takado does not teach wherein, in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order; the controller configured to generate an address signal with respect to the first dummy circuit and the second dummy circuit, output the address signal to control the first dummy circuit to output the first signal and control the second dummy circuit to output the second signal, wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information corresponds to the address signal, perform a diagnosis process by comparing the line identification information to the address signal, wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the address signal.
In reference to Engelbrecht et al. (here after referred as Engel), Engel teaches a controller (Engel, Fig. 2, control circuit 106, Fig. 4, “row address”, Paragraph 0029 and 0033) configured to
generate an address signals to control the plurality of pixel lines, output the address signals to control the each pixel line of the plurality of pixel lines to output signals (Engel, Fig. 2, control circuit 106, Paragraph 0029 and 0033),
receive the signals for the each pixel line, determine, from the signals for the each pixel line, line identification information for the each pixel line (Engel, Fig. 6A, Paragraphs 0039 and 0042),
wherein an arrangement of values corresponds to the address signal such that the line identification information corresponds to the address signal (Engel, Fig. 6, Paragraph 0039), and
perform a diagnosis process by comparing the line identification information to the address signal (Engel, Paragraphs 0038-0040 and 0042).
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the address signal (Engel, Paragraphs 0038-0040 and 0042).
These arts are analogous since they are both related to error detection of image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Takado with the teaching of using the row address as a voltage pattern as seen in Engel since it is a known pattern for use in determining image sensor errors and would provide similar and expected results for providing unique patterns for performing the diagnosis process. Further, by using the row address pattern as the voltage pattern of Takado, the limitation “wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information corresponds to the address signal” is met.
However, the combination of Takado and Engel does not teach wherein, in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order.
In reference to Sohn, Sohn teaches wherein in the first direction (Sohn, Fig. 2, the first direction is the horizontal direction.), a first light-shielded pixel region (Sohn, Fig. 2, Second RPA 230), a normal pixel region, and a second light shielded pixel region (Sohn, Fig. 2, First RPA 220) are disposed in this order (Sohn, Fig. 2, Paragraph 0037-0038).
These arts are analogous since they are both related to imaging devices with shielded pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Takado and Engel with the teaching of placing shielded pixel areas on both sides of the normal pixel region as seen in Sohn to compensating for shading which occurs at the left side and the right side of the array (Sohn, Paragraphs 0065-0068). That is, to place a light shielded pixel region on right side of the normal pixel region of Figure 1 of Takado. Further, by placing light-shielded pixel region on both sides of the normal pixel region, the limitation “wherein in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order” is met when the first light-shielded pixel region is considered to be the right side light-shielded pixel region.
Regarding claim 13, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis), wherein
the pixel array further includes a second light-shielded pixel region (Takado, Fig. 1, The second light-shielded pixel region is the light shielded pixels on the left side. The first light-shielded pixel region is the light shielded pixels on the right side introduced by the combination with Sohn.) including a third pixel circuit that includes a third light-receiving element different from the first light-receiving element and the second light-receiving element, the third light-receiving element being shielded from light (Takado, Fig. 1, Paragraph 0023, Fig. 2, PD of pixel 106 in the left area of the array, Paragraph 0039).
Regarding claim 14, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 13 (see claim 13 analysis), wherein
in the first direction (Takado, Fig. 1, The first direction is the horizontal direction.), the normal pixel region (Takado, Fig. 1, Region of pixels 105), the second light-shielded pixel region (Takado, Fig. 1, The second light-shielded pixel region is the light shielded pixels on the left side.), and the dummy circuit region are disposed in this order (Takado, Fig. 1, second region 11).
Regarding claim 15, the combination of Takado, Engel and Sohn teaches imaging device according to claim 13 (see claim 13 analysis), wherein in the first direction (Takado, Fig. 1, the first direction is the horizontal direction.), the first light-shielded pixel region (Sohn, Fig. 2, Second RPA 230, Takado, Fig. 1, The first light shield region is the light shield region on the right side of the pixel array in the combination.), the normal pixel region (Takado, Fig. 1, Region of pixels 105), the second light-shielded pixel region (Takado, Fig. 1, Left side pixel region of pixels 106), and the dummy circuit region are disposed in this order (Takado, Fig. 1, second region 11).
Regarding claim 19, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis), further comprising:
a conversion circuit (Takado, Fig. 1, column circuit 103 and output circuit 115, Paragraph 0031) configured to generate a first digital code by performing a first analog-to-digital (AD) conversion based on the first signal (Takado, Paragraph 0031, AD conversion of the first signal produces a first digital signal which is a first digital code.), and generate a second digital code by performing second analog-to-digital (AD) conversion based on the second signal (Takado, Paragraph 0031, AD conversion of the second signal produces a second digital signal which is a second digital code.), and
the controller is further configured to determine the line identification information based on the first digital code and the second digital code (Takado, Fig. 8, Step S840, Paragraphs 0104-0106),
wherein the line identification information is derived from a combination of the first signal and the second signal output by the first dummy circuit and the second dummy circuit based on their respective connections to the first voltage supply line and the second voltage supply line (Takado, Fig. 8, Step S840, Paragraphs 0104-0106).
Regarding claim 20, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 19 (see claim 19 analysis), wherein
the plurality array includes a plurality of pixel lines (Takado, Fig. 1),
the first dummy circuit, the second dummy circuit, and the first pixel circuit are connected to a first pixel line of the plurality of pixel lines (Takado, Fig. 1, The second row includes each of a pixel 105, and dummy pixels 110 and 111).
Regarding claim 21, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis),
wherein the operational malfunction is one malfunction selected from a group consisting of:
a connection malfunction between the controller (Takada, Fig. 1, Control Unit 107) and the scanning circuit (Takada, Fig. 1, vertical scanning circuit 102),
a malfunction of the scanning circuit,
a connection malfunction between the scanning circuit and one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a malfunction of the one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a connection malfunction between the readout circuit (Takada, Fig. 1, column circuit 103) and the one of the first plurality of dummy circuits or the second plurality of dummy circuits,
a connection malfunction between the readout circuit and the controller, and
a malfunction of the readout circuit (Takada, Fig. 8, Steps S820-S870, Paragraphs 0104-0106, Any malfunction that causes the output expected values and the actual output values of the pixels 110 and 111 to not match would be detected. Therefore, a malfunction in any of the listed group causing the output expected values and the actual output values to not match would be detected as an operation malfunction.), and
wherein the connection malfunction between the controller and the scanning circuit, the connection malfunction between the scanning circuit and the one of the first dummy circuit or the second dummy circuit, the connection malfunction between the readout circuit and the one of the first dummy circuit or the second dummy circuit, and the connection malfunction between the readout circuit and the controller is one of an open circuit or a short circuit of one or more wiring lines in a semiconductor chip (Takado, Fig. 8, Steps S840 and S870, Paragraphs 0104-0106, An open circuit or a short circuit of one or more wiring lines in the solid-state imaging device which causes a result of the classification at step S840, to be not matched would be detected as an abnormality.).
Regarding claim 23, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis), wherein
the controller is further configured to fix and set information regarding the each pixel line by using the first plurality of dummy circuits and the second plurality of dummy circuits as mask read only memory (ROM) (Takado, Fig. 1, Dummy pixels V0 and V1 are fixed and set to respective voltage lines. A row address input to corresponds to a respective pixel row with expected dummy circuit outputs. Therefore, the first plurality of dummy circuits and the second plurality of dummy circuits are seen to act as mask read only memory (see conclusion for details of a mask read only memory).).
Alternatively, claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takado et al. (US 2018/009012 A1) in view of Engelbrecht et al. (US 2015/0245019 A1) in view of Sohn (US 2014/0368710 A1) in view of Grinberg et al. (US 2013/0270422 A1).
Regarding claim 21, the combination of Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis),
wherein the operational malfunction is one malfunction selected from a group consisting of:
a connection malfunction between the controller (Takada, Fig. 1, Control Unit 107) and the scanning circuit (Takada, Fig. 1, vertical scanning circuit 102),
a malfunction of the scanning circuit,
a connection malfunction between the scanning circuit and one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a malfunction of the one of the first plurality of dummy circuits or the second plurality of dummy circuits (Takada, Fig. 1, pixels 110 or 111),
a connection malfunction between the readout circuit (Takada, Fig. 1, column circuit 103) and the one of the first plurality of dummy circuits or the second plurality of dummy circuits,
a connection malfunction between the readout circuit and the controller, and
a malfunction of the readout circuit (Takada, Fig. 8, Steps S820-S870, Paragraphs 0104-0106, Any malfunction that causes the output expected values and the actual output values of the pixels 110 and 111 to not match would be detected. Therefore, a malfunction in any of the listed group causing the output expected values and the actual output values to not match would be detected as an operation malfunction.), and
wherein the connection malfunction between the controller and the scanning circuit, the connection malfunction between the scanning circuit and the one of the first dummy circuit or the second dummy circuit, the connection malfunction between the readout circuit and the one of the first dummy circuit or the second dummy circuit, and the connection malfunction between the readout circuit and the controller is detected (Takado, Fig. 8, Steps S840 and S870, Paragraphs 0104-0106, A malfunction which causes a result of the classification at step S840, to be not matched would be detected as an abnormality.).
However, the combination of Takado, Engel and Sohn does not explicitly state wherein the connection malfunction is one of an open circuit or a short circuit of one or more wiring lines in a semiconductor chip
In reference to Grinberg et al. (hereafter referred as Grinberg), Grinberg teaches a connection malfunction; wherein the connection malfunction an open circuit or a short circuit of one or more wiring lines (Grinberg, Paragraph 0004, 0006 and 0031-0032) in a semiconductor chip (Grinberg, Paragraph 0002).
These arts are analogous since they are both related to imaging devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Takado, Engel and Sohn with the explicit teaching that short or open circuits cause malfunctions as seen in Grinberg since it is a known source of image sensor malfunctions.
Claim(s) 11 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wada et al. (US 2018/0197907 A1) in view of Takado et al. (US 2018/009012 A1) in view of Engelbrecht et al. (US 2015/0245019 A1) in view of Sohn (US 2014/0368710 A1).
Regarding claim 11, Wada teaches an imaging device (Wada, Fig. 7) comprising:
a scanning circuit (Wada, Fig. 7, vertical scanning circuit 30);
a readout circuit (Wada, Fig. 7, column circuit 40);
a pixel array comprising a plurality of pixel circuits (Wada, Fig. 7), the pixel array comprising:
a dummy circuit region (Wada, Fig. 7, second region 14, Paragraph 0025) including a first dummy circuit configured to output a first signal (Wada, Fig. 7, pixel 20B (V1), Paragraph 0067) and a second dummy circuit configured to output a second signal (Wada, Fig. 7, pixel 20B (V0), Paragraph 0067), wherein the first dummy circuit and the second dummy circuit do not include any light-receiving element (Wada, Paragraph 0038, “The pixel 20B is not necessarily required to have the photoelectric converter DB.”(;
a normal pixel region including a first pixel circuit that includes a first light-receiving element (Wada, Fig. 7, first region 12 and pixel 20A, Paragraph 0025);
a first voltage supply line coupled to the first dummy circuit, the first voltage supply line extending in a first direction (Wada, Fig. 7, Paragraph 0028, the first direction may be the horizontal direction (row direction).) and supplying a first voltage (Wada, Figs. 7, voltage supply line 19, Voltage V1, Paragraph 0067-0068);
a second voltage supply line coupled to the second dummy circuit, the second voltage supply line different from the first voltage supply line, the second voltage supply line extending in the first direction and supplying a second voltage (Wada, Figs. 7, voltage supply line 19, Voltage V0, Paragraph 0067-0068, Paragraph 0028, “Note that the voltage supply line 19 on each column may include a plurality of voltage supply lines connected to the pixels 20B that are different from each other”); and
a controller (Wada, Fig. 7, Control Unit 80, Paragraphs 0029),configured to
output a signal to control the first dummy circuit to output the first signal and control the second dummy circuit to output the second signal (Wada, Fig. 14, Paragraphs 0118),
receive the first signal and the second signal (Takado, Fig. 14, Paragraph 0118)
determine, from the first signal and the second signal, line identification information ((Wada, Fig. 14, Paragraphs 0118, actual output values are the line identification information.),
wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information (Takado, Fig. 1, Paragraphs 0104), and
perform a diagnosis process by comparing the line identification information to expected values (Wada, Fig. 14, Paragraphs 0117-0121),
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the expected values (Wada, Fig. 14, Paragraphs 0119-0121).
However, Wada does not teach a first light-shielded pixel region including a second pixel circuit that includes a second light-receiving element different from the first light-receiving element, the second light-receiving element being shielded from light; wherein, in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order; the controller configured to generate an address signal with respect to the first dummy circuit and the second dummy circuit, output the address signal to control the first dummy circuit to output the first signal and control the second dummy circuit to output the second signal, wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information corresponds to the address signal, perform a diagnosis process by comparing the line identification information to the address signal, wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the address signal.
In reference to Takado, Takado teaches a light-shielded pixel region including a second pixel circuit that includes a second light-receiving element different from the first light-receiving element, the second light-receiving element being shielded from light (Takado, Fig. 1, pixels 106, Paragraph 0023, Fig. 2, PD of pixel 106, Paragraph 0039, The first light-shielded pixel region may be the light shielded pixels of the left side or the light shielded pixels on the bottom row.).
These arts are analogous since they are both related to imaging devices with reference pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the invention of Wada with the teaching of a shielded pixel region as seen in Takado to provide the pixel array with pixels for reference of a black level for pixel noise correction (Takado, Paragraph 0023).
However, the combination of Wada and Takado does not teach wherein, in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order; the controller configured to generate an address signal with respect to the first dummy circuit and the second dummy circuit, output the address signal to control the first dummy circuit to output the first signal and control the second dummy circuit to output the second signal, wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information corresponds to the address signal, perform a diagnosis process by comparing the line identification information to the address signal, wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the address signal.
In reference to Engelbrecht et al. (here after referred as Engel), Engel teaches a controller (Engel, Fig. 2, control circuit 106, Fig. 4, “row address”, Paragraph 0029 and 0033) configured to
generate an address signals to control the plurality of pixel lines, output the address signals to control the each pixel line of the plurality of pixel lines to output signals (Engel, Fig. 2, control circuit 106, Paragraph 0029 and 0033),
receive the signals for the each pixel line, determine, from the signals for the each pixel line, line identification information for the each pixel line (Engel, Fig. 6A, Paragraphs 0039 and 0042),
wherein an arrangement of values corresponds to the address signal such that the line identification information corresponds to the address signal (Engel, Fig. 6, Paragraph 0039), and
perform a diagnosis process by comparing the line identification information to the address signal (Engel, Paragraphs 0038-0040 and 0042).
wherein the diagnosis process detects an operational malfunction indicated by a failure of correspondence between the line identification information and the address signal (Engel, Paragraphs 0038-0040 and 0042).
These arts are analogous since they are both related to error detection of image sensors. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Wada and Takado with the teaching of using the row address as a voltage pattern as seen in Engel since it is a known pattern for use in determining image sensor errors and would provide similar and expected results for providing unique patterns for performing the diagnosis process. Further, by using the row address pattern as the voltage pattern of Wada, the limitation “wherein an arrangement of the first dummy circuit coupled to the first voltage supply line and the second dummy circuit coupled to the second voltage supply line corresponds to the address signal such that the line identification information corresponds to the address signal” is met.
However, the combination of Wada, Takado and Engel does not teach wherein, in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order.
In reference to Sohn, Sohn teaches wherein in the first direction (Sohn, Fig. 2, the first direction is the horizontal direction.), a first light-shielded pixel region (Sohn, Fig. 2, Second RPA 230), a normal pixel region, and a second light shielded pixel region (Sohn, Fig. 2, First RPA 220) are disposed in this order (Sohn, Fig. 2, Paragraph 0037-0038).
These arts are analogous since they are both related to imaging devices with shielded pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Wada, Takado and Engel with the teaching of placing shielded pixel areas on both sides of the normal pixel region as seen in Sohn to compensating for shading which occurs at the left side and the right side of the array (Sohn, Paragraphs 0065-0068). That is, to place a light shielded pixel region on right side of the normal pixel region of Figure 1 of Takado. Further, by placing light-shielded pixel region on both sides of the normal pixel region, the limitation “wherein in the first direction, the first light-shielded pixel region, the normal pixel region, and the dummy circuit region are disposed in this order” is met when the first light-shielded pixel region is considered to be the right side light-shielded pixel region.
Regarding claim 16, the combination of Wada, Takado, Engel and Sohn teaches the imaging device according to claim 11 (see claim 11 analysis), further comprising: a driving unit (Wada, Fig. 7, vertical scanning circuit 30, Paragraph 0029) coupled to the first dummy circuit, the second dummy circuit, and the first pixel circuit via a control signal line (Wada, Fig. 7, pixel control line 16, Paragraph 0026),
wherein the first pixel circuit is disposed between the driving unit and the first dummy circuit along the control signal line (Wada, Fig. 7).
However, the combination of Wada, Takado, Engel and Sohn does not teach wherein the second voltage supply line is coupled to the first pixel circuit and the second pixel circuit.
In reference to Sohn, Sohn teaches wherein a fixed voltage supply line is connected to the pixel power supply line (Sohn, Fig. 3C, Voltage V, Paragraph 0048).
These arts are analogous since they are both related to imaging devices with reference pixels. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the combination of Wada, Takado, Engel and Sohn with the teaching of using the pixel power line as a fixed reference voltage as seen in Sohn since it is a known power supply line for providing a fixed voltage and would provide similar and expected results for providing a fixed reference voltage and reduce the number of power supply lines to the pixel array. Therefore, the limitation “wherein the second voltage supply line is coupled to the first pixel circuit and the second pixel circuit” is met since the second voltage supply line is the pixel power line (VDD).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
https://web.archive.org/web/20170320043511/https://en.wikipedia.org/wiki/Read-only_memory
“Mask ROM consists of a grid of word lines (the address input) and bit lines (the data output), … and can represent an arbitrary look-up table with a regular physical layout and predictable propagation delay.”
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WESLEY JASON CHIU whose telephone number is (571)270-1312. The examiner can normally be reached Mon-Fri: 8am-4pm.
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/WESLEY J CHIU/ Examiner, Art Unit 2639
/TWYLER L HASKINS/ Supervisory Patent Examiner, Art Unit 2639
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