CTNF 18/296,264 CTNF 83735 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5, 6, 8, 12, 14, 17, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1, 7, 9, 10, 13, 15, 16 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by GLEN (US 2022/0210294 A1)(hereinafter GLEN) . Re claim 1, GLEN discloses one or more non-transitory computer-readable media (NTCRM) comprising instructions, wherein execution of the instructions by a display controller is to cause the display controller to (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20): monitor clock drift of a display clock (dispelk) with respect to a Precision Time Protocol (PTP) clock (see ¶s 24, 25 for monitor clock drift of a display clock (dispelk) with respect to a Precision Time Protocol (PTP) clock (i.e. over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, furthermore, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)); and adjust a vertical synchronization signal (Vsync) based on the clock drift without broadcasting the Vsync over a network (see ¶s 24, 25 for adjust a vertical synchronization signal (Vsync) based on the clock drift without broadcasting the Vsync over a network (i.e. after the mode set has been completed and the local time bases have been synchronized with the virtual global time base, the display timing generators 120- 1, 120-2 signal the driver 150 to indicate that the display timing generators 120-1, 120-2 have adjusted the frequencies of their local time bases to match the frequency of the virtual global time base, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, furthermore, over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, moreover, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)) Re claim 7, GLEN as discussed above in claim 1 discloses all the claim limitations with additional claimed feature wherein execution of the instructions is to cause the display controller to (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20): broadcast a frame number of a frame to be played by a content playback application (see ¶s 12, 15, 18, 21 for broadcast a frame number of a frame to be played by a content playback application (i.e. the GPUs 115-1, 115-2 employ multiple buffering for outputting respective portions of frames to the display modules 141, such that the GPU 115-1, 115-2 is writing a frame to one buffer (referred to as the back buffer) while a current frame is being scanned out from another buffer (referred to as the front buffer) as described in fig. 1 paragraph 19, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command, the video timing signals indicate the start of a display cycle for displaying the generated portions of the frame as described in fig. 1 paragraph 27). Also, see fig. 3 paragraph 34) Re claim 9, GLEN discloses a method for display network synchronization, comprising: performing intra-system synchronization of a primary display system (PS) including synchronizing a primary Precision Time Protocol (PTP) clock of the PS with a primary application clock of the PS (see ¶s 24, 25 for performing intra-system synchronization of a primary display system (PS) including synchronizing a primary Precision Time Protocol (PTP) clock of the PS with a primary application clock of the PS (i.e. the display timing generators 120-1, 120-2 generate one or more clock signals to synchronize logic operations at the VPUs 105-1, 105-2 as described in fig. 1 paragraph 20, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, moreover, at block 302, the virtual global time base generator 145 generates a virtual global time base from a network protocol such as PTP, by issuing the video timing signals 165-1, 165-2 at the same time in the virtual global time base, VPUs 105-1, 105-2 effectively synchronize the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods as described in fig. 3 paragraph 33)); performing inter-system synchronization between the PS and a secondary display system (SS) including synchronizing the primary PTP clock with a secondary PTP clock of the SS (see ¶s 24, 25 for performing inter-system synchronization between the PS and a secondary display system (SS) including synchronizing the primary PTP clock with a secondary PTP clock of the SS (i.e. the display timing generators 120-1, 120-2 generate one or more clock signals to synchronize logic operations at the VPUs 105-1, 105-2 as described in fig. 1 paragraph 20, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, moreover, at block 302, the virtual global time base generator 145 generates a virtual global time base from a network protocol such as PTP, by issuing the video timing signals 165-1, 165-2 at the same time in the virtual global time base, VPUs 105-1, 105-2 effectively synchronize the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods as described in fig. 3 paragraph 33)); performing intra-system synchronization of the SS including synchronizing the secondary PTP clock with a secondary application clock of the SS (see ¶s 24, 25 for performing intra-system synchronization of the SS including synchronizing the secondary PTP clock with a secondary application clock of the SS (i.e. the display timing generators 120-1, 120-2 generate one or more clock signals to synchronize logic operations at the VPUs 105-1, 105-2 as described in fig. 1 paragraph 20, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, moreover, at block 302, the virtual global time base generator 145 generates a virtual global time base from a network protocol such as PTP, by issuing the video timing signals 165-1, 165-2 at the same time in the virtual global time base, VPUs 105-1, 105-2 effectively synchronize the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods as described in fig. 3 paragraph 33)); and performing display synchronization including: synchronizing a primary display clock of the PS with the primary PTP clock, and synchronizing a secondary display clock of the SS with the secondary PTP clock (see ¶s 24, 25 for performing display synchronization including: synchronizing a primary display clock of the PS with the primary PTP clock, and synchronizing a secondary display clock of the SS with the secondary PTP clock (i.e. the display timing generators 120-1, 120-2 generate one or more clock signals to synchronize logic operations at the VPUs 105-1, 105-2 as described in fig. 1 paragraph 20, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, moreover, at block 302, the virtual global time base generator 145 generates a virtual global time base from a network protocol such as PTP, by issuing the video timing signals 165-1, 165-2 at the same time in the virtual global time base, VPUs 105-1, 105-2 effectively synchronize the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods as described in fig. 3 paragraph 33)) Re claim 10, GLEN as discussed above in claim 9 discloses all the claim limitations with additional claimed feature wherein the performing the display synchronization includes: monitoring clock drift of a display clock with respect to the PTP clock (see ¶s 24, 25 for the performing the display synchronization includes: monitoring clock drift of a display clock with respect to the PTP clock (i.e. over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, furthermore, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)); and adjusting a vertical synchronization signal (Vsync) based on the clock drift without broadcasting the Vsync over a network (see ¶s 24, 25 for adjusting a vertical synchronization signal (Vsync) based on the clock drift without broadcasting the Vsync over a network (i.e. after the mode set has been completed and the local time bases have been synchronized with the virtual global time base, the display timing generators 120-1, 120-2 signal the driver 150 to indicate that the display timing generators 120-1, 120-2 have adjusted the frequencies of their local time bases to match the frequency of the virtual global time base, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, furthermore, over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, moreover, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)) Re claim 13, GLEN as discussed above in claim 7 discloses all the claimed limitations of claim 13. Re claim 15, GLEN discloses a display controller, comprising: display clock (dispclk) monitor circuitry to generate a correction signal based on a clock drift of a dispclk with respect to a reference time of a Precision Time Protocol (PTP) clock (see ¶s 24, 25 for display clock (dispclk) monitor circuitry to generate a correction signal based on a clock drift of a dispclk with respect to a reference time of a Precision Time Protocol (PTP) clock (i.e. over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, furthermore, at block 302, the virtual global time base generator 145 generates a virtual global time base from a network protocol such as PTP, at block 304, each of the VPU display timing generators 120-1, 120-2 generates a local time base, at block 306, the VPUs 105-1, 105-2 use the local time base frequency to generate fixed refresh rate video timing signals for each of the display modules 141 for which the VPUs 105-1, 105-2 generate frames or portions of frames for display, by issuing the video timing signals 165-1, 165-2 at the same time in the virtual global time base, VPUs 105-1, 105-2 effectively synchronize the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods as described in fig. 3 paragraph 33, moreover, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34). Also, see fig. 2 paragraphs 20, 27, 29-31); and vertical synchronization signal (Vsync) timer circuitry connected to the dispclk monitor circuitry, wherein the Vsync timer circuitry is to: adjust generation of a Vsync based on the correction signal, and output the Vsync to a display device, wherein the Vsync is to cause the display device to synchronize output of a set of frames to the PTP time (see ¶s 24, 25 for vertical synchronization signal (Vsync) timer circuitry connected to the dispclk monitor circuitry, wherein the Vsync timer circuitry is to: adjust generation of a Vsync based on the correction signal, and output the Vsync to a display device, wherein the Vsync is to cause the display device to synchronize output of a set of frames to the PTP time (i.e. after the mode set has been completed and the local time bases have been synchronized with the virtual global time base, the display timing generators 120-1, 120-2 signal the driver 150 to indicate that the display timing generators 120-1, 120-2 have adjusted the frequencies of their local time bases to match the frequency of the virtual global time base, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command, the video timing signals indicate the start of a display cycle for displaying the generated portions of the frame, simultaneous (or near simultaneous) issuance of the video timing signals 165-1, 165-2 by the VPUs 105-1, 105-2 effectively synchronizes the frequencies and phases of the display cycles of each of the display modules 141 based on the virtual global time base to within a few display line periods, which is a difference that is not perceptible by the human eye as described in fig. 1 paragraph 27, furthermore, once the VPU display timing generators 120-1, 120-2 start at the same time on the virtual global time base with frequencies that match the frequency of the virtual global time base, the VPU display timing generators 120-1, 120-2 remain essentially locked in both frequency and phase with each other, the VPUs 105-1, 105-2 generate new frames at the frequency of the virtual global time base and the display modules 141 refresh at the same rate, within a small margin such as a few line periods as described in fig. 1 paragraph 28, moreover, a display timing generator 220 of a VPU 105-1, 105-2 and a timing control 225 for synchronizing a local time base frequency to a virtual global time base frequency in accordance with some embodiments, the display timing generator 220 includes a PLL 215 that receives a reference clock signal from a crystal oscillator 210 or other clock source and based on the reference clock signal generates a plurality of base clock signals, the display timing generator 220 combines the base clock signals to generate a local time base 230 at a frequency indicated by signal received from the timing control 225 as described in fig. 2 paragraph 29, additionally, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34). Also, see paragraphs 20-22, 28, 30-33) Re claim 16, GLEN as discussed above in claim 15 discloses all the claimed limitations but fails to explicitly teach wherein the dispclk monitor circuitry is to (i.e. a display timing generator 220 of a VPU 105-1, 105-2 and a timing control 225 as described in fig. 2 paragraph 29): receive the reference time from a network interface controller (NIC), wherein the PTP clock is part of the NIC (see ¶ 25 for receive the reference time from a network interface controller (NIC), wherein the PTP clock is part of the NIC (i.e. the processing system includes a virtual global time base generator 145 to generate a network protocol-based virtual global time base for the VPUs 105-1, 105-2, the virtual global time base generator 145 is implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof, the virtual global time base generator 145 is incorporated in the VPUs 105-1, 105-2, the virtual global time base generator 145 serves as the PTP master clock signal, the virtual global time base generator 145 selects a clock signal generated by another networked component as the PTP master clock signal as described in fig. 1 paragraph 24). Also, see figs. 2-3 paragraphs 27, 29-34) Re claim 19, GLEN as discussed above in claim 15 discloses all the claim limitations with additional claimed feature further comprising: microcontroller circuitry (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20) to provide an indication of a frame number of a current frame to be rendered (see ¶s 12, 15, 18, 21 for provide an indication of a frame number of a current frame to be rendered (i.e. the GPUs 115-1, 115-2 employ multiple buffering for outputting respective portions of frames to the display modules 141, such that the GPU 115-1, 115-2 is writing a frame to one buffer (referred to as the back buffer) while a current frame is being scanned out from another buffer (referred to as the front buffer) as described in fig. 1 paragraph 19, furthermore, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command, the video timing signals indicate the start of a display cycle for displaying the generated portions of the frame as described in fig. 1 paragraph 27). Also, see fig. 3 paragraph 34) Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-22-aia AIA Claim s 2, 3, 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over GLEN (US 2022/0210294 A1)(hereinafter GLEN) as applied to claim s 1, 7, 9, 10, 13, 15, 16 and 19 above, and further in view of Law et al. (US 9,036,084 B2)(hereinafter Law) . Re claim 2, GLEN as discussed above in claim 1 discloses all the claim limitations with additional claimed feature wherein execution of the instructions is to cause the display controller to (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20): GLEN fails to explicitly teach receive a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock. However, Law explicitly teaches receive a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock (see fig. 2 col. 6 lines 13-16 for receive a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock (i.e. an access point 404 may in some examples be a router or other access point module that may receive data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmit the data to each of the display panels 402, 412, 422, and 432 as described in fig. 4 col. 7 lines 39-45). Also, see col. 7 lines 46-67, col. 8 lines 1-6) Therefore, taking the combined teachings of GLEN and Law as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (PPS) into the system of GLEN as taught by Law. One would have been motivated to incorporate the above feature as taught by Law into the system of GLEN for the benefit of having display panels 402, 412, 422, and 432 which may be used as display panels 104 illustrated in FIGS. 1A and 1B, wherein as shown in the display panel 402, each display panel may include a cluster global clock 442, a genlock component 452, and display hardware 472, wherein one of the cluster global clocks 442 of one of the display panels 402, 412, 422, 432 may function as a master clock, to which other cluster global clocks 442, functioning as slave clocks, may synchronize, wherein all the cluster global clocks 442 may receive the same network time signal and synchronize to the network time signal rather than a master clock signal, wherein an access point 404 may in some examples be a router or other access point module that may receive data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmit the data to each of the display panels 402, 412, 422, and 432 in order to ease the processing time and improve efficiency when receiving data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmitting the data to each of the display panels 402, 412, 422, and 432 (see fig. 4 col. 7 lines 29-45) Re claim 3, the combination of GLEN and Law as discussed above in claim 2 discloses all the claim limitations with additional claimed feature taught by GLEN wherein execution of the instructions is to cause the display controller to (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20): GLEN fails to explicitly teach determine the clock drift of the dispelk with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock. However, the reference of Law explicitly teaches determine the clock drift of the dispelk with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock (see col. 7 lines 23-58 for determine the clock drift of the dispelk with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock (i.e. first, all the display panels 402, 412, 422, and 432 may be synchronized to the same global cluster time, using NTP, GPS-PPS signal, or PTP, for NTP and PTP, one device in the network may be chosen as the master (e.g., the panel 402 in the array 400 of FIG. 4), wherein all the other panels 412, 422, and 432 may follow the master clock through the closed network among these devices using these protocols, wherein PTP has a mechanism to select the optimal master clock source among the display panels, for example, PTP may use Best Master Clock (BMC) algorithm as specified in IEEE 1588 to select the optimal master source among the display panels, wherein for GPS-PPS signal, the GPS satellite clock may serve as the master clock and all display panels may follow the satellite clock, therefore, various example systems may work within a closed network system, including without access to the Internet as described in fig. 4 col. 7 lines 59-67, col. 8 lines 1-7)) Therefore, taking the combined teachings of GLEN and Law as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (PPS) into the system of GLEN as taught by Law. Per claim 3, GLEN and Law are combined for the same motivation as set forth in claim 2 above. Re claim 4, the combination of GLEN and Law as discussed above in claim 3 discloses all the claim limitations with additional claimed feature taught by GLEN wherein execution of the instructions is to cause the display controller to (i.e. the display timing generators 120-1, 120-2 and the timing control modules 125-1, 125-2 are implemented as hard-coded or programmable logic, one or more processors executing software/firmware instructions, or any combination thereof as described in fig. 1 paragraph 20): determine a step value based on the clock drift and a desired Vsync frequency (see ¶s 24, 25 for determine a step value based on the clock drift and a desired Vsync frequency (i.e. after the mode set has been completed and the local time bases have been synchronized with the virtual global time base, the display timing generators 120-1, 120-2 signal the driver 150 to indicate that the display timing generators 120-1, 120-2 have adjusted the frequencies of their local time bases to match the frequency of the virtual global time base, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, furthermore, over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, moreover, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)) Re claim 11, GLEN as discussed above in claim 10 discloses all the claim limitations with additional claimed feature wherein the performing the display synchronization includes (see ¶s 24, 25 for the performing the display synchronization (i.e. the display timing generators 120-1, 120-2 generate one or more clock signals to synchronize logic operations at the VPUs 105-1, 105-2 as described in fig. 1 paragraph 20): and determining a step value based on the clock drift and a desired Vsync frequency (see ¶s 24, 25 for determining a step value based on the clock drift and a desired Vsync frequency (i.e. after the mode set has been completed and the local time bases have been synchronized with the virtual global time base, the display timing generators 120-1, 120-2 signal the driver 150 to indicate that the display timing generators 120-1, 120-2 have adjusted the frequencies of their local time bases to match the frequency of the virtual global time base, in response to receiving the start command, the VPUs 105-1, 105-2 send fixed refresh rate video timing signals, including information such as a vertical synchronization (vsync) command, fixed refresh rate, line rate, and pixel clock timing, to the display modules 141 via the display interfaces 130-1, 130-2 and interconnects 135-1, 135-2 at the time indicated by the start command as described in fig. 1 paragraph 27, furthermore, over time, it is possible that the frequency of the local time base of one or more of the VPUs 105-1, 105-2 will drift and become faster or slower than the virtual global time base due to factors such as heat, to maintain synchronicity over time, the display timing generators 120-1, 120-2 monitor differences between the frequencies of the local time base and the virtual global time base and re-adjust the local time base frequency to match the virtual global time base if the difference exceeds a threshold as described in fig. 1 paragraph 28, moreover, the timing control modules 125-1, 125-2 determine if the frequencies of the local time bases have drifted far enough from the virtual global time base frequency to cause the displays to be more than a threshold amount (such as a display line) out of sync as described in fig. 3 paragraph 34)) GLEN fails to explicitly teach receiving a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock; determining the clock drift of the display clock with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock. However, the reference of Law explicitly teaches receiving a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock (see fig. 2 col. 6 lines 13-16 for receiving a pulse per second signal (PPS) from a network interface controller (NIC), wherein the PPS is based on the PTP clock (i.e. an access point 404 may in some examples be a router or other access point module that may receive data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmit the data to each of the display panels 402, 412, 422, and 432 as described in fig. 4 col. 7 lines 39-45). Also, see col. 7 lines 46-67, col. 8 lines 1-6); determining the clock drift of the display clock with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock (see col. 7 lines 23-58 for determining the clock drift of the display clock with respect to the PPS, wherein the PPS is a frame of reference for the PTP clock (i.e. first, all the display panels 402, 412, 422, and 432 may be synchronized to the same global cluster time, using NTP, GPS-PPS signal, or PTP, for NTP and PTP, one device in the network may be chosen as the master (e.g., the panel 402 in the array 400 of FIG. 4), wherein all the other panels 412, 422, and 432 may follow the master clock through the closed network among these devices using these protocols, wherein PTP has a mechanism to select the optimal master clock source among the display panels, for example, PTP may use Best Master Clock (BMC) algorithm as specified in IEEE 1588 to select the optimal master source among the display panels, wherein for GPS-PPS signal, the GPS satellite clock may serve as the master clock and all display panels may follow the satellite clock, therefore, various example systems may work within a closed network system, including without access to the Internet as described in fig. 4 col. 7 lines 59-67, col. 8 lines 1-7)) Therefore, taking the combined teachings of GLEN and Law as a whole, it would have been obvious before the effective filing date of the claimed invention to incorporate this feature (PPS) into the system of GLEN as taught by Law. One would have been motivated to incorporate the above feature as taught by Law into the system of GLEN for the benefit of having display panels 402, 412, 422, and 432 which may be used as display panels 104 illustrated in FIGS. 1A and 1B, wherein as shown in the display panel 402, each display panel may include a cluster global clock 442, a genlock component 452, and display hardware 472, wherein one of the cluster global clocks 442 of one of the display panels 402, 412, 422, 432 may function as a master clock, to which other cluster global clocks 442, functioning as slave clocks, may synchronize, wherein all the cluster global clocks 442 may receive the same network time signal and synchronize to the network time signal rather than a master clock signal, wherein an access point 404 may in some examples be a router or other access point module that may receive data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmit the data to each of the display panels 402, 412, 422, and 432 in order to ease the processing time and improve efficiency when receiving data (e.g., a network time signal) from a source (e.g., a master clock in the display panel 402 using, for example, NTP, GPS-PPS signal, or PTP) and transmitting the data to each of the display panels 402, 412, 422, and 432 (see fig. 4 col. 7 lines 29-45) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE M MESA whose telephone number is (571)270-1706. The examiner can normally be reached Monday-Friday 8:30AM-6:00PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thai Tran can be reached at 571-272-7382. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. 5/13/2026 /JOSE M. MESA/ Examiner Art Unit 2484 /HUNG Q DANG/Primary Examiner, Art Unit 2484 Application/Control Number: 18/296,264 Page 2 Art Unit: 2484 Application/Control Number: 18/296,264 Page 3 Art Unit: 2484 Application/Control Number: 18/296,264 Page 4 Art Unit: 2484 Application/Control Number: 18/296,264 Page 5 Art Unit: 2484 Application/Control Number: 18/296,264 Page 6 Art Unit: 2484 Application/Control Number: 18/296,264 Page 7 Art Unit: 2484 Application/Control Number: 18/296,264 Page 8 Art Unit: 2484 Application/Control Number: 18/296,264 Page 9 Art Unit: 2484 Application/Control Number: 18/296,264 Page 10 Art Unit: 2484 Application/Control Number: 18/296,264 Page 11 Art Unit: 2484 Application/Control Number: 18/296,264 Page 12 Art Unit: 2484 Application/Control Number: 18/296,264 Page 13 Art Unit: 2484 Application/Control Number: 18/296,264 Page 14 Art Unit: 2484 Application/Control Number: 18/296,264 Page 15 Art Unit: 2484 Application/Control Number: 18/296,264 Page 17 Art Unit: 2484 Application/Control Number: 18/296,264 Page 18 Art Unit: 2484 Application/Control Number: 18/296,264 Page 19 Art Unit: 2484 Application/Control Number: 18/296,264 Page 20 Art Unit: 2484 Application/Control Number: 18/296,264 Page 21 Art Unit: 2484 Application/Control Number: 18/296,264 Page 22 Art Unit: 2484 Application/Control Number: 18/296,264 Page 23 Art Unit: 2484 Application/Control Number: 18/296,264 Page 24 Art Unit: 2484
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