Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Such claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are all in Claim 27:
a data analysis unit configured to acquire a plurality of data elements from a memory, evaluate each of the plurality of data elements relative to at least one criteria, and generate an output that includes a plurality of validity indicators identifying a first plurality of data elements among the plurality of data elements that validly satisfy the at least one criteria and identifying a second plurality of data elements among the plurality of data elements that do not validly satisfy the criteria;
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 27-28, 33, 40-42, and 46 are rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1).
Regarding Claim 27, Morishige teaches a data processing unit, comprising:
a data analysis unit configured to acquire a plurality of data elements from a memory (
Morishige discloses, “In addition, the memory control section 154 erases the invalid data in the data which is copied to the predetermined area in the RAM 16, extracts the valid data from the data which is copied to the predetermined area in the RAM 16,” ¶ 0112. ¶ 0042 further provides an example, as seen below.),
evaluate each of the plurality of data elements relative to at least one criteria (
Morishige discloses, “In addition, the memory control section 154 erases the invalid data in the data which is copied to the predetermined area in the RAM 16, extracts the valid data from the data which is copied to the predetermined area in the RAM 16,” ¶ 0112.),
anddetermine a plurality of validity indicators identifying a first plurality of data elements among the plurality of data elements that validly satisfy the at least one criteria and identifying a second plurality of data elements among the plurality of data elements that do not validly satisfy the criteria
Morishige teaching identifying stale data, stating “The control unit 15 writes ‘A=1’ and ‘B=2’ into the data save area in the flash memory 17 as data on A and B in a state where no data is written in the data save area in the flash memory 17 (a data-erased state). The latest data so written is also called valid data. Thereby, the data save area in the flash memory 17 is brought into a state where the data is written in areas for 2 pages in the 15 pages,” ¶ 0041, and “Next, in a case where the data on A and B are to be updated to ‘A=2’ and ‘B=0’ and ‘C=5’ is to be newly written into the data save area in the flash memory 17 as data on C, the control unit 15 sets the previously written ‘A=1’and ‘B=2’ as invalid data and writes ‘A=2’ and ‘B=0’ and then ‘C=5’ into new areas (pages),” ¶ 0042.
Fig. 2 visually illustrates the same process, cells’ background color indicating whether data are stale or not.
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and a data packer configured to generate, based onthe validity determination of the data analysis unit, a packed data output including the first plurality of data elements and omitting the second plurality of data elements (
Morishige discloses, “In addition, the memory control section 154 erases the invalid data in the data which is copied to the predetermined area in the RAM 16, extracts the valid data from the data which is copied to the predetermined area in the RAM 16 and writes the extracted data to the predetermined positions of the above-described predetermined area in the RAM 16 (for example, packing the data into the predetermined area one after another),” ¶ 0112. Fig. 2 visually illustrates the same process.).
Morishige does not teach generat[ing] an output that includes Morishige’s validity determination.
However, Higgins teaches generat[ing] an output that includes a validity determination (
Higgins discloses, “In some embodiments, each logical address of a plurality of logical addresses has a corresponding stale flag and each stale flag is stored in a logical-to-physical table used for mapping logical addresses to physical addresses,” ¶ 0025, and “Because the stale flag is co-located with a logical-to-physical entry, multiple memory accesses can be reduced and additional memory is not required to support the invention. Using the stale flag increases the visibility of valid and invalid/stale data,” ¶ 0102.).
Morishige and Higgins are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige to incorporate the teachings of Higgins and provide generating an output that includes a validity determination. Doing so would help allow for efficiently checking if a data element is valid or not (Higgins discloses, “Allocating the stale flag in the logical-to-physical tabling system can quickly detect overlap in a single lookup operation,” ¶ 0101.).
Regarding Claim 28, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the plurality of validity indicators further identify which of the plurality of data elements do not validly satisfy the at least one criteria (
Higgins discloses, “Because the stale flag is co-located with a logical-to-physical entry, multiple memory accesses can be reduced and additional memory is not required to support the invention. Using the stale flag increases the visibility of valid and invalid/stale data,” ¶ 0102.).
Regarding Claim 33, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the plurality of data elements include a plurality of row values from a single column of the database (
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Fig. 2 of Morishige discloses a plurality of row values from a single column of a database.).
Regarding Claim 40, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the plurality of indicators include single bit values (
Higgins discloses “It is possible to make the stale flag a count to address multiple versions but there is always an upper limit based on the number of bits available to the stale flag. Although a single bit implementation is described, it is understood that a multiple bit implementation would also be valid to increase the number of in-flight versions allowed,” ¶ 0092.).
Morishige and Higgins are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige to incorporate the teachings of Higgins and provide wherein the plurality of indicators include single bit values. Doing so would help allow for efficiently checking if a data element is valid or not (Higgins discloses, “Allocating the stale flag in the logical-to-physical tabling system can quickly detect overlap in a single lookup operation,” ¶ 0101.).
Regarding Claim 41, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the data analysis unit is further configured to execute one or more of logic, algebraic, or string operations relative to the plurality of data elements (
Morishige discloses “For example, in a case where the control unit 15 decides that the amount of data written in the data save area in the flash memory 17 is not less than the threshold value HP (YES), the control unit 15 proceeds to a process of step S107. On the other hand, in a case where the control unit 15 decides that the amount of data which is written in the data save area in the flash memory 17 is less than the threshold HP (NO), the control unit 15 terminates execution of the POST processing without executing the process of step S107,” ¶ 0070.).
Regarding Claim 42, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the data packer uses the plurality of validity indicators included in the output of the data analysis unit to identify the first plurality of data elements to include in the output of the data packer (
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Fig. 2 of Morishige indicates that the cell status indicates the validity of each data element, and the first plurality of data elements that are data packed are shown in the last part (f) of Fig. 2 of Morishige.).
Regarding Claim 46, Morishige in view of Higgins teaches the data processing unit of claim 27, wherein the data packer output further includes validity metadata (
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Higgins’ Fig. 4 and Fig. 5 show that the data being written includes stale flags.),
and wherein the validity metadata includes at least one source identifier associated with a source location for the first plurality of data elements and where the validity metadata also includes one or more identifiers associated with the first plurality of data elements (
Higgins’ Fig. 4 and Fig. 5 show that the data being written includes both the index and physical addresses of each data element.).
Morishige and Higgins are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige to incorporate the teachings of Higgins and provide wherein the data packer output further includes validity metadata, and wherein the validity metadata includes at least one source identifier associated with a source location for the first plurality of data elements and where the validity metadata also includes one or more identifiers associated with the first plurality of data elements. Doing so would allow for tracking the validity or invalidity status of each data element even after the data packing. Doing so would help allow for efficiently checking if a data element is valid or not (Higgins discloses, “Allocating the stale flag in the logical-to-physical tabling system can quickly detect overlap in a single lookup operation,” ¶ 0101.).
Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Shavit (US 10552349 B1).
Regarding Claim 29, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the data packer output further includes validity metadata, the validity metadata includes one or more identifiers associated with the first plurality of data elements.
However, Shavit teaches wherein the data packer output further includes validity metadata, the validity metadata includes one or more identifiers associated with the first plurality of data elements (
Shavit discloses “In some embodiments, address table 203 may further include a validity metadata flag, associating a validity value (e.g. ‘valid’ or ‘invalid’) to each physical block that is fetched by accelerator 200 from storage 300,” Col 7, Lines 55-57.)
Morishige in view of Higgins, and Shavit are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Shavit and provide wherein the data packer output further includes validity metadata, the validity metadata includes one or more identifiers associated with the first plurality of data elements. Doing would help increase memory operation efficiency and correctness. Doing so would help prevent redundant memory operations (Shavit discloses, “In some embodiments, host 100 may execute two or more processes that may require access to the same physical data blocks. Accelerator may respond to a first read-request, initiated by a first process with a first read-response 30, containing the requested data. If a second process sends a second read-request that requires access to the same data block, accelerator 200 may send a read-response that only includes an indication that the data block has already been read, and is therefore already available on the memory of host 100,” Col 7, Lines 66-67 and Col 8, Lines 1-8.).
Regarding Claim 30, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the data packer output is transmitted to one or more destination chips external to a chip on which the data packer resides.
However, Shavit teaches wherein the data packer output is transmitted to one or more destination chips external to a chip on which the data packer resides (
Shavit discloses “For example, accelerator 200 may fetch data from at least one data block of storage module 300 and may write the data in a sequential order (e.g. data D1, data D2, data D3 . . . ) into staging buffer 210,” Col 5, Line 67 and Col 6, Lines 1-3, and “Alternately, staging buffer 210 may be included within a memory space that is not integrated within accelerator 200, such as an external memory module 401,” Col 6, Lines 7-9.).
Morishige in view of Higgins, and Shavit are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Shavit and provide wherein the data packer output is transmitted to one or more destination chips external to a chip on which the data packer resides. Doing so would help reduce load for the accelerator by offloading the storage of the load to an external memory (Shavit discloses, “Alternately, staging buffer 210 may be included within a memory space that is not integrated within accelerator 200, such as an external memory module 401,” Col 6, Lines 7-9.).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Xiang (US 20210089479 A1).
Regarding Claim 31, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach further including a controller configured to communicate one or more commands to the data analysis unit, wherein the one or more commands include a filter command, and wherein the at least one criteria is associated with the filter command.
However, Xiang teaches further including a controller configured to communicate one or more commands to the data analysis unit, wherein the one or more commands include a filter command, and wherein the at least one criteria is associated with the filter command (
Xiang discloses “In some improved solutions, a snoop filter (Snoop Filter) is disposed in the multi-core processor, and the snoop filter is used to record validity of data in the local caches of the processor cores,” ¶ 0039, and “The snoop and caching module 220 is a shared cache module with an embedded snoop filter,” ¶ 0053.).
Morishige in view of Higgins, and Xiang are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Xiang and provide further including a controller configured to communicate one or more commands to the data analysis unit, wherein the one or more commands include a filter command, and wherein the at least one criteria is associated with the filter command. Doing so would help determine valid data more quickly (Shavit discloses, “When a processor core of the multi-core processor initiates a data request specific to a shared address, the multi-core interconnection bus first accesses the snoop filter to determine whether there is valid data in the local caches of the processor cores, and then requests data only from a processor core storing valid data, thereby avoiding unnecessary bus-based transmission and reducing transmission blocking,” ¶ 0039.).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Resch (US 20180074899 A1).
Regarding Claim 32, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the at least one criteria includes one or more reference values to be compared to data values included in the plurality of data elements.
However, Resch teaches wherein the at least one criteria includes one or more reference values to be compared to data values included in the plurality of data elements (
Resch discloses “The validator 514 can validate the data 498 to produce a validity indicator 520 based on a comparison of the received integrity value 516 to the calculated integrity value 518,” ¶ 0046.).
Morishige in view of Higgins, and Resch are both considered to be analogous to the claimed invention because they are in the same field of computer-based storage. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Resch and provide wherein the at least one criteria includes one or more reference values to be compared to data values included in the plurality of data elements. Doing so would help determine if the data elements are valid or not (Resch discloses, “or example, the validator 514 can generate the validity indicator 520 to indicate that the data 498 is valid when the received integrity value 516 is substantially the same as the calculated integrity value 518,” ¶ 0046.).
Claims 34-35 is rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Ziauddin (US 11354310 B2).
Regarding Claim 34, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the evaluation performed by the data analysis unit results from a query relative to a database stored in the memory, and wherein the evaluation includes a filter function.
However, Ziauddin teaches wherein the evaluation performed by the data analysis unit results from a query relative to a database stored in the memory, and wherein the evaluation includes a filter function (
Ziauddin discloses “Based on the rewritten query, COUNT(*) is derived from (a) fresh zones in the zone map and (b) scanning customers data pertaining to the stale or missing zones. In the rewritten query, the second inner SELECT computes COUNT(*) of customers table rows that belong to zones that are either stale or missing from the zone map,” Col 13, Lines 13-18, and “Computer system 400 also includes a main memory 406, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 402 for storing information and instructions to be executed by processor 404,” Col 14, Lines 63-66).
Morishige in view of Higgins, and Ziauddin are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Ziauddin and provide wherein the evaluation performed by the data analysis unit results from a query relative to a database stored in the memory, and wherein the evaluation includes a filter function. Doing so would help increase the efficiency of operations related to determining validity/staleness conditions by using database tools. Doing so would also help improve the performance of the query (Ziauddin discloses, “Techniques are described herein for using of zone maps to improve the performance of a much wider range of queries than those for which zone maps are currently used,” Col 2, Lines 12-14.).
Regarding Claim 35, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the evaluation of the plurality of data elements includes at least one of a scan, filter, join, aggregate, or sort operation.
However, Ziauddin teaches wherein the evaluation of the plurality of data elements includes at least one of a scan, filter, join, aggregate, or sort operation (
Ziauddin teaches “filter” and “aggregate” options, stating “. . . . wherein one or more of the zones, of the plurality of zones, are marked as stale; processing, by the database server, a query that: includes a filter condition, and requires generation of a target aggregation of values from the particular column; and wherein said processing the query comprises: while the one or more zones are marked as stale: determining, based on the filter condition, that a first zone of the plurality of zones is a no-overlap zone, determining, based on the filter condition, that a second zone of the plurality of zones is a total-overlap zone, pruning the first zone responsive to determining that the first zone is a no -overlap zone, determining that the second zone is not stale, and using a per-zone count value of the second zone, obtained from the zone map, to derive the target aggregation of values responsive to determining that the second zone is a total-overlap zone and responsive to determining that the second zone is not stale.” Claim 36.
Ziauddin teaches scan and aggregate operations, stating “According to one embodiment, the transparently added aggregate columns include: COUNT(*) aggregate stored in a column named zone_rows$, current state of individual zone in a column named zone_state$ (0 signifies fresh zone, 1 signifies stale zone), and level of aggregation in a column named zone_level$ (0 signifies aggregates per zone, 1 signifies aggregates per table partition),” Col 12, Lines 30-40, and “Based on the rewritten query, COUNT(*) is derived from (a) fresh zones in the zone map and (b) scanning customers data pertaining to the stale or missing zones. In the rewritten query, the second inner SELECT computes COUNT(*) of customers table rows that belong to zones that are either stale or missing from the zone map,” Col 13, Lines 13-18.
).
Morishige in view of Higgins, and Ziauddin are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Ziauddin and provide wherein the evaluation of the plurality of data elements includes at least one of a scan, filter, join, aggregate, or sort operation. Doing so would help increase the efficiency of operations related to determining validity/staleness conditions by using database tools. Doing so would also help improve the performance of the query (Ziauddin discloses, “Techniques are described herein for using of zone maps to improve the performance of a much wider range of queries than those for which zone maps are currently used,” Col 2, Lines 12-14.).
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Lai (US 20200167076 A1).
Regarding Claim 36, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the data analysis unit includes a single instruction, multiple data (SIMD) configured processor.
However, Lai teaches wherein the data analysis unit includes a single instruction, multiple data (SIMD) configured processor (
Lai discloses “An example of a data write unit 402 includes a SIMD unit 138 writing data to the compressed data set 407 under the control of a shader program,” ¶ 0036.).
Morishige in view of Higgins, and Lai are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Lai and provide wherein the data analysis unit includes a single instruction, multiple data (SIMD) configured processor. Doing so would help allow for increased efficiency due to the SIMD paradigm (Lai discloses, “As described in further detail below, the APD 116 includes one or more parallel processing units configured to perform computations in accordance with a single-instruction-multiple-data (‘SIMD’) paradigm,” ¶ 0015.).
Claims 37 and 44-45 are rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Goss (US 20110231623 A1).
Regarding Claim 37, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the plurality of validity indicators included in the output of the data analysis unit are included in a bit mask.
However, Goss teaches wherein the plurality of validity indicators included in the output of the data analysis unit are included in a bit mask (
Goss discloses “The descriptor data may further employ a bitmask with status bits that indicate the status (valid or stale) of each stored LA,” ¶ 0017.).
Morishige in view of Higgins, and Goss are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Goss and provide wherein the plurality of validity indicators included in the output of the data analysis unit are included in a bit mask. Doing so would help allow for increased efficiency of resource management (Goss discloses, “…system management can be improved by minimizing the number of metadata operations through monitoring various portions of a memory space for stale data in real-time by maintaining mapping structures in separate memories or caches that can direct portions of memory that contain a large percentage of stale data to be erased and made available for new data,” ¶ 0016.).
Regarding Claim 44, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the data packer is configured to use a packing mask included in a predicate register to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer.
However, Goss teaches wherein the data packer is configured to use a packing mask included in a predicate register to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer (
Goss discloses “The descriptor data may further employ a bitmask with status bits that indicate the status (valid or stale) of each stored LA,” ¶ 0017, and “It is contemplated that write data will be accumulated and written a page at a time, so that the page descriptor data can be generated and written during the writing of the associated LAs. If less than a complete page of data are written, filler bits can be appended to fill the page, and the next write operation will commence with the next available page in the GCU,” ¶ 0042.).
After the combination of Morishige in view of Higgins with Goss, Goss’ bitmask is used to represent the status of data in each cell as shown in Morishige’s Fig. 2:
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The disclosed bitmask, including valid and invalid status of the tables shown in Morishige’s Fig. 2, is mapped to the claimed “packing mask included in a predicate register.” The bitmask is stored in user memory/register space. See Goss’ Fig. 3.
After the combination of Morishige in view of Higgins with Goss, the bitmask guides the process as shown in Morishige’s Fig. 2. When having accumulated one or more data segments to be “Almost full,” a predetermined size, the accumulated one or more data segments are packed as output as shown in Fig. 2 (f).
Morishige in view of Higgins, and Goss are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Goss and provide wherein the data packer is configured to use a packing mask included in a predicate register to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer. Doing so would help allow for increased efficiency of resource management (Goss discloses, “…system management can be improved by minimizing the number of metadata operations through monitoring various portions of a memory space for stale data in real-time by maintaining mapping structures in separate memories or caches that can direct portions of memory that contain a large percentage of stale data to be erased and made available for new data,” ¶ 0016.).
Regarding Claim 45, Morishige in view of Higgins and Goss teaches the data processing unit of claim 44, wherein the predetermined size is associated with a size of the predicate register (
After the combination of Morishige in view of Higgins with Goss, Goss’ bitmask is used to represent the status of data in each cell as shown in Morishige’s Fig. 2:
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The size of the bitmask corresponds to capacity or fullness of memory region, a predetermined size.).
Morishige in view of Higgins, and Goss are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Goss and provide wherein the predetermined size is associated with a size of the predicate register. Doing so would help allow for increased efficiency of resource management (Goss discloses, “…system management can be improved by minimizing the number of metadata operations through monitoring various portions of a memory space for stale data in real-time by maintaining mapping structures in separate memories or caches that can direct portions of memory that contain a large percentage of stale data to be erased and made available for new data,” ¶ 0016.).
Claims 38-39 are rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Lueh (US 20200394041 A1).
Regarding Claim 38, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria.
However, Lueh teaches wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria (
Lueh discloses “Assuming 8 threads per execution unit 1413 and 64 shared registers/threads on average results in mapping table 1508 encoding 512 (e.g., 8*64) unique physical storage locations. In one embodiment, the 3.sup.rd column can have 1 of 512 address values, requiring 9 bits for each row. The 4.sup.th column indicates the validity of data using 1 bit,” ¶ 0204).
Morishige in view of Higgins, and Lueh are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Lueh and provide wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria. Doing so would help allow for increased efficiency for looking up values based on indices (Lueh discloses, “Accordingly, register sharing mechanism 1410 includes mapping table 1508 to perform lookups of virtual address to physical address mappings,” ¶ 0203.).
Regarding Claim 39, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria and further identify row values in a column of data of a database that do not satisfy the at least one criteria.
However, Lueh teaches wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria and further identify row values in a column of data of a database that do not satisfy the at least one criteria (
Lueh discloses “The 4.sup.th column indicates the validity of data using 1 bit,” ¶ 0204.).
Morishige in view of Higgins, and Lueh are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Lueh and provide wherein the plurality of validity indicators identify row values in a column of data of a database that satisfy the at least one criteria and further identify row values in a column of data of a database that do not satisfy the at least one criteria. Doing so would help allow for increased efficiency for looking up values based on the criteria. (Lueh discloses, “Accordingly, register sharing mechanism 1410 includes mapping table 1508 to perform lookups of virtual address to physical address mappings,” ¶ 0203.).
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Morishige (US 20200133562 A1) in view of Higgins (US 20150046665 A1) and Nam (US 10445014 B2).
Regarding Claim 43, Morishige in view of Higgins teaches the data processing unit of claim 27. Morishige in view of Higgins does not teach wherein the data packer is configured to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer.
However, Nam teaches wherein the data packer is configured to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer (
Nam discloses “The memory controller 300 may temporarily and incrementally store the first data segments Di as received from the host 120 in a buffer (e.g., buffer 340 shown in FIG. 2) included in the memory controller 300. Once the total (or cumulative) size of the received data (e.g., a sequence of first data segments Di) temporarily stored in the buffer 340 reaches the second size, the cumulatively stored data in the buffer 340 may be programmed to the NVM 400 under the control of the memory controller 300,” Col 5, Lines 32-40.).
Morishige in view of Higgins, and Nam are both considered to be analogous to the claimed invention because they are in the same field of computer memory management. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Morishige in view of Higgins to incorporate the teachings of Nam and provide wherein the data packer is configured to accumulate one or more data segments of a predetermined size before including the accumulated one or more data segments in the output of the data packer. Doing so would help allow for increased efficiency of data transferring. (Nam discloses, “Moreover, such a computing system need only transmit data required to be changed to the non-volatile memory, thereby increasing efficiency of a host interface,” Col 11, Lines 18-21.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yap (US 20190034490 A1): Technologies for Structured Database Query
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/A.N.S./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195