Response to Amendments
The amendment filed 07/30/2026 has been accepted and entered.
Status of Claims
Claims 1 and 10-21 are pending.
Claims 2-9 and 22 are cancelled.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 10-21, specifically to independent claim 1, have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1, 11, 18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0155934 A1 Yim et al (herein “Yim”) in view of High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Shibuya et al (herein “Shibuya”) and further in view of US 2017/0170095 A1 Matsubara (herein “Matsubara”).
Regarding Claim 1, Yim discloses:
A semiconductor package (see Fig. 1) comprising:
a module carrier (#110) having an upper surface;
a die (#120) formed over the upper surface of the module carrier (#110); and
a thermally enhanced molding compound (#150) formed over the upper surface of module carrier (#110) to encapsulate the die (#120), wherein:
the thermally enhanced molding compound (#150) is formed from a molding compound mixed with a thermal additive and has no air pockets or voids (see generally “ultra-fine dispersion of carbon nanotubes” in paragraph [0016], see also “uniform curing” in paragraph [0022]);
the thermal additive includes a plurality of carbon flakes or a plurality of carbon spherical particles (see Fig. 1 showing carbon black / CNT dispersion flakes (agglomerations) with sizes between 1µm - 20µm within molding compound #150); and
the thermal additive has a thermal conductivity larger than 450 W/m*K and an electrical resistivity larger than 90 µΩ.cm (see MPEP 2112.01, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” In this case, the prior art discloses carbon flakes of similar size and composition within the molding compound as the claimed subject matter, and would therefore have the same properties, specifically a thermal conductivity larger than 450 W/m*K and an electrical resistivity larger than 90 µΩ.cm.).
Yim does not explicitly disclose:
the thermally enhanced molding compound is formed from a molding compound mixed with a thermal additive that includes a plurality of graphene flakes, each of the plurality of graphene flakes having a maximum dimension between 5 µm and 50 µm;
However, in analogous art, Shibuya teaches:
the thermal additive includes graphene spherical particles (see Figs. 1, 14, abstract, Table 1 specifically including thermal conductivity row, sections I-V).
the thermal additive has a thermal conductivity larger than 450 W/m*K and an electrical resistivity larger than 90 µΩ.cm (see MPEP 2112.01, “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established.” In this case, the prior art discloses graphene spherical particles of similar size and composition within the molding compound as the claimed subject matter, and would therefore have the same properties, specifically a thermal conductivity larger than 450 W/m*K and an electrical resistivity larger than 90 µΩ.cm.).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Shibuya to the device disclosed by Yim and replace the disclosed molding compound with the included thermal additive (see generally “ultra-fine dispersion of carbon nanotubes” in paragraph [0016], see also “uniform curing” in paragraph [0022], see Fig. 1 showing carbon black / CNT dispersion flakes (agglomerations) with sizes between 1µm - 20µm within molding compound #150) for the high thermal conductivity mold compound taught by Shibuya that includes spherical graphene particles (see Fig. 1). Doing so would be an example of applying a known technique to a known device (Method, or Product) ready for improvement to yield predictable results, see MPEP 2143 (I) (D). Yim discloses a semiconductor package with a molding compound that has a generic additive (carbon agglomerations) for the purposes achieving an improved thermal conductivity for the encapsulant/molding compound. Shibuya teaches that thermal conductivity of thermally enhanced molding compounds is an area of the art which is ready for improvement, as miniaturizing of devices has led to challenges in removal of excess heat from electronic packaging, (Introduction). Additionally, Shibuya provides a known method of forming a molding compound utilizing spherical graphene particles (see Fig. 1) as an improvement over alternative thermally conductive polymer materials, for the predictable result of improving and enhancing thermal conductivity of a molding compound (see abstract). See MPEP 2143.I(D).
Additionally, in analogous art, Matsubara discloses:
See generally Figs. 1 and 2, and paragraphs [0066]-[0068]. Specifically:
[0066] In the first embodiment, particle size (average diameter) of the graphene particles GR to be mixedly added in the sealing resin MR may be adjusted to 10 to 500 μm. ... The particles may include particles formed by granulating a monolayer or multilayer film of graphene. The particles may further include particles formed by compacting pulverized material (granular material, powdery material) of graphene with resin or the like. The added amount of the graphene particles GR in the sealing resin MR (the content in the sealing resin MR) may be about 50 vol %, for example…
[0067] A larger size or a larger added-amount of the graphene particles GR leads to higher thermal conductivity.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Matsubara to the device disclosed by Yim in view of Shibuya and form the thermally enhanced molding compound using graphene flakes with a maximum dimension between 5 and 50 microns in diameter. Matsubara discloses the size of graphene flakes themselves, or the volume of graphene flakes added to the compound affects the thermal conductivity of the compound, therefore the size (diameter) of the graphene flakes is considered a result effective variable that impacts the thermal conductivity of the layer that may be optimized by the person of ordinary skill in the art for specific device needs, see MPEP 2144.05(II)(B).
Regarding Claim 11, Yim in view of Shibuya and further in view of Matsubara discloses: The semiconductor package of claim 1.
Yim further discloses:
wherein the die (#120) is a wire-bonding die (see paragraph [0010]: “The molded chip package illustrated in FIG. 1 is a wire-bonded Plastic Ball Grid Array (PBGA) package”).
Regarding Claim 18, Yim in view of Shibuya and further in view of Matsubara discloses: The semiconductor package of claim 1.
Yim in view of Shibuya and further in view of Matsubara discloses:
wherein the molding compound itself has a thermal conductivity between 0.8 W/mK - 1.0 W/mK (see Table 1, specifically thermal conductivity of control variable, i.e. the molding compound without the thermal additive has a thermal conductivity of 0.9 W/mK).
Regarding Claim 21, Yim in view of Shibuya and further in view of Matsubara discloses: The semiconductor package of claim 1.
Shibuya further teaches:
wherein a density of the thermal additive is between 1 g/cm3 and 30 g/cm3 (see Fig. 8).
Shibuya Fig. 8 discloses thermal conductivity (W/mK) as a function of additive mass fraction (wt%), i.e. density of graphene additive. Although not explicitly disclosed as having a density of between 1 g/cm3 and 30 g/cm3, the property of density of the thermal additive would be an example of a result effective variable that may be optimized by the person of ordinary skill, which in this case specifically relates the density, and the thermal conductivity, which in turn may be adjusted to meet the needs of the device.
Claims 10 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010 US 2010/0155934 A1 Yim et al in view of High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Shibuya et al and further in view of US 2017/0170095 A1 Matsubara and further in view of US 2019/0043802 A1 Kapusta et al (herein “Kapusta”).
Regarding Claim 10, Yim in view of Shibuya and further in view of Matsubara discloses: the semiconductor package of claim 1.
Yim in view of Shibuya and further in view of Matsubara does not explicitly disclose:
wherein the die is produced from Gallium Nitride (GaN) and/or Gallium Arsenide (GaAs).
However, in analogous art, Kapusta teaches:
wherein the die is produced from Gallium Nitride (GaN) and/or Gallium Arsenide (GaAs) (see paragraph [0047]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kapusta to the package including a resin encapsulant disclosed by Yim in view of Shibuya and further in view of Matsubara and form the semiconductor die from a GaN or GaAs type material. Doing so would be a simple substitution of one known material/element for another to obtain predictable results.
Regarding Claim 15, Yim in view of Shibuya and further in view of Matsubara discloses: the semiconductor package of claim 1.
Yim in view of Shibuya and further in view of Matsubara does not explicitly disclose:
wherein the die is a flip-chip die including a plurality of interconnections protruding from a lower surface of the die towards the upper surface of the module carrier.
However, in analogous art, Kapusta teaches:
wherein the die is a flip-chip die (see Fig. 2, flip chip includes die #12, die pads #32, flip chip solder bumps #42, and microvias #26) including a plurality of interconnections (#32, #42, #26) protruding from a lower surface of the die (#12) towards the upper surface of the module carrier (#14).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kapusta to the semiconductor package discloses by Yim in view of Shibuya and further in view of Matsubara and form the semiconductor structure using backside interconnects to the module carrier. Doing so would reduce semiconductor substrate damage as compared to wire bond packages, and when using solder bumps, the device can have larger current carrying cross-sections than with wire bonds.
Regarding Claim 16, Yim in view of Shibuya and further in view of Matsubara and further in view of Kapusta discloses: the semiconductor package of claim 15.
Kapusta further teaches:
further comprising an underfilling layer (#36, see annotated Fig. 2 below) that resides over the upper surface of the module carrier (#14), encapsulates sides of each of the plurality of interconnects (#32, #42, #26), and underfills the die (#12) between the lower surface of the die (#12) and the upper surface of the module carrier (#14).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kapusta to the semiconductor package discloses by Yim in view of Shibuya and further in view of Matsubara and form the semiconductor structure using backside interconnects to the module carrier. When forming the package in this manner, including an underfill layer to fully surround/encapsulate the die (with the exception of the space the interconnects occupy) would not only electrically isolate the dies, but also assist in the thermal characteristics of the package.
PNG
media_image1.png
291
1008
media_image1.png
Greyscale
Kapusta Fig. 2 Annotated by Examiner
Regarding Claim 17, Yim in view of Shibuya and further in view of Matsubara and further in view of Kapusta discloses: the semiconductor package of claim 16.
Kapusta further discloses:
wherein the underfilling layer is a portion of the (thermally enhanced) molding compound (#36).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kapusta to the package disclosed by Yim in view of Shibuya and further in view of Matsubara and include the underfill layer to fully surround/encapsulate the die (with the exception of the space the interconnects occupy) would not only electrically isolate the dies, but also assist in the thermal characteristics of the package. Additionally, it would have been obvious to include the thermal additive material throughout the entire molding compound for consistent thermal enhancement all around the die.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0155934 A1 Yim et al in view of High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Shibuya et al and further in view of US 2017/0170095 A1 Matsubara and further in view of US 5153385 A Juskey et al (herein “Juskey”).
Regarding Claim 12, Yim in view of Shibuya and further in view of Matsubara discloses: the semiconductor package of claim 11.
Yim in view of Shibuya and further in view of Matsubara does not explicitly disclose:
the semiconductor package further includes a polymer layer directly and fully covering the die, wherein the thermally enhanced molding compound is in contact with the polymer layer.
However, in analogous art, Juskey teaches:
the semiconductor package further includes a polymer layer (Fig. 2, #18) directly and fully covering the die (#12), wherein the molding compound (#20) is in contact with the polymer layer (#18).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Juskey to the semiconductor package disclosed by Yim in view of Shibuya and further in view of Matsubara and include the polymer layer that fully covers the die. Doing so would improve the moisture resistance of the package and reduce the stress at the surface of the die when applying the resin molding compound.
Regarding Claim 13, Yim in view of Shibuya and further in view of Matsubara and further in view of Juskey discloses: the semiconductor package of claim 12.
Juskey further discloses
wherein the polymer layer has a thickness up to 10 µm (see paragraph (2), “The finished thickness of the coating may vary from 0.1 mil to approximately 2 mils depending upon the material selected and the coating thickness desired.”) and is configured to protect the die and release stress of the die (see abstract, “The polymer coating (18) also provides a barrier to alpha particle emission, improves the moisture resistance of the completed package and reduces stress at the surface of the device.”).
Regarding Claim 14, Yim in view of Shibuya and further in view of Matsubara and further in view of Juskey discloses: the semiconductor package of claim 12.
Juskey further discloses
The semiconductor package of claim 12 wherein the polymer layer is formed of one of a group consisting of poly benzo butene (BCB), poly benzo oxazol (PBO), and polyimide (PI) (see paragraph (2): “After electrical interconnections have been made, the assembly is then coated with a polymer resin 18 such as a polyimide resin”).
Note, the phrase “formed of one of a group consisting of” is interpreted as formed by one of the choices listed. In other words, formed by A, B, or C. In this case, Juskey discloses the polymer cover material is formed of a polyimide material and therefore teaches the claim.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0155934 A1 Yim et al in view of High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Shibuya et al and further in view of US 2017/0170095 A1 Matsubara and further in view of US 2014/0131757 A1 Lin et al (herein “Lin”).
Regarding Claim 19, Yim in view of Shibuya and further in view of Matsubara discloses: The semiconductor package of claim 1
Yim in view of Shibuya and further in view of Matsubara does not explicitly disclose:
wherein the molding compound is an organic epoxy resin.
However, in analogous art, Lin teaches:
wherein the molding compound (#15) is an organic epoxy resin (paragraph [0032] discloses “The heat conducting composite material includes a matrix and a plurality of graphene sheets.” And paragraph [0036] discloses “In the embodiment, the matrix is an organic material of epoxy”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Lin to the package disclosed by Yim in view of Shibuya and further in view of Matsubara and include an organic resin material in place of the resin material which would be a simple substitution of one known element for another to achieve a predictable result.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over US 2010/0155934 A1 Yim et al in view of High Thermal Conductivity Mold Compounds for Advanced Packaging Applications Shibuya et al and further in view of US 2017/0170095 A1 Matsubara and further in view of US 2017/0358511 A1 Costa et al (herein “Costa”).
Regarding Claim 20, Yim in view of Shibuya and further in view of Matsubara discloses the semiconductor package of claim 1.
Yim in view of Shibuya and further in view of Matsubara does not explicitly disclose:
wherein within the thermally enhanced molding compound, a density of the thermal additive dispersed throughout the molding compound varies, such that the density increases closer to an upper surface of the die.
However, in analogous art, Costa teaches:
wherein within the thermally enhanced molding compound, a density of the thermal additive dispersed throughout the molding compound varies, such that the density increases closer to an upper surface of the die.
See paragraphs [0028] and [0036]. Costa discloses a thermal additive 32 has a varied density that “decreases gradually from a bottom to a top of the lower portion of the thermally enhanced mold compound component 20”. In this case, this varying of the thermal additive is substantially identical to the claimed limitation, as the top of the thermal compound is further away from the die, thus the density increases closer to the die.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Costa to the package disclosed by Yim in view of Shibuya and further in view of Matsubara and include a varying density of thermal additives to the molding compound that increases closer to an upper surface of the die. Doing so would allow the fine tuning or customization of the thermal properties depending on the region that the additives occupy.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571)272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
