DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 13 April 2023 was filed prior to the mailing date of this office correspondence. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Invention II, claims 6-14 in the reply filed on 02 March 2026 is acknowledged.
Claims 1-5 and 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Inventions I and II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02 March 2026.
Claim Objections
Claim 7 is objected to because of the following informalities:
In claim 7, line 4, “manufacturing the second integrated circuit die according to a lower-resolution process.” should read:
-- manufacturing the second integrated circuit die according to a lower-resolution process compared to the first integrated circuit die. --
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 6 and 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Trimberger (US 8179159).
Regarding claim 6, Trimberger teaches, a method for manufacturing an integrated circuit device (see Figs. 1 to 8A), the method comprising:
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Annotated Fig. 3, Trimberger.
obtaining a first integrated circuit die (FPGA die 202, Figs. 2 and 3) comprising field programmable gate array fabric (programmable routing fabric 314 of the FPGA die 202, see Fig. 2 and annotated Fig. 3 above, PHI tile 150 includes one or more programmable interconnect elements 111, a configurable logic element 112, interface circuits 304, selection logic 308, and a plurality of TDVs 310. The PHI tile 300 includes an interface 312 to programmable routing fabric 314 of the FPGA, col. 6, lines 27-32);
obtaining a second integrated circuit die (second IC die 204, Fig. 2) comprising fabric support circuitry configured to operate the field programmable gate array fabric of the first integrated circuit die (the selection logic 308 cause the PHI tile 150 to operate as an interface tile between the FPGA routing fabric 314 and the second IC die 318, col. 6, lines 60-35);
vertically aligning the first integrated circuit die and the second integrated circuit die (second IC die 204 is vertically stacked with the FPGA die 202, see Fig. 2 and Fig. 6, col. 5, line 38); and
connecting a first surface of the first integrated circuit die to a second surface of the second integrated circuit die (see Fig. 2 and Fig. 6, FPGA die 202 may include a plurality of TDVs for coupling electrical signals between circuits on the FPGA die 202 and circuits on the second IC die 204. A PHI tile 150 includes TDVs for providing an interface between FPGA logic and one or more stacked ICs, col. 6, lines 20-24).
Regarding claim 9, Trimberger teaches the recited limitations with respect to claim 6. Trimberger further teaches, the method of claim 6, wherein vertically aligning the first integrated circuit die and the second integrated circuit die comprises vertically aligning first sectors of the field programmable gate array fabric with second sectors of the fabric support circuitry (see Figs. 2 and 6, integrated circuits inherently have sectors that divides critical components and hence vertical stacking enables aligning the first sectors of the field programmable gate array fabric with second sectors of the fabric support circuitry).
Regarding claim 10, Trimberger teaches the recited limitations with respect to claim 6. Trimberger further teaches, the method of claim 6, wherein connecting the first surface and the second surface comprises forming an electrical connection between a connector of the first integrated circuit die and a corresponding connector of the second integrated circuit die (second IC die 204 also includes conductive interconnect formed over the circuitry, col. 5, lines 50-52, see annotated Fig. 2 below).
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Annotated Fig. 2, Trimberger.
Regarding claim 11, Trimberger teaches the recited limitations with respect to claim 10. Trimberger further teaches, the method of claim 10, wherein the electrical connection comprises a microbump (an array of bump contacts 218 formed on the face side for flip-chip mounting to a carrier, col. 5, line 58).
Regarding claim 12, Trimberger teaches the recited limitations with respect to claim 6. Trimberger further teaches, the method of claim 6, wherein the integrated circuit device comprises a field programmable gate array (FPGA) comprising the first integrated circuit die (FPGA die 202) and the second integrated circuit die (second IC die 204).
Regarding claim 13, Trimberger teaches the recited limitations with respect to claim 6. Trimberger further teaches, the method of claim 6, comprising electrically coupling a processor (FPGA typically includes configurable logic blocks CLBs,…microprocessors, digital signal processors DSPs, col. 1, lines 22-24) to the second integrated circuit die, the processor configured to manage a data processing request for the first integrated circuit die and the second integrated circuit die (col. 10, lines 50-55).
Regarding claim 14, Trimberger teaches the recited limitations with respect to claim 6. Trimberger further teaches, the method of claim 6, wherein the second integrated circuit die comprises sector-aligned memory (FPGA typically includes configurable logic blocks CLBs, programmable input/output blocks IOBs, …internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured, col. 1, lines 22-30) corresponding to one or more fabric sectors of the field programmable gate array fabric, wherein the sector-aligned memory is configured to store configuration data for programming the one or more fabric sectors (see Figs. 2 and 6, integrated circuits inherently have sectors that divides critical components and hence vertical stacking enables aligning the first sectors of the field programmable gate array fabric with second sectors of the fabric support circuitry).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Trimberger as applied to claim 6 above, and further in view of Leedy (US 20170330876).
Regarding claim 7, Trimberger does not teach, a high-resolution or a low-resolution process. However, Leedy teaches a method of manufacturing an integrated circuit device, including field programmable gate array, in which, the method of claim 6, wherein obtaining the first integrated circuit die comprises manufacturing the first integrated circuit die according to a higher-resolution process (high density high performance…FPGA, para. [0723]), and wherein obtaining the second integrated circuit die comprises manufacturing the second integrated circuit die according to a lower-resolution process (VSI FPGA invention are variable programmable gate density per VSI, para. [0747]). Therefore, in view of the teachings of Leedy, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the integrated circuit of Trimberger and to include a high density process and a low density process for the manufacturing of the first integrated circuit die and the second integrated circuit die so that it enables in-circuit programming changes of the programmable gates or routing interconnections as Leedy disclosed in para. [0747]. Moreover, there is no indication in the instant invention that any surprising results were derived, or that any special steps were devised in manufacturing the higher-resolution process or the lower-resolution process. Such a combination would have been done by one of ordinary skill in the art without any need for experimentation and with reasonable expectations of success.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Trimberger as applied to claim 6 above, and further in view of Trimberger (US 10147666, hereafter Trimberger ‘666).
Regarding claim 8, Trimberger does not teach a microchannel integrated heat spreader. However, Trimberger ‘666 teaches a method of manufacturing an integrated circuit device including a first integrated circuit die 116 comprising field programmable gate arrays memory device, a second integrated circuit die 114 in which, the method of claim 6, comprising disposing the first integrated circuit die and the second integrated circuit die in a microchannel integrated heat spreader (heat spreader 622, a plurality of IC dies 114, 116 interfaced with at least one heat spreader 602, col. 6, lines 28-30). Therefore, in view of the teachings of Trimberger ‘666, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method of manufacturing the integrated circuit of Trimberger and to include a heat spreader 602 as Trimberger ’666 taught in Fig. 6 so that it enables forming a segmented heat spreader that draws heat from the integrated circuit.
Conclusion
Prior art Wu (US 20180083635) teaches a method for manufacturing an integrated circuit device, the method comprising: obtaining a first integrated circuit die comprising field programmable gate array; obtaining a second integrated circuit die comprising fabric support circuitry; vertically aligning the first integrated circuit die and the second integrated circuit die; and connecting a first surface of the first integrated circuit die to a second surface of the second integrated circuit die.
Prior art New (US 20040178819) teaches a method for manufacturing an integrated circuit device, including obtaining a first integrated circuit die comprising field programmable gate array; obtaining a second integrated circuit die comprising fabric support circuitry; vertically aligning the first integrated circuit die and the second integrated circuit die; and connecting a first surface of the first integrated circuit die to a second surface of the second integrated circuit die.
Prior art Kwon (US 9147661) teaches a method for manufacturing an integrated circuit device, including a first integrated circuit die comprising field programmable gate array; a second integrated circuit die comprising fabric support circuitry; vertically aligning the first integrated circuit die and the second integrated circuit die; and connecting a first surface of the first integrated circuit die to a second surface of the second integrated circuit die.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE K. ABRAHAM whose telephone number is (571)270-1087. The examiner can normally be reached Monday-Friday 8:30-4:30 EST.
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/JOSE K ABRAHAM/Examiner, Art Unit 3729