DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/7/2017 has been entered.
Claims 1-12 are pending and they are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 (similarly claim 6) recite: “the control apparatus comprises only one register to receive information from the host machine or the virtual machine for triggering a virtual interrupt”.
After careful search of the instant application, the examiner was unable to find any disclosure which states “the control apparatus comprises only one register to receive information from the host machine or the virtual machine for triggering a virtual interrupt”.
Closest disclosure from the instant application states:
[PGPub paragraph 11] (similarly 125), “In this application, the control apparatus may include at least one register, where each register may be configured to receive one type of information used to trigger a virtual interrupt. For example, three registers are included, where one register is configured to receive information used to trigger a virtual local interrupt, one register is configured to receive information used to trigger a virtual software interrupt, and one register is configured to receive information used to trigger a virtual device interrupt. Certainly, in the control apparatus, only one register may be configured for the virtual interrupt, and information used to trigger each type of virtual interrupt is different. The type of the virtual interrupt may be identified by using information received by the register.”
Nothing in the speciation disclose the only one register is to “receive information from the host machine” (emphasis added). The three types of registers included in the control apparatus are for triggering a virtual local interrupt, information used to trigger a virtual software interrupt and information used to trigger a virtual device interrupt. The only one register is not used to receive information (any particular information) from the host machine.
Claims 2-5 and 7-12 are rejected based on rejection of its corresponding dependent claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 (similarly claim 6) recite: “the control apparatus comprises only one register to receive information from the host machine or the virtual machine for triggering a virtual interrupt”.
The examiner is unclear how the one register can receive two types of information. Per specification, only one register can receive only one type of interrupt/information. Information from the host machine or the virtual machine should have its own corresponding register. Furthermore, the types of registers disclosed in the specification only holds interrupt information not any information for a host device.
Claims 2-5 and 7-12 are rejected based on rejection of its corresponding dependent claim.
Response to Arguments
Applicant's arguments filed regarding claim 1 (page 8), “Song lacks the “only one register” limitation now recited in independent claim 1”.
The examiner would like to point out to the instant application which discloses three registers within the control apparatus:
[PGPub paragraph 125], “In this application, the control apparatus may include at least one register, where each register may be configured to receive one type of information used to trigger a virtual interrupt. For example, three registers are included, where one register is configured to receive information used to trigger a virtual local interrupt, one register is configured to receive information used to trigger a virtual software interrupt, and one register is configured to receive information used to trigger a virtual device interrupt.”
The instant application discloses plurality of registers within the control apparatus which receive a type of information used to trigger a virtual interrupt.
Similarly, Song discloses two types of register APIC_ICR (main register) which interrupt vector information is received for realizing addressing of interrupt service and determining specific content of interrupt. APIC_ICR2 (secondary register) for determining the target virtual processor. The hypervisor converts the information of the target VCPU in APIC_ICR2 into the information (transforms VCPU to CPU) of the corresponding physical processor CPU and sends an interrupt to the physical processor where the target VCPU is located.
[Page 2], Fig. 1 shows a scheme for sending an Interrupt between Virtual machine processors in the current x86 architecture, if one of the Virtual processors VCPU _ # M needs to send an Interrupt to another Virtual processor VCPU _ # N in one Virtual machine, first, interrupt vector information and information of a target VCPU (i.e., VCPU _ # N) are written into an Interrupt command register APIC _ ICR (Interrupt command main register) and APIC _ ICR2 (Interrupt command sub register) of a Virtual Local Advanced Programmable Interrupt Controller (Virtual Local Advanced Programmable Interrupt Controller), respectively. At this time, the CPU _ # X corresponding to VCPU _ # M knows the write operation to the VLAPIC, enters Hypervisor, and enters the root mode, the Hypervisor converts the information of the target VCPU in APIC _ ICR2 into the information (transform VCPU to CPU) of the corresponding physical processor CPU _ # Y, sends an interrupt to the physical processor CPU _ # Y where the target VCPU _# N is located, and sends the relevant information of the interrupt to the target CPU _ # Y through the bus. Thus, the transmission of the interrupt is completed so that the CPU _ # Y responds to the IPI interrupt according to the interrupt vector information.
[Page 6], The interrupt command register comprises an APIC_ICR (interrupt command main register) and an APIC_ICR2 (interrupt command secondary register), wherein interrupt vector information is written into the APIC_ICR for realizing addressing of interrupt service and determining the specific content of interrupt, and information of a target virtual processor is written into the APIC _ ICR2 for determining the target of interrupt sending.)
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (Song, Wen-jun; CN 110609730 B) (hereafter Song)
As per claim 1, Song teaches:
A chip system, comprising:
a source physical processor, a control apparatus, an intermediate apparatus, a sending apparatus, and a target physical processor, wherein:
the source physical processor is configured for a host machine or a virtual machine;
the control apparatus comprises only one register configured to receive information from the host machine or the virtual machine for triggering a virtual interrupt, wherein the control apparatus is configured to send the received information to the intermediate apparatus;
the intermediate apparatus is configured to send the virtual interrupt to the sending apparatus; and
the sending apparatus is configured to receive the virtual interrupt from the intermediate apparatus and send the virtual interrupt to the target physical processor. ([Page 3-4], To achieve the above object, the present application provides a method for implementing transparent interrupt transmission between virtual processors, the method comprising: when a source virtual processor needs to send an interrupt to a target virtual processor, a source physical processor corresponding to the source virtual processor writes interrupt vector information and information of the target virtual processor into an interrupt command register, wherein a mapping relation exists between the virtual processor and the physical processor; the interrupt controller of the source physical processor determines the information of a target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor; and the interrupt controller of the source physical processor sends the interrupt vector information to the interrupt controller of the target physical processor according to the information of the target physical processor, so that the interrupt controller of the target physical processor responds to the interrupt according to the interrupt vector information. Based on another aspect of the present application, there is also provided an apparatus for implementing transparent interrupt transmission between virtual processors, the apparatus including: the interrupt writing device is used for controlling a source physical processor corresponding to a source virtual processor to write interrupt vector information and information of a target virtual processor into an interrupt command register when the source virtual processor needs to send an interrupt to the target virtual processor, wherein a mapping relation exists between the virtual processor and the physical processor; the interrupt routing device is used for controlling an interrupt controller of the source physical processor to determine the information of a target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor; and the interrupt sending device is used for controlling the interrupt controller of the source physical processor to send the interrupt vector information to the interrupt controller of the target physical processor according to the information of the target physical processor so that the interrupt controller of the target physical processor responds to the interrupt according to the interrupt vector information. In addition, the present application also provides an apparatus for implementing virtual inter-processor interrupt pass-through, including a memory for storing computer program instructions and a plurality of physical processors for executing the computer program instructions, where the physical processors correspond to the plurality of virtual processors when operating in a non-root mode, and when the computer program instructions are executed by the physical processors, the apparatus is triggered to execute the foregoing method for implementing virtual inter-processor interrupt pass-through. [Page 6], Fig. 4 is a schematic structural diagram illustrating an apparatus for implementing virtual inter-processor interrupt pass-through according to an embodiment of the present application, where the apparatus includes a mapping maintenance device 410, an interrupt writing device 420, an interrupt routing device 430, and an interrupt sending device 440. The mapping maintenance device 410 is used for storing the mapping relationship between the virtual processor and the physical processor. In an actual virtualization scenario, hypervisor is responsible for creating and managing virtual machines, and Hypervisor is an intermediate software layer running between a physical server and an operating system, and can allow multiple operating systems and applications to share one set of basic physical hardware and coordinate to access all physical devices and virtual machines on the server. Thus, the mapping maintenance device 410 may also control the Hypervisor to maintain the mapping relationship between the virtual processors and the physical processors, that is, at the time of creating the virtual machine, the Hypervisor creates the mapping relationship between the virtual processors and the physical processors of the virtual machine, and updates the mapping relationship at the time of scheduling the virtual processors. In an embodiment of the application, a Mapping relationship between a virtual processor and a physical processor may be recorded through a Mapping Table, which is denoted as VMT (VCPU Mapping Table), and when the Hypervisor performs a scheduling action of the virtual processor, a Mapping relationship between the virtual processor and the physical processor may be changed, so that the Mapping relationship needs to be updated when the Hypervisor schedules the virtual processor, so as to ensure that the Mapping relationship in the Mapping Table is correct. The following mapping relationship can be known from the mapping table in this embodiment: the virtual processor VCPU _ # M corresponds to the physical processor CPU _ # X, and the virtual processor VCPU _ # N corresponds to the physical processor CPU _ # Y…
The interrupt command register comprises an APIC_ICR (interrupt command main register) and an APIC_ICR2 (interrupt command secondary register), wherein interrupt vector information is written into the APIC_ICR for realizing addressing of interrupt service and determining the specific content of interrupt, and information of a target virtual processor is written into the APIC _ ICR2 for determining the target of interrupt sending.)
As per claim 2, rejection of claim 1 is incorporated:
Song teaches wherein the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are a same physical processor;
the register is configured to receive information written by the virtual machine for triggering the virtual local interrupt; and
the sending apparatus is configured to send the virtual local interrupt to a first virtual processor of the virtual machine, wherein the first virtual processor runs on the source physical processor. ([Page 5], In an embodiment of the present application, a Mapping Table register may be added in the LAPIC, and the register may be referred to as an APIC _ VMT (APIC VCPU Mapping Table) register, and is used to store a base address of a Mapping Table for recording a Mapping relationship between a virtual processor and a physical processor. Therefore, when the interrupt controller of the source physical processor determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor, the interrupt controller of the source physical processor can firstly read the information from the mapping table register, access the mapping table according to the base address of the mapping table stored in the mapping table register, and then determine the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor in the mapping table. [Page 3], In addition, the present application also provides an apparatus for implementing virtual inter-processor interrupt pass-through, including a memory for storing computer program instructions and a plurality of physical processors for executing the computer program instructions, where the physical processors correspond to the plurality of virtual processors when operating in a non-root mode, and when the computer program instructions are executed by the physical processors, the apparatus is triggered to execute the foregoing method for implementing virtual inter-processor interrupt pass-through. )
As per claim 3, rejection of claim 1 is incorporated:
Song teaches wherein the virtual interrupt is a virtual software interrupt, the information for triggering the virtual interrupt comprises an identifier of a second virtual processor written by a first virtual processor of the virtual machine into the register, and the second virtual processor is a virtual processor of the virtual machine and runs on the target physical processor;
the control apparatus is configured to:
read the identifier of the second virtual processor from the register;
obtain an identifier of the virtual machine; and
send the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate apparatus;
the intermediate apparatus is configured to:
determine, from a first correspondence based on the identifier of the virtual machine and the identifier of the second virtual processor, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor, wherein the first correspondence is a correspondence between the target physical processor, the second virtual processor, and the virtual machine; and
send the virtual software interrupt to the sending apparatus corresponding to the target physical processor; and
the sending apparatus is configured to send the virtual software interrupt to the second virtual processor.
([Page 3-4], Fig. 1 shows a scheme for sending an Interrupt between Virtual machine processors in the current x86 architecture, if one of the Virtual processors VCPU _ # M needs to send an Interrupt to another Virtual processor VCPU _ # N in one Virtual machine, first, interrupt vector information and information of a target VCPU (i.e., VCPU _ # N) are written into an Interrupt command register APIC _ ICR (Interrupt command main register) and APIC _ ICR2 (Interrupt command sub register) of a Virtual Local Advanced Programmable Interrupt Controller (Virtual Local Advanced Programmable Interrupt Controller), respectively. At this time, the CPU _ # X corresponding to VCPU _ # M knows the write operation to the VLAPIC, enters Hypervisor, and enters the root mode, the Hypervisor converts the information of the target VCPU in APIC _ ICR2 into the information (transform VCPU to CPU) of the corresponding physical processor CPU _ # Y, sends an interrupt to the physical processor CPU _ # Y where the target VCPU _# N is located, and sends the relevant information of the interrupt to the target CPU _ # Y through the bus. Thus, the transmission of the interrupt is completed so that the CPU _ # Y responds to the IPI interrupt according to the interrupt vector information. To achieve the above object, the present application provides a method for implementing transparent interrupt transmission between virtual processors, the method comprising: when a source virtual processor needs to send an interrupt to a target virtual processor, a source physical processor corresponding to the source virtual processor writes interrupt vector information and information of the target virtual processor into an interrupt command register, wherein a mapping relation exists between the virtual processor and the physical processor; the interrupt controller of the source physical processor determines the information of a target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor; and the interrupt controller of the source physical processor sends the interrupt vector information to the interrupt controller of the target physical processor according to the information of the target physical processor, so that the interrupt controller of the target physical processor responds to the interrupt according to the interrupt vector information. Based on another aspect of the present application, there is also provided an apparatus for implementing transparent interrupt transmission between virtual processors, the apparatus including: the interrupt writing device is used for controlling a source physical processor corresponding to a source virtual processor to write interrupt vector information and information of a target virtual processor into an interrupt command register when the source virtual processor needs to send an interrupt to the target virtual processor, wherein a mapping relation exists between the virtual processor and the physical processor; the interrupt routing device is used for controlling an interrupt controller of the source physical processor to determine the information of a target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor; and the interrupt sending device is used for controlling the interrupt controller of the source physical processor to send the interrupt vector information to the interrupt controller of the target physical processor according to the information of the target physical processor so that the interrupt controller of the target physical processor responds to the interrupt according to the interrupt vector information. In addition, the present application also provides an apparatus for implementing virtual inter-processor interrupt pass-through, including a memory for storing computer program instructions and a plurality of physical processors for executing the computer program instructions, where the physical processors correspond to the plurality of virtual processors when operating in a non-root mode, and when the computer program instructions are executed by the physical processors, the apparatus is triggered to execute the foregoing method for implementing virtual inter-processor interrupt pass-through. [Page 6], Fig. 4 is a schematic structural diagram illustrating an apparatus for implementing virtual inter-processor interrupt pass-through according to an embodiment of the present application, where the apparatus includes a mapping maintenance device 410, an interrupt writing device 420, an interrupt routing device 430, and an interrupt sending device 440. The mapping maintenance device 410 is used for storing the mapping relationship between the virtual processor and the physical processor. In an actual virtualization scenario, hypervisor is responsible for creating and managing virtual machines, and Hypervisor is an intermediate software layer running between a physical server and an operating system, and can allow multiple operating systems and applications to share one set of basic physical hardware and coordinate to access all physical devices and virtual machines on the server. Thus, the mapping maintenance device 410 may also control the Hypervisor to maintain the mapping relationship between the virtual processors and the physical processors, that is, at the time of creating the virtual machine, the Hypervisor creates the mapping relationship between the virtual processors and the physical processors of the virtual machine, and updates the mapping relationship at the time of scheduling the virtual processors. In an embodiment of the application, a Mapping relationship between a virtual processor and a physical processor may be recorded through a Mapping Table, which is denoted as VMT (VCPU Mapping Table), and when the Hypervisor performs a scheduling action of the virtual processor, a Mapping relationship between the virtual processor and the physical processor may be changed, so that the Mapping relationship needs to be updated when the Hypervisor schedules the virtual processor, so as to ensure that the Mapping relationship in the Mapping Table is correct. The following mapping relationship can be known from the mapping table in this embodiment: the virtual processor VCPU _ # M corresponds to the physical processor CPU _ # X, and the virtual processor VCPU _ # N corresponds to the physical processor CPU _ # Y.)
As per claim 4, rejection of claim 1 is incorporated:
Song teaches wherein the virtual interrupt is a virtual device interrupt, the information used to trigger the virtual interrupt comprises a target interrupt number written by the host machine into the register and an identifier of the virtual machine, and the target interrupt number is an identifier of an interrupt triggered when the host machine simulates a hardware device;
the control apparatus is configured to:
read the target interrupt number and the identifier of the virtual machine from the register; and
send the identifier of the virtual machine and the target interrupt number to the intermediate apparatus; ([Page 5], In an embodiment of the present application, a Mapping Table register may be added in the LAPIC, and the register may be referred to as an APIC _ VMT (APIC VCPU Mapping Table) register, and is used to store a base address of a Mapping Table for recording a Mapping relationship between a virtual processor and a physical processor. Therefore, when the interrupt controller of the source physical processor determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor, the interrupt controller of the source physical processor can firstly read the information from the mapping table register, access the mapping table according to the base address of the mapping table stored in the mapping table register, and then determine the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor in the mapping table. After determining the information of the target physical processor CPU _ # Y, the LAPIC of the source physical processor CPU _ # X sends the interrupt vector information to the interrupt controller LAPIC of the target physical processor CPU _ # Y according to the information of the target physical processor, so that the LAPIC of the target physical processor CPU _ # Y responds to the interrupt according to the interrupt vector information, thereby completing the transparent transmission of the interrupt between the virtual processors. In the process of realizing the interrupt transparent transmission among the virtual processors, the Hypervisor does not intervene in the process of interrupt sending, and only manages the mapping relation during the virtual machine creation and the virtual processor scheduling, so that the intervention processing of the Hypervisor during the processing of the interrupt among the virtual processors is avoided, the delay of interrupt processing is reduced, and the processing efficiency is improved.)
the intermediate apparatus is configured to:
search, based on the identifier of the virtual machine and the target interrupt number, the second correspondence for an identifier of a first virtual processor of the virtual machine corresponding to the identifier of the virtual machine and the target interrupt number; ([Page 5],
And the interrupt controller of the source physical processor CPU _ # X determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor. The Interrupt Controller is a Local Advanced Programmable Interrupt Controller (LAPIC) of the physical processor, and the LAPIC can query in a mapping relationship according to information written in the target virtual processor in the APIC _ ICR2, so as to obtain a target physical processor CPU _ # Y corresponding to the target virtual processor VCPU _ # N.)
determine, from a third correspondence based on the identifier of the virtual machine and the identifier of the first virtual processor, the target physical processor corresponding to the identifier of the virtual machine and the identifier of the first virtual processor, wherein the third correspondence is a correspondence between the target physical processor, the first virtual processor, and the virtual machine; and
send the virtual device interrupt to the sending apparatus corresponding to the target physical processor; and
the sending apparatus is configured to send the virtual device interrupt to the first virtual processor running on the target physical processor. ([Page 5], In an embodiment of the present application, a Mapping Table register may be added in the LAPIC, and the register may be referred to as an APIC _ VMT (APIC VCPU Mapping Table) register, and is used to store a base address of a Mapping Table for recording a Mapping relationship between a virtual processor and a physical processor. Therefore, when the interrupt controller of the source physical processor determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor, the interrupt controller of the source physical processor can firstly read the information from the mapping table register, access the mapping table according to the base address of the mapping table stored in the mapping table register, and then determine the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor in the mapping table. After determining the information of the target physical processor CPU _ # Y, the LAPIC of the source physical processor CPU _ # X sends the interrupt vector information to the interrupt controller LAPIC of the target physical processor CPU _ # Y according to the information of the target physical processor, so that the LAPIC of the target physical processor CPU _ # Y responds to the interrupt according to the interrupt vector information, thereby completing the transparent transmission of the interrupt between the virtual processors. In the process of realizing the interrupt transparent transmission among the virtual processors, the Hypervisor does not intervene in the process of interrupt sending, and only manages the mapping relation during the virtual machine creation and the virtual processor scheduling, so that the intervention processing of the Hypervisor during the processing of the interrupt among the virtual processors is avoided, the delay of interrupt processing is reduced, and the processing efficiency is improved.)
As per claim 5, rejection 4 is incorporated:
Song teaches wherein the intermediate apparatus is further configured to:
find an address register based on the identifier of the virtual machine; and
obtain the second correspondence from a memory based on a address in the address register.
([Page 5], And the interrupt controller of the source physical processor CPU _ # X determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relation between the virtual processor and the physical processor. The Interrupt Controller is a Local Advanced Programmable Interrupt Controller (LAPIC) of the physical processor, and the LAPIC can query in a mapping relationship according to information written in the target virtual processor in the APIC _ ICR2, so as to obtain a target physical processor CPU _ # Y corresponding to the target virtual processor VCPU _ # N. [Page 6], In step S303, the LAPIC of the CPU _ # X attempts to access the mapping table VMT according to the base address of the mapping table VMT stored in the mapping table register APIC _ VMT… A scene corresponding to the Interrupt transparent transmission between the virtual processors is that a certain virtual Processor of the virtual machine needs to send an IPI (Inter-Processor Interrupt) to other virtual processors, where the sent virtual Processor is marked as a source virtual Processor, the received virtual Processor is a target virtual Processor, the number of the target virtual processors may be one or multiple, a physical Processor corresponding to the source virtual Processor is a source physical Processor, and a physical Processor corresponding to the target virtual Processor is a target physical Processor. )
As per claim 11, rejection of claim 1 is incorporated:
Song teaches wherein the intermediate apparatus is configured to:
trigger the virtual interrupt based on the information used to trigger the virtual interrupt. ([Page 3], Hypervisor converts the information of the target VCPU in APIC _ ICR2 into the information (transform VCPU to CPU) of the corresponding physical processor CPU _ # Y, sends an interrupt to the physical processor CPU _ # Y where the target VCPU _# N is located, and sends the relevant information of the interrupt to the target CPU _ # Y through the bus. Thus, the transmission of the interrupt is completed so that the CPU _ # Y responds to the IPI interrupt according to the interrupt vector information. [Page 6], Fig. 4 is a schematic structural diagram illustrating an apparatus for implementing virtual inter-processor interrupt pass-through according to an embodiment of the present application, where the apparatus includes a mapping maintenance device 410, an interrupt writing device 420, an interrupt routing device 430, and an interrupt sending device 440. The mapping maintenance device 410 is used for storing the mapping relationship between the virtual processor and the physical processor. In an actual virtualization scenario, hypervisor is responsible for creating and managing virtual machines, and Hypervisor is an intermediate software layer running between a physical server and an operating system, and can allow multiple operating systems and applications to share one set of basic physical hardware and coordinate to access all physical devices and virtual machines on the server. Thus, the mapping maintenance device 410 may also control the Hypervisor to maintain the mapping relationship between the virtual processors and the physical processors, that is, at the time of creating the virtual machine, the Hypervisor creates the mapping relationship between the virtual processors and the physical processors of the virtual machine, and updates the mapping relationship at the time of scheduling the virtual processors. In an embodiment of the application, a Mapping relationship between a virtual processor and a physical processor may be recorded through a Mapping Table, which is denoted as VMT (VCPU Mapping Table), and when the Hypervisor performs a scheduling action of the virtual processor, a Mapping relationship between the virtual processor and the physical processor may be changed, so that the Mapping relationship needs to be updated when the Hypervisor schedules the virtual processor, so as to ensure that the Mapping relationship in the Mapping Table is correct. The following mapping relationship can be known from the mapping table in this embodiment: the virtual processor VCPU _ # M corresponds to the physical processor CPU _ # X, and the virtual processor VCPU _ # N corresponds to the physical processor CPU _ # Y.)
As per claim 12, rejection of claim 1 is incorporated:
Song teaches wherein the intermediate apparatus comprises an address register configured to store an address of a second correspondence in a memory and an identifier of a virtual machine, wherein the second correspondence is used to record a correspondence between the virtual machine, a target interrupt number, a target interrupt number, and a first virtual processor. ([Page 3], Hypervisor converts the information of the target VCPU in APIC _ ICR2 into the information (transform VCPU to CPU) of the corresponding physical processor CPU _ # Y, sends an interrupt to the physical processor CPU _ # Y where the target VCPU _# N is located, and sends the relevant information of the interrupt to the target CPU _ # Y through the bus. Thus, the transmission of the interrupt is completed so that the CPU _ # Y responds to the IPI interrupt according to the interrupt vector information. [Page 4], Thus, the mapping relationship between the virtual processor and the physical processor can be maintained by the Hypervisor, that is, at the time of creating the virtual machine, the Hypervisor creates the mapping relationship between the virtual processor and the physical processor of the virtual machine, and updates the mapping relationship at the time of scheduling the virtual processor. In an embodiment of the present application, a Mapping relationship between a virtual processor and a physical processor may be recorded through a Mapping Table, which is denoted as VMT (VCPU Mapping Table), and when the Hypervisor performs a scheduling action of the virtual processor, the Mapping relationship between the virtual processor and the physical processor may be changed, so that the Mapping relationship needs to be updated when the Hypervisor schedules the virtual processor, so as to ensure that the Mapping relationship in the Mapping Table is correct in real time. The following mapping relationship can be known from the mapping table in this embodiment: the virtual processor VCPU _ # M corresponds to the physical processor CPU _ # X, and the virtual processor VCPU _ # N corresponds to the physical processor CPU _ # Y. [Page 5], In an embodiment of the present application, a Mapping Table register may be added in the LAPIC, and the register may be referred to as an APIC _ VMT (APIC VCPU Mapping Table) register, and is used to store a base address of a Mapping Table for recording a Mapping relationship between a virtual processor and a physical processor. Therefore, when the interrupt controller of the source physical processor determines the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor, the interrupt controller of the source physical processor can firstly read the information from the mapping table register, access the mapping table according to the base address of the mapping table stored in the mapping table register, and then determine the information of the target physical processor corresponding to the information of the target virtual processor according to the mapping relationship between the virtual processor and the physical processor in the mapping table. [Page 6], Fig. 4 is a schematic structural diagram illustrating an apparatus for implementing virtual inter-processor interrupt pass-through according to an embodiment of the present application, where the apparatus includes a mapping maintenance device 410, an interrupt writing device 420, an interrupt routing device 430, and an interrupt sending device 440. The mapping maintenance device 410 is used for storing the mapping relationship between the virtual processor and the physical processor. In an actual virtualization scenario, hypervisor is responsible for creating and managing virtual machines, and Hypervisor is an intermediate software layer running between a physical server and an operating system, and can allow multiple operating systems and applications to share one set of basic physical hardware and coordinate to access all physical devices and virtual machines on the server. Thus, the mapping maintenance device 410 may also control the Hypervisor to maintain the mapping relationship between the virtual processors and the physical processors, that is, at the time of creating the virtual machine, the Hypervisor creates the mapping relationship between the virtual processors and the physical processors of the virtual machine, and updates the mapping relationship at the time of scheduling the virtual processors. In an embodiment of the application, a Mapping relationship between a virtual processor and a physical processor may be recorded through a Mapping Table, which is denoted as VMT (VCPU Mapping Table), and when the Hypervisor performs a scheduling action of the virtual processor, a Mapping relationship between the virtual processor and the physical processor may be changed, so that the Mapping relationship needs to be updated when the Hypervisor schedules the virtual processor, so as to ensure that the Mapping relationship in the Mapping Table is correct. The following mapping relationship can be known from the mapping table in this embodiment: the virtual processor VCPU _ # M corresponds to the physical processor CPU _ # X, and the virtual processor VCPU _ # N corresponds to the physical processor CPU _ # Y.)
As per claims 6-10, these are method claims corresponding to the chip system claims 1-5. Therefore, rejected based on similar rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DONG U KIM whose telephone number is (571)270-1313. The examiner can normally be reached 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached at 5712723338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DONG U KIM/Primary Examiner, Art Unit 2197
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