DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 1-31) in the reply filed on 12-1-2015 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9, 13-14, 22 and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tang (US 2022/0028593).
[claim 1] A chip package (fig. 23, 23A, 23B, 23C ) for a galvanically isolated integrated circuits (ICs), the chip package comprising: a lead frame (lead frame structure as shown in fig. 23 which including but not limited to the die attach pads 2304/2308, leads 2310 in multilevel substrate 2307, fig. 23/23A and the conductive leads attached to die attach pads, [0046]) with first and second sides (top and bottom sides of fig. 23); first and second semiconductor dies (2306/2302, fig. 23, [0046]) disposed on the first side of the lead frame; a molding material (2320, fig. 23, [0051]) configured to cover a portion of the lead frame and forming a package body; a ferromagnetic core (2314/2321, fig. 23, [0052]) disposed in the package body adjacent the second side of the lead frame; and first and second coils (2311/2309, fig. 23, [0052]) disposed in the package body about the ferromagnetic core in a transformer configuration [0052], each coil including a plurality of windings [0052]; wherein the first and second coils and ferromagnetic core are disposed within the package body on the second side of the lead frame (fig. 23, 23A), opposite to the first side.
[claim 2] The chip package of claim 1, further comprising first (2308, fig. 23, [0048]) and second (2304, fig. 23, [0048]) die pads, wherein the first and second semiconductor dies are disposed on first and second die pads, respectively.
[claim 3] The chip package of claim 2, wherein the first and/or second die comprises an integrated circuit [0047][0048].
[claim 5] The chip package of claim 1, further comprising an insulator material disposed between the first and second coils (the package body 2320 in which the coils are embedded and are separated as it fills is the void may be made of plastic which is an insulator, [0051]).
[claim 6] A chip package (fig. 23, 23A, 23B, 23C ) comprising: a lead frame (lead frame structure as shown in fig. 23 which including but not limited to the die attach pads 2304/2308, leads 2310 in multilevel substrate 2307, fig. 23/23A and the conductive leads attached to die attach pads, [0046]) having first and second sides (top and bottom sides of fig. 23) and configured to receive first and second semiconductor dies on the first side (fig. 23); a package body (2320, fig. 23, [0051]) including molding material and configured to cover a portion the lead frame; a transformer core (2314/2321, fig. 23, [0052]) disposed in the package body on the second side of the lead frame; and first and second coils (2311/2309, fig. 23, [0052]) having windings disposed about the transformer core in a transformer configuration [0052] and disposed in the package body; wherein the first and second coils and transformer core are disposed on the second side of the lead frame (fig. 23), opposite to the first side.
[claim 7] The chip package of claim 6, further comprising first and second semiconductor dies disposed on the first side of the lead frame (fig. 23).
[claim 8] The chip package of claim 7, wherein the first and second coils are configured to magnetically couple the first and second semiconductor dies [0055].
[claim 9] The chip package of claim 8, wherein the first and second semiconductor dies comprise first and second integrated circuits, respectively [0047][0048].
[claim 13] The chip package of claim 7, further comprising first (2308, fig. 23, [0048]) and second (2304, fig. 23, [0048]) die pads disposed on the first side of the lead frame and configured to receive the first and second semiconductor dies, respectively.
[claim 14] The chip package of claim 6, wherein the lead frame comprises a partially etched lead frame (the structure of the lead frame of fig. 23 may be the result of an etching process).
[claim 22] The chip package of claim 7, further comprising a first plurality of wire (2346, fig. 23, [0048] on the left upper side of fig. 23) bonds connecting the lead frame to the first semiconductor die.
[claim 23] The chip package of claim 22, further comprising a second plurality of wire bonds (2346, fig. 23, [0048] on the right lower side of fig. 23) connecting the lead frame to the second semiconductor die.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2022/0028593).
Tang discloses the chip package of claim 6 but does not expressly disclose that the shortest distance between first and second conductive portions of the lead frame is at least 8 mm.
Nevertheless it would have been obvious to one of ordinary skill before the time of filing to have made the shortest distance between first and second conductive portions of the lead frame at least 8 mm , since it has been held that where the general conditions of a claim are disclosed in prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It also been held that the normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003). The claimed range is a result-effective variable since the amount of spacing between the first and second conductive portions would affect how much space the overall device takes up.
Claim(s) 24-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2022/0028593).
Tang discloses the chip package of claim 23 but does not expressly disclose that a shortest distance between the first and second pluralities of wire bonds is at least 8 mm.
Nevertheless it would have been obvious to one of ordinary skill before the time of filing to have made the shortest distance between the first and second pluralities of wire bonds at least 8 mm, since it has been held that where the general conditions of a claim are disclosed in prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It also been held that the normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages. In re Peterson, 315 F.3d 1325, 1330 (Fed. Cir. 2003). The claimed range is a result-effective variable since the amount of spacing between the first and second pluralities of wire bonds would affect how much space the overall device takes up.
Claim(s) 4, 10-12, and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang (US 2022/0028593) in view of Vinciarelli (US 6,107,860).
Tang discloses the chip package of claims 3 and 9 but does not expressly that the integrated circuit comprises a gate driver circuit.
Vinciarelli discloses a chip package wherein the integrated circuit comprises a gate driver circuit (200, fig. 9a, 602, fig. 15, lines 50-56, col. 16 & lines 55-67, col. 13) in a die which drives a transformer (204, fig. 9a, lines 55-67, col. 13).
It would have been obvious to one of ordinary skill in the art before the time of filing to have the integrated circuit comprises a gate driver circuit in a die in order to provide a means to drive the transformer.
With this modification Tang discloses:
[claim 4] The chip package of claim 3, wherein the integrated circuit comprises a gate driver circuit (upon modification).
[claim 10] The chip package of claim 9, wherein the first or second integrated circuit comprises a gate driver (upon modification).
[claim 11] The chip package of claim 10, wherein the gate driver is configured to receive power from the transformer (via 250 in fig. 9a, Vinciarelli, lines 35-39, col. 9).
[claim 12] The chip package of claim 10, wherein the gate driver is configured to receive control signals from the transformer (via 254 in fig. 9a, Vinciarelli, lines 35-39, col. 9).
[claim 31] The chip package of claim 9, wherein the first or second integrated circuit comprises a gate driver (upon modification).
Conclusion
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/AMAR MOVVA/ Primary Examiner, Art Unit 2898