DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application and claims filed 4/14/2023. Claims 1-20 are pending and have been examined. Claims 1-18 and 20 are rejected, and claims 1-20 are objected to.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The present application claims foreign priority to Korean patent application No. KR10-2022-0108939 filed on 8/30/2022.
The examiner acknowledges that a certified copy of Korean patent application No. KR10-2022-0108939 has been retrieved (on 5/18/2023, in Korean). The examiner notes that a translation of Korean patent application No. KR10-2022-0108939 does not appear to have been furnished to-date.
Although a certified copy of the foreign priority application was retrieved, a translation of said application has not yet been made of record in accordance with 37 CFR 1.55. See MPEP §§ 215 and 216. Applicant is reminded of requirements set forth in 37 CFR 1.55(g)(3)-(4) Claim for foreign priority:
“(3) An English language translation of a non-English language foreign application is not required except:
(i) When the application is involved in an interference (see § 41.202 of this chapter) or derivation (see part 42 of this chapter) proceeding;
(ii) When necessary to overcome the date of a reference relied upon by the examiner; or
(iii) When specifically required by the examiner.
(4) If an English language translation of a non-English language foreign application is required, it must be filed together with a statement that the translation of the certified copy is accurate” (emphasis added).
Since an English language translation of Application No. KR10-2022-0108939 has not been made of record to-date, the Examiner notes that prior art references with a filing date or a publication date prior to the instant Application’s filing date of 4/14/2023 are considered applicable prior art references.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statement filed 4/14/2023, which complies with 37 CFR 1.97. As such, the information disclosure statement has been placed in the application file and the information referred to therein has been considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference characters not mentioned in the description:
250 (see, e.g., paragraphs 50-56 describing FIG. 3).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency.
Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Reference character 250 shown in Figure 3 is not described in applicant’s specification (see, e.g., paragraphs 50-56 describing FIG. 3). Appropriate correction is required.
Claim Objections
Claims 1-16 are objected to because of the following informalities:
The last step of claim 1 recites “a Grover oracle quantum circuit”. However, applicant previously introduced “a Grover oracle quantum circuit” in line 1 of the claim. As such, for clarity and consistency to refer to the previously-introduced “Grover oracle quantum circuit”, it appears the subsequent recitation of “a Grover oracle quantum circuit” should read “[[a]] the Grover oracle quantum circuit.” Appropriate correction is required.
The last operation of independent claim 9 recites “a Grover oracle quantum circuit”. However, applicant previously introduced “a Grover oracle quantum circuit” in line 1 of the claim. Thus, for clarity and consistency to refer to the previously-introduced “Grover oracle quantum circuit”, it appears the subsequent recitation of “a Grover oracle quantum circuit” should read “[[a]] the Grover oracle quantum circuit.” Claim 9 also recites “an oracle quantum circuit” in lines 2-3. For clarity and consistency to refer to the previously-introduced “Grover oracle quantum circuit”, it appears the recitation of “an oracle quantum circuit” should read “[[an]] the Grover oracle quantum circuit.” Appropriate correction is required.
Claims 8 and 16, which depend directly from intervening claims 7 and 15, respectively, which in turn depend directly from claims 6 and 14, both recite “a multiple-controlled Toffoli gate.” (see, line 4 of claims 8 and 16). However, applicant previously introduced “a multiple-controlled Toffoli gate” in line 2 of claims 6 and 14. For clarity and consistency to refer to the previously-introduced “multiple-controlled Toffoli gate”, it appears the recitation of “a multiple-controlled Toffoli gate” should read “[[a]] the multiple-controlled Toffoli gate.” (see, e.g., recitations of “the multiple-controlled Toffoli gate” in line 2 of intervening claims 7 and 15). Appropriate correction is required.
Also, claims 2-8 and 10-16, which depend directly or indirectly from claims 1 and 9, respectively, are objected to based on their respective dependencies from claims 1 and 9.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Independent claim 1 recites “analyzing data qubits and sub-qubits that are used for a design of an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit” (see, lines 2-4) and independent claim 9 recites “analyze data qubits and sub-qubits that are used for a design of an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit” (see, lines 5-7). These recitations are unclear and indefinite. In particular, it is unclear how analysis of qubits can be “used for a design of an analysis target cipher quantum circuit” where the target cipher quantum circuit is “configured to implement an analysis target cipher based on the analysis target cipher quantum circuit”. That is, the claims require that the claimed “target cipher quantum circuit” that is being designed in these claim steps is “configured to implement an analysis target cipher based on” itself (i.e., “based on the analysis target cipher quantum circuit” that is simultaneously in the process of being designed). It is unclear how an “analysis target cipher quantum circuit” that is still being designed (i.e., in the design stage, undergoing a design process) can, at the same time (i.e., in the same step/operation) already be “configured to implement an analysis target cipher based on the analysis target cipher quantum circuit” (i.e., based on the still-being-designed “analysis target cipher quantum circuit” itself). For the purposes of determining patent eligibility and comparison with the prior art, recitations of “analyzing data qubits and sub-qubits that are used for a design of an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit” and “analyze data qubits and sub-qubits that are used for a design of an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit” are being interpreted as analyzing data qubits and sub-qubits, designing, based at least in part on the analyzing, an analysis target cipher quantum circuit, wherein the analysis target cipher quantum circuit is configured to implement an analysis target cipher. Appropriate correction is required.
Independent claims 1 and 9 recite “allocating the data qubits and the sub-qubits” and “allocate the data qubits and the sub-qubits” (see, e.g., the penultimate step of claim 1, and the penultimate operation of claim 9). These recitations appear to be missing one or more words, and are unclear and indefinite. In particular, it is unclear what the recited “data qubits and the sub-qubits” are being allocated to or what the allocations are for. That is, it is unclear what the object, destination or purpose of the “allocation” and “allocate” is for the recited allocating of “the data qubits and the sub-qubits”. Aside from reciting “information about allocation of the data qubits and the sub-qubits” (see, the last 2 lines of claim 1 and the last line of claim 9), these claims and their dependent claims do not further mention the allocating or allocation of “the data qubits and the sub-qubits”, let alone what the allocating or allocation is for (i.e., unclear if the recited “allocating” and “allocate” is allocation of data values to the qubits, and/or allocation of resources such as memory, storage or processing resources). For the purposes of determining patent eligibility and comparison with the prior art, recitations of “allocating the data qubits and the sub-qubits” and “allocate the data qubits and the sub-qubits” are being interpreted as allocating any data values or resources, such as, but not limited to memory, storage, processing or other hardware resources, to or for “the data qubits and the sub-qubits”. Appropriate correction is required.
Also, claims 2-8 and 10-16, which depend directly or indirectly from claims 1 and 9, respectively, are rejected under 35 U.S.C. 112(b) as being indefinite under the same rationale as claims 1 and 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 5-10, 13-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii (U.S. Patent Application Pub. No. 2024/0296366 A1, hereinafter “Ishii”)1 in view of non-patent literature Grassl et al. ("Applying Grover's algorithm to AES: quantum resource estimates." arXiv preprint arXiv:1512.04965 (2015), hereinafter “Grassl”), and further in view of Chinese Patent Application Publication No. CN116541947A to Benyuan Quantum Computing Technology Hefei Co Ltd (hereinafter "Benyuan").
Regarding claim 1, Ishii discloses the invention as claimed including a method for generating a Grover oracle quantum circuit (see, e.g., paragraphs 44, “a quantum circuit design method”, 89, “a quantum circuit for causing the quantum computer 300 to execute the Grover's algorithm” and 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged … in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” [i.e., a method for generating a Grover oracle quantum circuit]), comprising:
analyzing data qubits and sub-qubits that are used for a design of an analysis target … quantum circuit configured to implement an analysis target … based on the analysis target … quantum circuit2 (see, e.g., paragraphs 48-49, “operation on a plurality of first qubits among the qubits q0, q1, and q2 included in the first quantum circuit 1. … an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.”, “processing unit 11 generates the second quantum circuit obtained by converting the first element 1a into a first equivalent circuit 2 in the first quantum circuit 1 and converting the second element 2b into a second equivalent circuit 3 arranged by symmetrically moving elements of the first equivalent circuit 2 in an arrangement direction of the plurality of first qubits. Quantum gates included in the first equivalent circuit 2 are two-qubit gates 2a to 2e or a one-qubit gate.” and 55, “the operation of inverting, according to two control bits among three first qubits, a phase of one target bit among the first qubits.” [i.e., analyze data qubits and sub-qubits/control bits to design and generate an equivalent analysis quantum circuit configured to implement the analysis target based on the analysis target quantum circuit]); …
generating a phase inversion quantum circuit configured to invert a phase of a target qubit by comparing output qubits of the analysis target … quantum circuit with a preset comparison target value (see, e.g., paragraphs 48, “the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.”, 55, “the predetermined operation is the operation of inverting, according to two control bits among three first qubits, a phase of one target bit among the first qubits.” and 92, “the respective qubits to be two control bits of the CCZ gate. The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit” [i.e., generate/construct a phase inversion quantum circuit to invert a phase of a target qubit by comparing output qubits of the analysis target quantum circuit with a predetermined/preset comparison target bit value]);
configuring a Grover oracle using the analysis target … quantum circuit, … and the phase inversion quantum circuit (see, e.g., paragraphs 78, “An oracle Uf is applied in inversion processing of the Grover's algorithm.”, 89, “a quantum circuit … to execute the Grover's algorithm”, 92, “in the quantum circuit 50, … The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.” and 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged … in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” [i.e., processing/configuring a Grover oracle using the analysis target quantum circuit and the phase inversion quantum circuit]);
allocating the data qubits and the sub-qubits3 (see, e.g., paragraphs 46, “the first quantum circuit 1 has lines corresponding to the respective qubits q0, q1, and q2 . In the first quantum circuit 1, the line corresponding to the qubit q0, the line corresponding to the qubit q1, and the line corresponding to the qubit q2 are arranged in order from the top.” and 48-49, “operation on a plurality of first qubits among the qubits q0 , q1, and q2 included in the first quantum circuit 1. … an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.”, “generates the second quantum circuit … by symmetrically moving elements of the first equivalent circuit 2 in an arrangement direction of the plurality of first qubits. Quantum gates included in the first equivalent circuit 2 are two-qubit gates 2a to 2e or a one-qubit gate.” [i.e., allocating/arranging lines for the data qubits and the target and control bits/sub-qubits in the quantum circuit]); and
generating a Grover oracle quantum circuit4 based on information about allocation of the data qubits and the sub-qubits (see, e.g., paragraphs 90, “the quantum circuit that executes the Grover's algorithm with three qubits. A quantum circuit 50 indicates order of operations for the respective qubits q0, q1, and q2 in a case where the Grover's algorithm with … three qubits. The quantum circuit 50 has lines corresponding to the respective qubits q0, q1, and q2.”, 92, “in the quantum circuit 50, each of blocks described as Z arranged on the lines corresponding to the respective qubits q0, q1, and q2 and two points coupled to the block described as Z by a line and arranged on the lines corresponding to the respective qubits q0, q1, and q2 indicate a CCZ gate. … respective qubits to be two control bits of the CCZ gate. The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.”, 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged … in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” and 106, “computer 100 generates a quantum circuit obtained by converting each of the two CCZ gates included in the quantum circuit 50 into the equivalent circuit 61. … computer 100 instructs the qubit control device 200 to control qubits according to the generated quantum circuit.” [i.e., generating a Grover oracle quantum circuit based on information about the allocated data qubits and target and control bits/sub-qubits]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit;
generating a … quantum circuit based on the analysis target cipher quantum circuit;
comparing output qubits of the analysis target cipher quantum circuit with a preset comparison target value; and
configuring a Grover oracle using the analysis target cipher quantum circuit.
In the same field, analogous art Grassl teaches an analysis target cipher quantum circuit configured to implement an analysis target cipher based on the analysis target cipher quantum circuit (see, e.g., Abstract, “We present quantum circuits to … analyze the quantum resources … to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs” and pages 3-4, sects 2-3, “Grover’s algorithm … we first focus on the circuit shown in part (b) of the figure and analyze”, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key.” [i.e., analyze/analysis target ciphertext/cipher quantum circuit to implement an analysis target cipher key based on the quantum circuit]);
generating a … quantum circuit based on the analysis target cipher quantum circuit (see, e.g., FIG. 1 – depicting a generated “Quantum circuit to implement Grover’s algorithm”, Abstract, “We present quantum circuits to implement … the number of elementary logical quantum gates that are needed to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs” and pages 1, “Grover’s algorithm needs to be realized as a circuit … requires some analysis as the circuit implementation is required … We provide reversible circuits” and pages 2-3, sects 2-3, “implement AES as a quantum circuit, … we need to provide … Grover’s algorithm [15]. The Grover procedure takes as an input a quantum circuit”, “needed in Grover’s algorithm is a circuit which … indicates if this key is equal to the secret target … and compare the result with the (assumed to be known) corresponding ciphertext under the secret target” [i.e., generate/implement a quantum circuit based on the analysis target ciphertext quantum circuit]);
comparing output qubits of the analysis target cipher quantum circuit with a preset comparison target value (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm” with output “qubits and a single qubit state … in the lower register” and page 3, sect. 3, “compare the result with the (assumed to be known) corresponding ciphertext under the secret target”, page 5, sect. 3.2.1, “We will devote 128 qubits to hold the current internal state.” and page 10, sect. 3.4, “the result is compared with the given ciphertexts” [i.e., compare output qubits of the ciphertext quantum circuit with a preset/given/known comparison target key value]); and
configuring a Grover oracle using the analysis target cipher quantum circuit (see, e.g., FIG. 1 – depicting configuring of a “Quantum circuit to implement Grover’s algorithm” and “One round of Grover’s algorithm. Shown is the operator G = Uf” [i.e., a Grover oracle function Uf], Abstract, “We present quantum circuits to … implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs.” and page 4, sects. 2-3, “providing exact quantum resource estimates for Grover’s algorithm … after the implementation details of the “oracle” function Uf”, “needed in Grover’s algorithm is a circuit which … indicates if this key is equal to the secret target … and compare the result with the … ciphertext under the secret target” [i.e., configure/implement a Grover oracle using the target ciphertext quantum circuit]).
Ishii and Grassl are analogous art because they are both directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, and Grassl, Abstract and pages 3-4, sect. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii to incorporate the teachings of Grassl to provide “quantum circuits to implement an exhaustive key search for the Advanced Encryption Standard (AES)” and to “establish precise bounds for the number of qubits and the number of elementary logical quantum gates that are needed to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs.” (See, e.g., Grassl, Abstract). Doing so would have allowed Ishii to use Grassl’s quantum circuits to “provide reversible circuits that implement the full Advanced Encryption Standard AES-k for each standardized key size” and to “establish resource estimates for the number of qubits and the number of Toffoli gates” [T-gates] while reducing circuit costs because “Clifford gates typically are much cheaper than the T-gate … When breaking down the circuit to the level of T-gates we therefore pay attention to reducing the overall T-count … to optimize the T-count”, as suggested by Grassl (See, e.g., Grassl, pages 1-1, sect. 1).
Although Ishii in view of Grassl substantially teaches the claimed invention, Ishii in view of Grassl is not relied on to teach generating a dagger quantum circuit based on the analysis … quantum circuit; and
configuring a Grover oracle using the analysis target … quantum circuit, the dagger quantum circuit and the phase inversion quantum circuit.
In the same field, analogous art Benyuan teaches generating a dagger quantum circuit based on the analysis … quantum circuit (see, e.g., page 6, “phase estimation circuit t Stored on the auxiliary bit, then a preset quantum logic gate can be added, for example, to control the number of test conditions to be met by the Z gate … The transposed conjugation (inverse process) operation is performed to restore the initial superposition state, thereby constructing a second quantum circuit corresponding to the preset test condition … the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover, so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits” [i.e., generate/construct a dagger/conjugate transpose 2nd quantum circuit based on an analysis/test quantum circuit]).
Ishii, Grassl and Benyuan are analogous art because they are each directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, Grassl, Abstract and pages 3-4, sect. 2, and Benyuan, Abstract and pages 2-3 and 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii in view of Grassl to incorporate the teachings of Benyuan to provide a quantum circuit generating/constructing technique where “The transposed conjugation (inverse process) operation is performed to restore the initial superposition state, thereby constructing a second quantum circuit corresponding to the preset test condition.” and the technique includes “obtaining a third quantum circuit corresponding to the Grover based on the initialization superposition circuit module and the phase estimation Oracle circuit”, where “the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover” (See, e.g., Benyuan page 6). Doing so would have allowed Ishii in view of Grassl to use Benyuan’s circuit generating/constructing technique “so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits in the overlapped state preparation line” and “so that the quantum computing technology can be applied”, as suggested by Benyuan (See, e.g., Benyuan, page 6).
With respect to independent claim 9, claim 9 is substantially similar to claim 1 and therefore is rejected on the same ground as claim 1, discussed above. In particular, claim 9 is an apparatus claim with operations that correspond to the method steps of claim 1.
Ishii further discloses an apparatus for generating a Grover oracle quantum circuit (see, e.g., paragraphs 89-90, “a quantum circuit for causing the quantum computer 300 to execute the Grover's algorithm”, “the quantum circuit that executes the Grover's algorithm”, 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged” and 106, “computer 100 generates a quantum circuit obtained by converting each of the two CCZ gates included in the quantum circuit 50” [i.e., computer/apparatus for generating a Grover oracle quantum circuit]), comprising: a memory configured to store a control program for generating an oracle quantum circuit5; and a processor configured to execute the control program stored in the memory, wherein the processor is configured (see, e.g., paragraphs 63-64, “control computer 100 is controlled by a central processing unit (CPU) 101. The CPU 101 is a processor that executes a program command … the CPU 101 executing a program may be implemented by an electronic circuit … To the CPU 101, a random access memory (RAM) 102 … [is] coupled”, “RAM 102 is a main storage device of the control computer 100. In the RAM 102, … an application program to be executed by the CPU 101 is temporarily stored. [i.e., computer/apparatus for generating the quantum circuit includes a memory storing a control program for generating the quantum circuit and a configured processor/CPU to execute the stored program]).
Regarding claims 2 and 10, as discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 1 and the apparatus of claim 9.
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing wherein a total number of qubits required for configuration of the analysis target cipher quantum circuit corresponds to a sum of a number of data qubits and a number of sub-qubits.
In the same field, analogous art Grassl teaches wherein a total number of qubits required for configuration of the analysis target cipher quantum circuit corresponds to a sum of a number of data qubits and a number of sub-qubits (see, e.g., Tables 2-4 – listing total numbers of required data qubits and sums of sub-qubits as “Total” “#qubits” for “Quantum resource estimates for the implementation”, and pages 6, sect. 3.2.1, “Trying to reduce the number of total qubits required at each step, the actual calculation of computing α-1 fits into 40 qubits total, producing |α>,|α>-1, and twenty-four reinitialized qubits as output.” and 9-10, Sects 3.3-3.4, “The numbers listed in the three tables below [Tables 2-4] show the costs in gates, depth and qubits to achieve the output of each AES-k system.”, “The number of qubits is given by r times the number of qubits within each AES box. Once the AES boxes have been computed, the result is compared with the given ciphertexts … denoting by sk the total number of qubits, tk the total number of T-gates, ck the total number of Clifford gates, бk the overall T-depth and ∆k the overall depth, where k = 128; 192; 256, then we obtain the following estimates for the overall Grover algorithm.” [i.e., a total number, sk, of qubits required for configuration of the analysis target ciphertext quantum circuit corresponds to a sum of a number of data qubits and a number of reinitialized sub-qubits]).
Ishii and Grassl are analogous art because they are both directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, and Grassl, Abstract and pages 3-4, sect. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii to incorporate the teachings of Grassl to provide “quantum circuits to implement an exhaustive key search for the Advanced Encryption Standard (AES)” and to “establish precise bounds for the number of qubits and the number of elementary logical quantum gates that are needed to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs.” (See, e.g., Grassl, Abstract). Doing so would have allowed Ishii to use Grassl’s quantum circuits to “provide reversible circuits that implement the full Advanced Encryption Standard AES-k for each standardized key size” and to “establish resource estimates for the number of qubits and the number of Toffoli gates” [T-gates] while reducing circuit costs because “Clifford gates typically are much cheaper than the T-gate … When breaking down the circuit to the level of T-gates we therefore pay attention to reducing the overall T-count … to optimize the T-count”, as suggested by Grassl (See, e.g., Grassl, pages 1-1, sect. 1).
Regarding claims 5 and 13, as discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 1 and the apparatus of claim 9.
Ishii further discloses wherein the phase inversion quantum circuit inverts the phase of the target qubit when the output qubits of the analysis target … quantum circuit are identical to the comparison target value (see, e.g., paragraphs 47-48, “elements arranged in the first quantum circuit 1 include … an X gate, a CCZ gate … the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.” and 92, “in the quantum circuit 50, … in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.” [i.e., phase inversion quantum circuit inverts a phase a target qubit when output qubits of the analysis target quantum circuit when the output control qubits equal/are identical to the comparison target value of 1]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing wherein the phase inversion quantum circuit inverts the phase of the target … when the output qubits of the analysis target cipher quantum circuit are identical to the comparison target value.
In the same field, analogous art Grassl teaches wherein the phase inversion quantum circuit inverts the phase of the target … when the output qubits of the analysis target cipher quantum circuit are identical to the comparison target value (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm.” and “One round of Grover’s algorithm. Shown is … its circuit decomposition. Note that the effect of the gates between the two layers of Hadamard gates is to invert the phase of the basis state” [i.e., a phase inversion quantum circuit inverts the phase] and page 4, sect. 3, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key.” [i.e., invert the phase of the target when the output result qubits of the analysis target ciphertext quantum circuit are identical to the comparison target key value]).
The motivation to combine Ishii and Grassl is the same as discussed above with respect to claims 2 and 10.
Regarding claims 6 and 14, as discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 1 and the apparatus of claim 9.
Ishii further discloses wherein the phase inversion quantum circuit comprises at least one of a multiple-controlled Toffoli gate having multiple-controlled qubits, or a Pauli-X gate, or a combination thereof (see, e.g., paragraphs 47-48, “elements arranged in the first quantum circuit 1 include … an X gate, a CCZ gate … the CCZ gate is arranged by setting two control bits and one target bit. The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.”, “the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.”, 55, “the predetermined operation is the operation of inverting, according to two control bits among three first qubits, a phase of one target bit among the first qubits.”, 91, “in the quantum circuit 50, each of blocks described as X arranged on the lines corresponding to the respective qubits q0 , q1, and q2 indicates an X gate. The X gate indicates an operation of inverting a bit of a qubit”, 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged”, 106, “in quantum calculation by the quantum computer 300, … errors in the qubits include an error due to interference with an external environment (stochastic Pauli” and 126, “the CCX gate is also called a Toffoli gate.” [i.e., the phase inversion quantum circuit includes a Toffoli gate/CCX with controlled qubits or a Pauli X gate]).
Additionally or alternatively, in the same field, analogous art Grassl also teaches wherein the phase inversion quantum circuit comprises at least one of a multiple-controlled Toffoli gate having multiple-controlled qubits (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm … and its circuit decomposition. Note that the effect of the gates between the two layers of Hadamard gates is to invert the phase of the basis state”, Table 1 – listing “#gates” of “Toffoli” gates and “#qubits” for “Quantum resource estimates for the key expansion phase of AES” and pages 3, sect. 2, “Toffoli gates per phase operation” and 7, sect 3.2.1, “Toffoli gates on n > 3 qubits” [i.e., phase inversion circuit includes multiple controlled Toffoli gate with multiple-controlled qubits]).
The motivation to combine Ishii and Grassl is the same as discussed above with respect to claims 2 and 10.
Additionally or alternatively, in the same field, analogous art Benyuan also teaches wherein the phase inversion quantum circuit comprises at least one of a multiple-controlled Toffoli gate having multiple-controlled qubits, or a Pauli-X gate, or a combination thereof (see, e.g., pages 4-6, “the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as … Z gates… ; two or more bit quantum logic gates, such as … toffoli gates”, “Pauli-X gate and H gate can be added to the first qubit”, “a Z gate is added to the bit to perform phase inversion for marking, so that q+1 additional quantum bits are needed in total” [i.e., the phase inversion quantum circuit includes a Toffoli gate and/or a Pauli X-gate]).
Ishii, Grassl and Benyuan are analogous art because they are each directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, Grassl, Abstract and pages 3-4, sect. 2, and Benyuan, Abstract and pages 2-3 and 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii in view of Grassl to incorporate the teachings of Benyuan to provide a quantum circuit generating/constructing technique where “The transposed conjugation (inverse process) operation is performed to restore the initial superposition state, thereby constructing a second quantum circuit corresponding to the preset test condition.” and the technique includes “obtaining a third quantum circuit corresponding to the Grover based on the initialization superposition circuit module and the phase estimation Oracle circuit”, where “the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover” (See, e.g., Benyuan page 6). Doing so would have allowed Ishii in view of Grassl to use Benyuan’s circuit generating/constructing technique “so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits in the overlapped state preparation line” and “so that the quantum computing technology can be applied”, as suggested by Benyuan (See, e.g., Benyuan, page 6).
Regarding claims 7 and 15, as discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 6 and the apparatus of claim 14.
Ishii further discloses wherein the multiple-controlled Toffoli gate is configured using a combination of Toffoli gates (see, e.g., paragraphs 126, “conversion processing of a CCX gate by the gate conversion unit 150 will be described. Note that the CCX gate is also called a Toffoli gate.” and 131, “The gate conversion unit 150 converts the CnNOT gate included in the quantum circuit into an equivalent circuit obtained by combining the CCX gates” [i.e., the Toffoli/CCX gate is configured using a combination of Toffoli/CCX gates]).
Regarding claims 8 and 16, as discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 6 and the apparatus of claim 14.
Ishii further discloses wherein output qubits of the phase inversion quantum circuit are connected to the output qubits of the analysis target … quantum circuit, and a number of qubits identical to a number of output qubits of the phase inversion quantum circuit are used as control qubits of a multiple-controlled Toffoli gate6 (see, e.g., paragraphs 126-127, “conversion processing of a CCX gate by the gate conversion unit 150 will be described. Note that the CCX gate is also called a Toffoli gate.”, “A CCX gate 70 indicates that, in a case where two control bits are "1", the X gate is acted on one target bit (phase is inverted). In a quantum circuit, … a qubit to be the target bit of the CCX gate 70, and points coupled to the symbol by a line are arranged on lines corresponding to the respective qubits to be the two control bits.” and 131-132, “a bit of one target bit is inverted in a case where all n (n is an integer equal to or larger than 1) control bits are "1". In a quantum circuit, … a qubit to be the target bit … and points coupled to the symbol by a line are arranged on lines corresponding to the respective qubits to be the n control bits. The gate conversion unit 150 converts the CnNOT gate included in the quantum circuit into an equivalent circuit obtained by combining the CCX gates”, “equivalent circuit 73 includes CCX gates in each of which any two of the qubits q0 to q4, a0, a1, a2, and a3 are control bits and any one of the qubits q0 to q4 and a0 to a3 is a target bit.” [i.e., output qubits of the phase conversion quantum circuit are connected to output qubits of the analysis target quantum circuit, and a number n of qubits equal/equivalent to the number of output qubits of the phase inversion circuit are used as control qubits of the CCX gate/Toffoli gate]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing wherein output qubits of the phase inversion quantum circuit are connected to the output qubits of the analysis target cipher quantum circuit.
In the same field, analogous art Grassl teaches wherein output qubits of the phase inversion quantum circuit are connected to the output qubits of the analysis target cipher quantum circuit (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm” with output “qubits and a single qubit state … in the lower register … and its circuit decomposition. Note that the effect of the gates between the two layers of Hadamard gates is to invert the phase of the basis state |0> on the upper k bits” [i.e., output qubits of the phase inversion circuit], Abstract, “We present quantum circuits to … analyze the quantum resources … to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs” and pages 3-4, sects 2-3, “Grover’s algorithm … we first focus on the circuit shown in part (b) of the figure and analyze”, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key. …“compare the result with the (assumed to be known) corresponding ciphertext under the secret target” and page 5, sect. 3.2.1, “We will devote 128 qubits to hold the current internal state.” [i.e., output qubits of the phase inversion quantum circuit are connected to the output qubits of the analysis target ciphertext quantum circuit]).
The motivation to combine Ishii and Grassl is the same as discussed above with respect to claims 2 and 10.
Regarding independent claim 17, Ishii discloses the invention as claimed including a Grover oracle quantum circuit (see, e.g., paragraphs 89, “a quantum circuit for causing the quantum computer 300 to execute the Grover's algorithm” and 95, “in the quantum circuit 50, a combination of the X gates and the CCZ gate indicating processing of applying the oracle is arranged … in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” [i.e., a Grover oracle quantum circuit]), comprising:
an analysis target … quantum circuit configured to allocate an input value to input qubits and allocate an output value to output qubits (see, e.g., paragraphs 46, “the first quantum circuit 1 has lines corresponding to the respective qubits q0, q1, and q2.”, 48-49, “operation on a plurality of first qubits among the qubits q0 , q1, and q2 included in the first quantum circuit 1. … an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.”, “generates the second quantum circuit … by symmetrically moving elements of the first equivalent circuit 2 in an arrangement direction of the plurality of first qubits.” and 95, “in the quantum circuit 50, observation for each of the qubits q0, q1, and q2 is arranged on the right side of the combination of the gates indicating the amplification processing. By the observation indicated in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” [i.e., analysis target quantum circuit allocates an input value to input qubits/1st qubits for an operation/processing and allocates an output value to processing result/output qubits]);
a phase inversion quantum circuit configured to receive an output of the analysis target … quantum circuit as an input (see, e.g., paragraphs 47-48, “elements arranged in the first quantum circuit 1 include … an X gate, a CCZ gate … The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.”, “the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.” and 55, “the predetermined operation is the operation of inverting, according to two control bits among three first qubits, a phase of one target bit among the first qubits.” [i.e., a phase inversion quantum circuit that receives output target bits of the analysis target quantum circuit as input]), compare the output with a preset comparison target value, and invert a phase of a target qubit when the output is identical to the preset comparison target value (see, e.g., paragraphs 48, “the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.” and 92, “in the quantum circuit 50, … in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.” [i.e., comparing output qubits of the analysis target quantum circuit with a predetermined/preset comparison target bit value, and invert a phase a target qubit when the output equals a predetermined/preset comparison target value of 1]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing an analysis target cipher quantum circuit configured to allocate an input value to input qubits and allocate an output value to output qubits; and
a phase inversion quantum circuit configured to receive an output of the analysis target cipher quantum circuit as an input.
In the same field, analogous art Grassl teaches an analysis target cipher quantum circuit configured to allocate an input value to input qubits and allocate an output value to output qubits (see, e.g., Abstract, “We present quantum circuits to … analyze the quantum resources … to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs” and pages 3-4, sects 2-3, “Grover’s algorithm … we first focus on the circuit shown in part (b) of the figure and analyze”, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key.” and pages 5-6, sect 3.2.1, “We will devote 128 qubits to hold the current internal state.”, “the number of total qubits required at each step, the actual calculation of computing α-1 fits into 40 qubits total, producing … twenty-four reinitialized qubits as output.” [i.e., analyze/analysis target ciphertext/cipher quantum circuit to devote/allocate an input state/value to input qubits and an output value to output qubits]); and
a phase inversion quantum circuit configured to receive an output of the analysis target cipher quantum circuit as an input (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm.” and “One round of Grover’s algorithm. Shown is … its circuit decomposition. Note that the effect of the gates between the two layers of Hadamard gates is to invert the phase of the basis state” [i.e., a phase inversion quantum circuit] and Abstract, “We present quantum circuits … we establish precise bounds for the number of qubits and the number of elementary logical quantum gates that are needed to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs.” and pages 3-4, sect. 2, “set of given plaintext-ciphertext pairs.”, “and then computing the equality function of the resulting vector with the given ciphertexts” [i.e., a phase inversion quantum circuit to receive the output of the target ciphertext quantum circuit as given input]).
Ishii and Grassl are analogous art because they are both directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, and Grassl, Abstract and pages 3-4, sect. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii to incorporate the teachings of Grassl to provide “quantum circuits to implement an exhaustive key search for the Advanced Encryption Standard (AES)” and to “establish precise bounds for the number of qubits and the number of elementary logical quantum gates that are needed to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs.” (See, e.g., Grassl, Abstract). Doing so would have allowed Ishii to use Grassl’s quantum circuits to “provide reversible circuits that implement the full Advanced Encryption Standard AES-k for each standardized key size” and to “establish resource estimates for the number of qubits and the number of Toffoli gates” [T-gates] while reducing circuit costs because “Clifford gates typically are much cheaper than the T-gate … When breaking down the circuit to the level of T-gates we therefore pay attention to reducing the overall T-count … to optimize the T-count”, as suggested by Grassl (See, e.g., Grassl, pages 1-1, sect. 1).
Although Ishii in view of Grassl substantially teaches the claimed invention, Ishii in view of Grassl is not relied on to teach a dagger quantum circuit configured to invert values of the output qubits to initial values.
In the same field, analogous art Benyuan teaches a dagger quantum circuit configured to invert values of the output qubits to initial values (see, e.g., page 6, “phase estimation circuit t Stored on the auxiliary bit, then a preset quantum logic gate can be added, for example, to control the number of test conditions to be met by the Z gate … The transposed conjugation (inverse process) operation is performed to restore the initial superposition state, thereby constructing a second quantum circuit corresponding to the preset test condition … the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover, so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits” [i.e., a dagger/conjugate transpose 2nd quantum circuit]).
Ishii, Grassl and Benyuan are analogous art because they are each directed to implementing and using quantum circuits and quantum computers based on applying an oracle circuit and executing/processing Grover’s algorithm (see, e.g., Ishii, Abstract and paragraphs 39, 78 and 95, Grassl, Abstract and pages 3-4, sect. 2, and Benyuan, Abstract and pages 2-3 and 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ishii in view of Grassl to incorporate the teachings of Benyuan to provide a quantum circuit generating/constructing technique where “The transposed conjugation (inverse process) operation is performed to restore the initial superposition state, thereby constructing a second quantum circuit corresponding to the preset test condition.” and the technique includes “obtaining a third quantum circuit corresponding to the Grover based on the initialization superposition circuit module and the phase estimation Oracle circuit”, where “the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover” (See, e.g., Benyuan page 6). Doing so would have allowed Ishii in view of Grassl to use Benyuan’s circuit generating/constructing technique “so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits in the overlapped state preparation line” and “so that the quantum computing technology can be applied”, as suggested by Benyuan (See, e.g., Benyuan, page 6).
Regarding claim 18, as discussed above, Ishii in view of Grassl and Benyuan teaches the circuit of claim 17.
Ishii further discloses wherein a number of output qubits of the analysis target … quantum circuit is set to a value identical to a number of control qubits of the phase inversion quantum circuit (see, e.g., paragraphs 46-48, “the first quantum circuit 1 has lines corresponding to the respective qubits q0, q1, and q2.”, “elements arranged in the first quantum circuit 1 include … an X gate, a CCZ gate … The CCZ gate indicates that, in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.”, “the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.” and 92, “in the quantum circuit 50, … in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.” and 95, “in the quantum circuit 50, observation for each of the qubits q0, q1, and q2 is arranged on the right side of the combination of the gates indicating the amplification processing. By the observation indicated in the quantum circuit 50, a result of performing the inversion amplification processing of the Grover's algorithm once is output.” [i.e., a number of output qubits of the target analysis quantum circuit is equal/equivalent/identical to the number of control bits of the phase conversion quantum circuit]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing wherein a number of output qubits of the analysis target cipher quantum circuit is set to a value identical to a number of control qubits of the phase inversion quantum circuit.
In the same field, analogous art Grassl teaches wherein a number of output qubits of the analysis target cipher quantum circuit is set to a value identical to a number of control qubits of the phase inversion quantum circuit (see, e.g., FIG. 1 – depicting “Quantum circuit to implement Grover’s algorithm … for the case of AES has k = 128” with a number of output “qubits and a single qubit state … in the lower register … and its circuit decomposition. Note that the effect of the gates between the two layers of Hadamard gates is to invert the phase of the basis state |0> on the upper k bits” [i.e., a number of control qubits of the phase inversion circuit], Abstract, “We present quantum circuits to … analyze the quantum resources … to implement Grover’s quantum algorithm to extract the key from a small number of AES plaintext-ciphertext pairs” and pages 3-4, sects 2-3, “Grover’s algorithm … we first focus on the circuit shown in part (b) of the figure and analyze”, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key. … compare the result with the (assumed to be known) corresponding ciphertext under the secret target”, page 5, sect. 3.2.1, “We will devote 128 qubits to hold the current internal state.” and page 10, sect. 3.4, “as AES operates on plaintexts/ciphertexts of length 128 we have that ciϵ{0,1}128 throughout … the controls are either 0 or 1 depending on the bits of ci.” [i.e., a number of output qubits of the analysis target ciphertext quantum circuit is equal/equivalent/identical to the number of control bits ci of the phase conversion quantum circuit]).
The motivation to combine Ishii and Grassl is the same as discussed above with respect to claim 17.
Regarding claim 20, as discussed above, Ishii in view of Grassl and Benyuan teaches the circuit of claim 17.
Ishii further discloses wherein the phase inversion quantum circuit inverts the phase of the target qubit when the output qubits of the analysis target … quantum circuit are identical to the comparison target value (see, e.g., paragraphs 47-48, “elements arranged in the first quantum circuit 1 include … an X gate, a CCZ gate … the predetermined operation is an operation of inverting a phase of one target bit among the qubits q0, q1, and q2 according to two control bits among the three qubits q0, q1, and q2.” and 92, “in the quantum circuit 50, … in a case where the two control bits are "1", a Z gate is acted (phase is inverted) on the one target bit.” [i.e., phase inversion quantum circuit inverts a phase a target qubit when output qubits of the analysis target quantum circuit when the output control qubits equal/are identical to the comparison target value of 1]).
Although Ishii substantially discloses the claimed invention, Ishii is not relied on for explicitly disclosing output qubits of the analysis target cipher quantum circuit.
In the same field, analogous art Grassl teaches output qubits of the analysis target cipher quantum circuit (see, e.g., pages 3-4, sects 2-3, “Grover’s algorithm … we first focus on the circuit shown in part (b) of the figure and analyze”, “An essential component needed in Grover’s algorithm is a circuit which on input a candidate key |K> indicates if this key is equal to the secret target key or not. To do so, the idea is to simply encrypt some (fixed) plaintext under the candidate key and compare the result with the (assumed to be known) corresponding ciphertext under the secret target key.” and pages 5-6, sect. 3.2.1, “We will devote 128 qubits to hold the current internal state”, “the number of total qubits required at each step, the actual calculation of computing α-1 fits into 40 qubits total, producing … twenty-four reinitialized qubits as output.” [i.e., an output value/output qubits of the analyze/analysis target ciphertext/cipher quantum circuit]).
The motivation to combine Ishii and Grassl is the same as discussed above with respect to claim 17.
Allowable Subject Matter
Upon overcoming of all the objections and rejections as discussed above in items 7-15, claims 3-4, 11-12 and 19 are objected to as being dependent upon a rejected base claim (i.e., independent claims 1, 9 and 17, respectively), but would be allowable if amended to address the above-noted objections and rejections under 35 U.S.C. 112(b) and 103, and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For example, with regard to dependent claims 3-4, 11-12 and 19, the prior art of record does not anticipate, nor do they render obvious in any reasonable combination to one of ordinary skill in the art at the time of Applicants' invention, the combination of recited limitations of claims 3, 11 and 19 their respective base claims, independent claims 1, 9 and 17, respectively.
As discussed above, Ishii in view of Grassl and Benyuan teaches the method of claim 1, the apparatus of claim 9, and the circuit of claim 17.
Grassl discloses that “the circuit implementation is required to be reversible” and “To realize this round-oriented block cipher as a reversible circuit over the Toffoli gate set, respectively as a quantum circuit over the Clifford+T gate set, we need to take care of the key expansion” and “we obtain a reversible circuit for computing AES” (see, pages 1, 5 and 10, sects 1, 3.2 - “Reversible and quantum circuits to implement AES” and 3.4) and Benyuan discloses that “the line before the Z gate is all required to be used as a line prepared in an overlapped state (including the constraint condition above), dagger (conjugate transpose) operation is performed in the amplifying part of Grover, so that the depth of the dagger line is deeper, and the Grover algorithm needs to use a multi-control quantum logic gate for operating all quantum bits” (see, e.g., page 6).
However, the prior art of record does not anticipate or render obvious the limitations “wherein the dagger quantum circuit is generated by compiling the analysis target cipher quantum circuit to create a Quantum Assembly Language (QASM) and by arranging the QASM in reverse order”, as recited in claims 3, 11 and 19, in combination with limitations of base claims 1, 9 and 17.
The prior art of record also does not anticipate or render obvious the limitations “wherein data qubits and sub-qubits of the dagger quantum circuit have sizes identical to those of the data qubits and the sub-qubits of the analysis target cipher quantum circuit, respectively”, as recited, using respective similar language, in claims 4 and 12, in combination with limitations of base claims 1 and 9.
Conclusion
The prior art made of record, listed on form PTO-892, and not relied upon, is considered pertinent to applicant's disclosure.
The references listed on form PTO-892 are all generally related to techniques, methods and systems for implementing and using quantum computing architectures, circuits and devices to execute quantum algorithms such as Grover’s algorithm.
For example, Ishii (U.S. Patent Application Pub. No. 2024/0169234 A1, hereinafter “Ishii ‘234”)7 discloses that “In the inversion process of the Grover's algorithm, the oracle Uf is applied.”, “The CCZ gate indicates that the Z gate is operated (the phase is inverted) on one target bit when the two control bits are "1". and “in the quantum circuit 50, a combination of the X gate and the CCZ gate indicating a process of applying an oracle is arranged” (see, paragraphs 65, 79 and 82).
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line no(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application.
When responding to this office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of the art disclosed by the reference cited or the objections made. He or she must also show how the amendments avoid such references or objections See 37 CFR 1.111 (c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANDY K BALDWIN whose telephone number is (571)270-5222. The examiner can normally be reached on Mon - Fri 9:00-6:00.
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/RANDALL K. BALDWIN/Primary Examiner, Art Unit 2125
1 Ishii is a continuation of PCT application number PCT/JP2021/048573, filed on 12/27/2021, which is prior to the earliest effective filing data of the instant application, 8/30/2022. Therefore it constitutes prior art under 35 U.S.C. 102(a)(2)
2 As indicated in the section 112(b) rejection of this claim above, “analyzing data qubits and sub-qubits that are used for a design of an analysis target … quantum circuit configured to implement an analysis target … based on the analysis target … quantum circuit” has been interpreted as analyzing data qubits and sub-qubits, designing, based at least in part on the analyzing, an analysis target … quantum circuit, wherein the analysis target … quantum circuit is configured to implement an analysis target.
3 As indicated in the section 112(b) rejection of this claim above, “allocating the data qubits and the sub-qubits” has been interpreted as allocating any data values or resources, such as, but not limited to memory, storage, processing or other hardware resources, to or for “the data qubits and the sub-qubits”.
4 As noted in the objection to this claim above, it appears the recitation of “a Grover oracle quantum circuit” should read “[[an]] the Grover oracle quantum circuit.”
5 As noted in the objection to this claim above, it appears the recitation of “an oracle quantum circuit” should read “[[an]] the Grover oracle quantum circuit.”
6 As noted above in the objections to these claims, it appears “a multiple-controlled Toffoli gate” should read “[[a]] the multiple-controlled Toffoli gate.”
7 Ishii ‘234 is a continuation of PCT application number PCT/JP21/30184, filed on 8/18/2021, which is prior to the earliest effective filing data of the instant application, 8/30/2022. Therefore it constitutes prior art under 35 U.S.C. 102(a)(2).