Office Action Predictor
Last updated: April 15, 2026
Application No. 18/301,182

TEST EQUIPMENT HUB

Final Rejection §102§103
Filed
Apr 14, 2023
Examiner
UNELUS, ERNEST
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Future Dial, INC.
OA Round
4 (Final)
77%
Grant Probability
Favorable
5-6
OA Rounds
3y 1m
To Grant
99%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
417 granted / 540 resolved
+22.2% vs TC avg
Strong +39% interview lift
Without
With
+38.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
29 currently pending
Career history
569
Total Applications
across all art units

Statute-Specific Performance

§101
5.8%
-34.2% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
45.9%
+5.9% vs TC avg
§112
3.5%
-36.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 540 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . RESPONSE TO AMENDMENT Claim rejections based on prior art Applicant's arguments filed on 01/07/2026 with respect to claims 1-20 have been fully considered but are moot in view of newly cited reference. OBJECTIONS TO THE CLAIMS Claims 1-20 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention. As per claim 1, in line 3, the phrase ‘USB (universal serial bus)’ should be rewritten as ‘universal serial bus (USB)’. This objection is applied to all acronyms in the other independent claims. Correction is needed. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 1. Claims 1, 8 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Quach et al. (US pub. # 2016/0170931), hereinafter, “Quach”. At the outset, Applicant is reminded that claims subject to examination will be given their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023,1027-28 (Fed. Cir. 1997). With this in mind, the discussion will focus on how the terms and relationships between the terms in the claims are met by the references. 2. As per claims 1, 8 and 16, Quach discloses a device (console server 200 of fig. 3, as discloses in paragraph 0038) comprising: a housing (serial cards 220, 230 and 240 combined with circuit board 205 of fig. 3); and a plurality of USB (universal serial bus) ports (USB ports such as 335-350 inside the serial cards 220 and 240) configured on the housing (see figs. 3 and 4); wherein the plurality of USB ports are configured as a plurality of groups, each group in the plurality of groups including two USB ports in the plurality of USB ports (see fig. 4); wherein the housing is configured to receive a plurality of connectors (a respective connector of each serial card 220 and serial card 240 that plugs into each respective connector of the PCIE bus 260, as shown in fig. 3. See also paragraph 0039, which discloses “one or more serial cards 220, 230 and 240 may be plugged into connectors of the PCIE bus 260, placing the serial cards in communication with the processor 212 of the main circuit board”) from a PCI (peripheral communication interface) bridge (a respective connector of the PCIE bus 260 for a respective serial card; see paragraph 0039); wherein the device is configured to connect each of the plurality of connectors to a respective group of USB ports among the plurality of groups (see paragraphs 0038 and 0039 and figs. 3 and 4). Claim Rejections - 35 USC § 103 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claim 2-7, 9-15 and 17-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Quach et al. (US pub. # 2016/0170931), hereinafter, “Quach”, in view of Numamoto et al. (US pub. # 2013/0013842), hereinafter, “Numamoto”. 5. As per claims 2, 9 and 18, Quach discloses “The device of Claim 1” [See rejection to claim 1 above], but fails to expressly disclose wherein each of the plurality of USB ports has an average bandwidth of 240 megabits per second (Mbps). Numamoto discloses wherein each of the plurality of USB ports has an average bandwidth of 240 megabits per second (Mbps) (see paragraph 0011). It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to modified Numamoto’s controller and transfer speed control system that enables data transfer between buses with different standards such as PCI Express and USB, and particularly to a controller and a transfer speed thereof that are suitable for the case in which both standards have a plurality of transfer speeds, into Quach’s monitoring server that provides universal serial bus (USB) connectivity between the monitoring server and devices connected to the monitoring server, for the benefits of having a transfer speed switching unit besides a transfer data converting unit that mutually converts transfer data from a USB device and transfer data from a PCI Express bus. 6. As per claims 3, 10 and 19, the combination of Quach and Numamoto discloses “The device of Claim 1” [See rejection to claim 1 above], further comprising a plurality of outputs, wherein the plurality of outputs is configured to display a status indicator for a respective one of the plurality of USB ports (see paragraph 0035 of Quach). 7. As per claims 4, 11 and 20, the combination of Quach and Numamoto discloses “The device of Claim 2” [See rejection to claim 2 above], wherein the plurality of USB ports comprises 40 USB ports (see paragraphs 033 and 0040 of Quach). 8. As per claims 5, 12 and 13, the combination of Quach and Numamoto discloses “The device of Claim 4” [See rejection to claim 4 above], wherein the plurality of connectors comprise 20 connectors (see paragraphs 033 and 0040 of Quach) from a plurality of PCI bridges (respective connectors of the PCIE bus 260 for each respective serial card; see paragraph 0039 of Quach). 9. As per claims 6 and 14, the combination of Quach and Numamoto discloses “The device of Claim 5” [See rejection to claim 5 above], wherein the plurality of connectors include 4 connectors (see fig. 4 of Quach) per PCI bridge among the plurality of PCI bridges (see paragraphs 033 and 0040 of Quach). 10. As per claims 7, 15 and 17, the combination of Quach and Numamoto discloses “The device of Claim 6” [See rejection to claim 6 above], wherein the plurality of connectors are configured to provide an average bandwidth of 480 Mbps (see paragraph 0011 of Numamoto). CLOSING COMMENTS Conclusion a. STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): a(1) CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-20 have received a final action on the merits. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. b. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM. IMPORTANT NOTE If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /Ernest Unelus/ Primary Examiner Art Unit 2181
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Prosecution Timeline

Apr 14, 2023
Application Filed
Jul 12, 2024
Non-Final Rejection — §102, §103
Oct 18, 2024
Response Filed
Nov 22, 2024
Final Rejection — §102, §103
Jan 27, 2025
Response after Non-Final Action
Feb 25, 2025
Request for Continued Examination
Feb 27, 2025
Response after Non-Final Action
Feb 27, 2025
Response after Non-Final Action
Oct 03, 2025
Non-Final Rejection — §102, §103
Jan 07, 2026
Response Filed
Jan 31, 2026
Final Rejection — §102, §103
Apr 06, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
77%
Grant Probability
99%
With Interview (+38.6%)
3y 1m
Median Time to Grant
High
PTA Risk
Based on 540 resolved cases by this examiner. Grant probability derived from career allow rate.

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