DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1, 3-12, 14-17 and 19-23 are pending.
3. This office action is in response to the Applicant’s communication filed 06/23/2025 in response to PTO Office Action mailed 03/27/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Response to Arguments
4. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited previously presented prior art, Jenkins et al. (US Pub. No. 2009/0106476 A1 hereinafter “Jenkins” – IDS Submission), as necessitated by the amended independent claims disclosing “simultaneously sending, by the host, the first data and the second data to the PCIe device through the first PCIe link and the second PCIe links respectively” (Jenkins – par. [0022]).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 1, 3, 4, 12, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins et al. (US Pub. No. 2009/0106476 A1 hereinafter “Jenkins” – IDS Submission) in view of Chen et al. (US Pub. No. 2019/0052617 A1 hereinafter “Chen”), and further in view of Tsu (US Patent No. 7,705,850 B1 hereinafter “Tsu”).
Referring to claim 1, Jenkins discloses a data processing system comprising a host (Jenkins – Fig.1 shows a component A; Fig. 3 shows a PCIe component 100A.) and a peripheral component interconnect express (PCIe) device (Jenkins – Fig.1 shows a component B; Par. [0030] discloses a second component (see Fig. 1) similar to component 100A.), the PCIe device establishing a first PCIe link to the host through a first interface (Jenkins – Fig. 3, see xK PCIe link) and a second PCIe link to the host through a second interface (Jenkins – Fig. 3, see xN PCIe link), wherein the data processing system to perform operations comprising:
simultaneously sending (Jenkins – par. [0022] discloses The designations xK (by K) or xN (by N) indicate the number of lanes in a link. An xX lane therefore includes xX transmit lanes and xX receive lanes. Lanes in a link transmit data in parallel. It is implied that the data is sent simultaneously on both links since the lanes within each link transmits data in parallel.), by the host, first data (Jenkins – par. [0035] discloses DLLPs are transmitted/received through the xK PCI Express Link at the lower data rate.) and the second data to the PCIe device through the first PCIe link and the second PCIe link, respectfully (Jenkins – par. [0035] discloses TLPs are transmitted/received through the xN PCI Express Link of PORT 1 at the higher data rate.); and
receiving, by the PCIe device, the first data through the first PCIe link (Jenkins – par. [0035] discloses DLLPs are transmitted/received through the xK PCI Express Link at the lower data rate.) and the second data through the second PCIe link (Jenkins – par. [0035] discloses TLPs are transmitted/received through the xN PCI Express Link of PORT 1 at the higher data rate.), wherein both the first PCIe link and the second PCIe link are in an active state during data transmission (Jenkins – par. [0033, 0043; claims 7, 12] disclose the lanes of the PCIe links being in an active state during data transmission.).
Jenkins fails to explicitly disclose wherein the host and the PCIe device comprise at least one processor and at least one memory coupled to the at least one processor, and the at least one memory stores programming instructions for execution by the at least one processor to cause the data processing system to perform operations comprising: splitting, by the host, to-be-transmitted data to be sent to the PCIe device into first data through the first PCIe link and second data through the second PCIe link based at least on a threshold, wherein the to-be-transmitted data is a transaction layer packet (TLP), and the threshold is determined based on a first parameter associated with the first PCIe link and a second parameter associated with the second PCIe link.
Chen discloses wherein the host and the PCIe device comprise at least one processor and at least one memory coupled to the at least one processor, and the at least one memory stores programming instructions for execution by the at least one processor to cause the data processing system to perform operations (Chen – Fig. 8 & par. [0060] disclose a host 510 comprising a processor 805 and a memory 810; a PCIe device 505 comprising a processor 830 and a memory 855. Par. [0066] discloses the host may include one or more microprocessors (e.g., 805), computer memory (e.g., 810), to implement system software (e.g., 815).); wherein the to-be-transmitted data is a transaction layer packet (TLP) (Chen – Par. [0044] discloses exchanging Transaction Layer Packets (TLPs) between two components on a link.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Chen’s teachings with Jenkins’ techniques for providing computer security enhancements and better energy efficiency and energy conservation (Chen – par. [0022]).
Jenkins and Chen fail to explicitly disclose splitting, by the host, to-be-transmitted data to be sent to the PCIe device into first data through the first PCIe link and second data through the second PCIe link based at least on a threshold, wherein the to-be-transmitted data is a transaction layer packet (TLP), and the threshold is determined based on a first parameter associated with the first PCIe link and a second parameter associated with the second PCIe link.
Tsu discloses splitting, by the host, to-be-transmitted data to be sent to the PCIe device into first data through the first PCIe link and second data through the second PCIe link (Tsu – Fig. 5 & col. 3, lines 51-59 disclose endpoint device 220 in connection with a read request that is issued as a first read request PCIe packet communicated through PCIe interface 222 and a second read request PCIe packet communicated through PCIe interface 224. At step 502, endpoint device 220 sends the first read request PCIe packet over PCIe interface 222. Then, at step 504, endpoint device 220 sends the second read request PCIe packet over PCIe interface 224. Fig. 3 shows Controller 310 that will receive the first and second read requests via PCIe interfaces 210 and 212, respectfully.) based at least on a threshold, and the threshold is determined based on a first parameter associated with the first PCIe link and a second parameter associated with the second PCIe link (Tsu – Col. 1, lines 46-48 discloses optimizing the bus utilization of the PCIe link can increase the PCIe bus throughput efficiency, but the efficiency can be increased only up to a certain limit.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Tsu’s teachings with Jenkins and Chen’s techniques for providing a computer system that increases the PCIe bandwidth available to an endpoint device. (Tsu –Col. 1, lines 54-56).
Referring to claim 3, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, wherein the operations further comprise: determining, by the PCIe device, to-be-transmitted data to be requested from the host (Jenkins – Fig. 8 & par. [0037, 0052] disclose in step 250 it is determined if the information to be transmitted by one of the two single-port/multiple link linked PCI Express components is of an ordered set (first framing class), or a DLLP or TLP packet (second framing class).); and separately requesting, by the PCIe device, the first data and the second data from the host based on the to-be-transmitted data (Jenkins – Fig. 8 & par. [0043, 0052] disclose if the information is a packet, the method proceeds to step 265. If in step 265, the packet type is DLLP then in step 270 the DLLP is transmitted on the narrow link. If in step 265, the packet type is TLP then in step 277 the TLP is transmitted on the wide link.).
Referring to claim 4, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, wherein the host splits the to-be-transmitted data into the first data and the second data based on a link state of the first PCIe link and a link state of the second PCIe link (Jenkins – Fig. 8 & par. [0043, 0052] disclose if the information is a packet, the method proceeds to step 265. If in step 265, the packet type is DLLP then in step 270 the DLLP is transmitted on the narrow link. If in step 265, the packet type is TLP then in step 277 the TLP is transmitted on the wide link.).
Referring to claims 12 and 17, Note the rejections of claim 1 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 14, Note the rejections of claim 4 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
7. Claims 5, 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Bhandaru et al. (US Pub. No. 2020/0117642 A1 hereinafter “Bhandaru”).
Referring to claim 5, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the first data and the second data have the same size.
Bhandaru discloses the first data and the second data have the same size (Bhandaru –Par. [0027] discloses the data object 310 may be separated or divided into different data blocks 315 that are of the same size.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Bhandaru’s teachings with Jenkins, Chen and Tsu’s techniques for the benefit of determining an optimal data size for a data deduplication operation (Bhandaru – par. [0012]).
Referring to claims 22 and 23, Note the rejections of claim 5 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
8. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Monji et al. (US Pub. No. 2017/0075828 A1 hereinafter “Monji”).
Referring to claim 6, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the operations further comprise: sending, by the host, the first data to the PCIe device through the first PCIe link by using direct memory access (DMA) and the second data to the PCIe device through the second PCIe link by using the DMA.
Monji discloses sending, by the host, the data to the PCIe device through the first PCIe link by using direct memory access (DMA) and the data to the PCIe device through the second PCIe link by using the DMA (Monji – Figs. 1, 2 & par. [0065] disclose the server apparatus 100 having a DMA controller 240 within an interface device 200 that transfers the write data stored in the server-side storage area, to the storage-side storage area of the storage apparatus 300 via a first PCIe bus and a second PCIe bus).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Monji’s teachings with Jenkins, Chen and Tsu’s techniques for starting a host computer and a high-speed data transfer achieved by NVMe to be both realized (Monji – Abstract).
9. Claims 7, 15, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Adachi (US Pub. No. 2008/0263307 A1 hereinafter “Adachi”).
Referring to claim 7, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the operations further comprise: before splitting the to-be-transmitted data into the first data and the second data, determining, by the host, that a size of the to-be-transmitted data exceeds a preset value.
Adachi discloses before splitting the to-be-transmitted data into the first data and the second data, determining, by the host, that a size of the to-be-transmitted data exceeds a preset value (Adachi – Par. [0068] discloses in the case where there is a desire to transfer data that exceeds such a size, for example, the host system 22 in related art, which generates the link list while taking account of the restrictions, needs to generate the link list such that the data will be divided into parts for data exchange.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Adachi’s teachings with Jenkins, Chen and Tsu’s techniques for making it possible to reduce processing to be performed in the host at the time of data transfer (Adachi – par. [0012]).
Referring to claims 15 and 19, Note the rejections of claim 7 above. The Instant Claims recite substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 20, Jenkins, Chen and Tsu disclose the computer apparatus of claim 17, however, fail to explicitly disclose wherein the wherein the operations further comprise: receiving a data processing task sent by a user, wherein data corresponding to the data processing task comprises the first data and the second data.
Adachi discloses receiving a data processing task sent by a user (Adachi – Par. [0040] discloses the host CPU 61 controls an operation of the host system 22. Based on a user operation inputted via the operation input section (not shown), for example, the host CPU 61 is capable of generating the command and writing the command to the register 43 in the storage system 21 via the storage I/F 23. Examples of such commands include: a command for writing data stored in the host memory 62 to the storage memory 48 in the storage system 21.), wherein data corresponding to the data processing task comprises the first data and the second data (Adachi – Par. [0068] discloses in the case where there is a desire to transfer data that exceeds such a size, for example, the host system 22 in related art, which generates the link list while taking account of the restrictions, needs to generate the link list such that the data will be divided into parts for data exchange.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Adachi’s teachings with Jenkins, Chen and Tsu’s techniques for making it possible to reduce processing to be performed in the host at the time of data transfer (Adachi – par. [0012]).
10. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Xu et al. (US Pub. No. 2013/0042136 A1 hereinafter “Xu”).
Referring to claim 8, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, wherein the operations further comprise: determining, by the host, that the first data and the second data are sent to the PCIe device (Jenkins – Fig. 8 & par. [0037, 0043, 0052] disclose in step 250 it is determined if the information to be transmitted by one of the two single-port/multiple link linked PCI Express components is of an ordered set (first framing class), or a DLLP or TLP packet (second framing class). If the information is a packet, the method proceeds to step 265. If in step 265, the packet type is DLLP then in step 270 the DLLP is transmitted on the narrow link. If in step 265, the packet type is TLP then in step 277 the TLP is transmitted on the wide link.); however, fail to explicitly disclose sending, by the host, a synchronization signal to the PCIe device.
Xu discloses sending, by the host, a synchronization signal to the PCIe device (Xu – Fig. 5 & par. [0049] disclose a clock source device 51, configured to send a time synchronization signal to a PCIE device.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Xu’s teachings with Jenkins, Chen and Tsu’s techniques for the benefit of the reliability and security of the system are increased; the cost of the system is lowered; and the maintenance thereof is easy (Xu – par. [0044]).
11. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Johnson et al. (US Pub. No. 2018/0129439 A1 hereinafter “Johnson”).
Referring to claim 9, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the operations further comprise: after determining that the first data is written, adjusting, by the PCIe device, a pointer to an end of storage space, wherein the storage space is in the PCIe device and stores the first data.
Johnson discloses after determining that the first data is written, adjusting, by the storage device, a pointer to an end of storage space, wherein the storage space is in the storage device and stores the first data (Johnson – Par. [0143] discloses a drive 100 may be configured so that all data stored thereon is write protected, in which case the device controller 130 may simply write content sequentially through the drive, maintaining a pointer to the next location to write content. In this case, when the pointer reaches the end of the available space on the storage media 110, any additional requests to write will be returned as errors.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Johnson’s teachings with Jenkins, Chen and Tsu’s techniques for providing instruction to refuse a delete request in accordance to the storage information and providing direction to store the storage information at a remote location (Johnson – par. [0005]).
12. Claim 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, further in view of Nandlall et al. (US Pub. No. 2012/0072481 A1 hereinafter “Nandlall”), and further in view of Adachi.
Referring to claim 10, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, wherein the operations further comprise: before sending the first data to the PCIe device through the first PCIe link (Jenkins – Fig. 8 & par. [0037, 0052] disclose in step 250 it is determined if the information to be transmitted by one of the two single-port/multiple link linked PCI Express components is of an ordered set (first framing class), or a DLLP or TLP packet (second framing class). Par. [0035] discloses DLLPs are transmitted/received through the xK PCI Express Link at the lower data rate.); however, fail to explicitly disclose wherein the data processing system is applied to a cloud phone scenario, and wherein the operations further comprise: before sending the first data to the PCIe device through the first PCIe link, receiving, by the host, a data processing task sent by a user, wherein data corresponding to the data processing task comprises the first data and the second data.
Nandlall discloses the data processing system is applied to a cloud phone scenario (Nandlall – Par. [0030] discloses The cloud phone application may be a software module having various distributed data processing functionalities.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Nandlall’s teachings with Jenkins, Chen and Tsu’s techniques for devising a methodology and a long-term solution to address the growing demands--on handset processing power and network communication resources--of modern applications designed for mobile usage, without the need to place any usage or monetary restrictions on the users of mobile handsets and without sacrificing advanced functionalities afforded by the applications (Nandlall – par. [0009]).
Jenkins, Chen, Tsu and Nandlall fail to explicitly disclose wherein the operations further comprise: before sending the first data to the PCIe device through the first PCIe link, receiving, by the host, a data processing task sent by a user, wherein data corresponding to the data processing task comprises the first data and the second data.
Adachi discloses receiving, by the host, a data processing task sent by a user (Adachi – Par. [0040] discloses the host CPU 61 controls an operation of the host system 22. Based on a user operation inputted via the operation input section (not shown), for example, the host CPU 61 is capable of generating the command and writing the command to the register 43 in the storage system 21 via the storage I/F 23. Examples of such commands include: a command for writing data stored in the host memory 62 to the storage memory 48 in the storage system 21.), wherein data corresponding to the data processing task comprises the first data and the second data (Adachi – Par. [0068] discloses in the case where there is a desire to transfer data that exceeds such a size, for example, the host system 22 in related art, which generates the link list while taking account of the restrictions, needs to generate the link list such that the data will be divided into parts for data exchange.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Adachi’s teachings with Jenkins, Chen, Tsu and Nandlall’s techniques for making it possible to reduce processing to be performed in the host at the time of data transfer (Adachi – par. [0012]).
Referring to claim 16, Note the rejections of claim 10 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
13. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Shi et al. (US Pub. No. 2020/0050924 A1 hereinafter “Shi”).
Referring to claim 11, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the data processing system is applied to an artificial intelligence (AI) scenario, and wherein the operations further comprise: before sending the first data to the PCIe device through the first PCIe link, receiving, by the host, an AI task, wherein data corresponding to the AI task comprises the first data and the second data.
Shi discloses the data processing system is applied to an artificial intelligence (AI) scenario, and wherein the operations further comprise: before sending the first data to the PCIe device through the first PCIe link, receiving, by the host, an AI task, wherein data corresponding to the AI task comprises the first data and the second data (Shi – Par. [0045, 0086] discloses the artificial intelligence chip (AI chip) 106, also referred to as an AI accelerator or computing card, i.e., a module specially configured to process a large amount of computational tasks in artificial intelligence applications. For example, a CPU (Central Processing Unit) of the server 105 may transmit acquired training data and/or test data to the artificial intelligence chip 106 by a PCIE (Peripheral Component Interconnect Express). A user may send a model training instruction to the server 105 using the terminal 101. After receiving the instruction, the CPU in the server 105 may acquire training data and model data from a local memory, and transmit the acquired data to the artificial intelligence chip A.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Shi’s teachings with Jenkins, Chen and Tsu’s techniques for presenting a data processing method and apparatus for a neural network (Shi – par. [0005]).
14. Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Jenkins in view of Chen and Tsu, and further in view of Benisty et al. (US Pub. No. 2019/0278485 A1 hereinafter “Benisty”).
Referring to claim 21, Jenkins, Chen and Tsu disclose the data processing system according to claim 1, however, fail to explicitly disclose wherein the first parameter comprises a maximum value of a TLP payload of the first PCIe link, and the second parameter comprises a maximum value of a TLP payload of the second PCIe link.
the parameter comprises a maximum value of a TLP payload of the PCIe link (Benisty – Par. [0039] discloses when a TLP is sent between a source PCIe device and a destination PCIe device, the TLPs are sent with a data payload size equal to or less than the lowest maximum TLP payload size setting along the TLPs' path.).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include Benisty’s teachings with Jenkins, Chen and Tsu’s techniques for providing a storage device with reduced latency and a method of accessing data by a storage device with reduced latency (Benisty – par. [0003]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DAYTON LEWIS-TAYLOR/Examiner, Art Unit 2181
/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181
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