DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of invention I in the reply filed on 5/27/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites “is likely…than.” It is unclear what the limitation requires; however, it appears that the limitation should read “is more likely…than.” The claim will be interpreted to read “is more likely…than” for purposes of examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8, and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,468,853 (Kondo).
For claim 1, Kondo teaches a light emitting component (fig. 5, 7 and 25) comprising:
a substrate(fig. 5, 7, and 25, label 80);
a plurality of light emitting elements that are provided on the substrate and respectively have light emission regions (fig. 5, LD1-LD128; fig. 7, LD; fig. 25, VCSEL); and
a plurality of thyristors that are turned on to cause the light emission regions of the respective light emitting elements to emit light, or that increase amounts of emitted light of the light emission regions (fig. 5, S1-S128; fig. 7 and 25, s),
wherein the light emitting elements absorb light emitted from a corresponding thyristor among the plurality of thyristors (the well layer of light emitting layer 82 may be GaAs [c. 3, l. 39-40] while the thyristor gate layers are AlGaAs [c. 31, l. 1-8] and given the inherent band gaps for GaAs and AlGaAs [see fig. 16 of instant application] the light emitting elements inherently absorb light from the corresponding thyristor due to their inherent band gaps).
For claim 2, Kondo teaches the light emitting elements have a semiconductor layer having a band gap energy smaller than a band gap energy corresponding to light emitted from the thyristors (fig. 25, DBRs 81a and 81c include layers with Al0.2Ga0.8As having smaller bandgap than the light emitted by the thyristor due to a lower Al content).
For claim 3, Kondo teaches the thyristors include a gate layer formed of a semiconductor including Al (c. 31, l. 1-8), and wherein the semiconductor layer of the light emitting elements includes Al (c. 40, l. 58-67) and a content ratio of Al of the semiconductor layer is equal to or less than a content ratio of Al of the gate layer (0.2 < 0.9).
For claims 5 and 6, Kondo teaches assuming that λ is an emission wavelength due to the light emission regions and n is a refractive index of the semiconductor layer, the semiconductor layer of the light emitting elements has a thickness of (λ /4n) x 0.4 or more and (λ /4n) x 1.2 or less (c. 40, l. 58-64).
For claim 8, Kondo teaches the plurality of thyristors are laminated on a side opposite to the substrate with respect to the plurality of light emitting elements (fig. 7 and 25; thyristor S is on the opposite side as substrate 80 with respect to the light emitting elements LD/VCSEL).
For claim 10, Kondo teaches the light emitting elements each have a lower semiconductor layer laminated on the substrate (fig. 25, 81; c. 40, l.58-61; Al0.2Ga0.8As layer), a light emission layer laminated on the lower semiconductor layer (fig. 25, 82), and an upper semiconductor layer laminated on the light emission layer (fig. 25, 83; . 40, l.58-61; Al0.9Ga0.1As layer), and the lower semiconductor layer is more likely to absorb the light emitted from the thyristors than the upper semiconductor layer (inherent due to the different Al contents).
For claim 11, Kondo teaches the light emitting elements include an absorptive layer that absorbs light emitted from the thyristors (col. 40, l. 58-67; Al0.2Ga0.8As will absorb light from the Al0.9Ga0.1As thyristor).
Kondo further teaches the light emitting elements each have a film thickness greater than an emission wavelength (col. 40, l. 63-67; there are minimally 4 quarter wavelength DBR layers and the emission).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 10,468,853 (Kondo).
For claim 4, Kondo teaches the gate layer of the thyristors has a content ratio which may be changed in the range 0 to 1 (c. 3, l. 1-8) but does not explicitly state an Al of less than 30%. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to determine workable Al percentages including less than 30% in Kondo’s range between 0 and 1, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 7, Kondo teaches assuming that λ is an emission wavelength due to the light emission regions and n is a refractive index of the semiconductor layer, the semiconductor layer of the light emitting elements has a thickness of (λ /4n) x 0.4 or more and (λ /4n) x 1.2 or less (c. 40, l. 58-64).
For claim 10, Kondo teaches the light emitting elements each have a lower semiconductor layer laminated on the substrate (fig. 25, 81; c. 40, l.58-61; Al0.2Ga0.8As layer), a light emission layer laminated on the lower semiconductor layer (fig. 25, 82), and an upper semiconductor layer laminated on the light emission layer (fig. 25, 83; . 40, l.58-61; Al0.9Ga0.1As layer).
If it is determined that the lower semiconductor layer is not inherently more likely to absorb the light emitted from the thyristors than the upper semiconductor layer. Kondo teaches the Al content of the gate layers as well as the two DBR layers may be varied in the range 0 to 1 (c. 31, l. 1-8, and c. 40, l. 58-67).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to determine workable Al percentages for the gate layers and the lower and upper semiconductor layer such that the lower semiconductor layer is more likely to absorb the light emitted from the thyristors than the upper semiconductor layer, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 10,468,853 (Kondo)in view of US 6,014,400 (Kobayashi).
For claim 9, Kondo teaches the light emitting elements each have a first region corresponding to one thyristor among the plurality of thyristors (fig. 25; region under thyristor S). Kondo does not teach a second region corresponding to another thyristor adjacent to the one thyristor, and at least a part of the first region or the second region is continuous.
However, Kobayashi teaches a VCSEL array (fig. 12) Where each light emitting element has a first region (fig. 12, each element has a region corresponding to its mesa 150) and a second region corresponding to another light emitting elements first region (fig. 12, DBR 120 exits under the mesa 150 in the first region of a given light emitting element and extends to a second region that includes other light emitting elements with their own mesas) and at least part of the first region and second region are continuous in order to provide the lower DBR for the light emitting elements of the array (fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a continuous lower DBR under the plurality of light emitting elements as taught by Kobayashi in order to provide the lower DBR for the light emitting elements of Kondo such that the lower DBR of each VCSEL exists in a first region under the VCSEL and thyristor (fig. 25) and continuously extends to a second region corresponding to an adjacent VCSEL and its thyristor. The combination has the additional advantage of not requiring etching through the lower DBR.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30.
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/Michael Carter/ Primary Examiner, Art Unit 2828