DETAILED ACTION
This action is responsive to the following: the amendments and remarks made in amendment filed on June 27, 2025 and the information disclosure statement filed on October 1, 2025.
Claims 1-8, 10-14, and 16-20 are pending. Claims 1, 8, and 14 are independent. Claims 9 and 15 are cancelled by applicant.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 1, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendment to claims filed on June 27, 2025 have been entered. Claims 1-8, 10-14, and 16-20 remain pending. Claims 9 and 15 are cancelled by the applicant. The amendments to claims overcome the objections set forth in the previous non-final office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-14, and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Sinangil et al (US 9,208,900 B2 hereafter “Sinangil”) in view of Zimmer et al (US 20140160871 A1 hereafter “Zimmer”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitation from the specification.
Regarding independent claims 1 and 14, Sinangil and Zimmer disclose an integrated circuit (Fig. 7A: but also see Figs. 1-6, 8-9), comprising:
a semiconductor substrate (see for example in Fig. 1 shows a semiconductor memory device and related in Figs. 2-9); integrated circuitry on the semiconductor substrate, wherein the integrated circuitry includes:
a static random access memory (SRAM) cell array (e.g., sram cell array; in Figs. 1A and 1B related in Figs. 2-9);
a first assist circuit (Fig. 7A: 200) and a differently configured second assist circuit (Fig. 7A: 720), wherein the first assist circuit (Fig. 7A: 200) is configured to apply a voltage boost to an access line (Fig. 7A: word line 704) utilized to access the SRAM cell array and the second assist circuit (Fig. 7A: 720) is configured to apply a voltage boost to a voltage supply rail (Fig. 7A: column supply voltage 722) of the SRAM cell array; and
a common boost capacitor (see Fig. 4B; but also see Fig. 7A: Boost Cam 500 as related to Fig. 5: Boost Cam 500, as explained in col. 10, lines 32-38) coupled to selectively and concurrently provide a voltage boost to both the access line (see Fig. 7A: 704) and the power rail (Fig. 7A: 722) via the first and second assist circuits, respectively.
However, Sinangil fails to teach wherein the second assist circuit comprises a transistor having a source coupled to the voltage supply rail and a drain coupled to the common boost capacitor.
Zimmer teaches wherein the second assist circuit (Fig. 2A: 220) comprises a transistor (Fig. 2A: 233) having a source coupled to the voltage supply rail (Fig. 2A: Column Supply 221) and a drain coupled to the common boost capacitor (Fig. 2A: 240).
Zimmer teaches collapsing the supply voltage using the supply collapse circuit in combination with a negative boost on the bitlines allow for a lower energy write operation that does not lose reliability. Thus, applying these teachings to Sinangil would have represented an obvious improvement on the write circuit disclosed with word line boost.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Zimmer to the teachings of Sinangil to produce a write access circuit with a transistor with source coupled to the voltage supply rail of the cells and drain coupled to common boost capacitor.
Regarding independent claim 8, Sinangil and Zimmer disclose a method, comprising: providing an integrated circuit (Fig. 7A: but also see Figs. 1-6, 8-9), including integrated circuitry on the semiconductor substrate (see for example in Fig. 1 shows a semiconductor memory device and related in Figs. 2-9); wherein the integrated circuitry includes:
a static random access memory (SRAM) cell array (Figs. 1A: 100, but also see Fig 1B: 128);
a first assist circuit (Fig. 7A: 200) and a differently configured second assist circuit (Fig. 7A: 720), wherein the first assist circuit (Fig. 7A: 200) is configured to apply a voltage boost to an access line (Fig. 7A: word line 704) utilized to access the SRAM cell array and the second assist circuit (Fig. 7A: 720) is configured to apply a voltage boost to a voltage supply rail (Fig. 7A: column supply voltage 722) of the SRAM cell array; and
a common boost capacitor (see Fig. 4B; but also see Fig. 7A: Boost Cam 500 as related to Fig. 5: Boost Cam 500, as explained in col. 10, lines 32-38) coupled to selectively and concurrently provide a voltage boost to both the access line (see Fig. 7A: 704) and the power rail (Fig. 7A: 722) via the first and second assist circuits, respectively.
and setting one or more control signals (Fig. 5: 506 Boost Level Signal, but also see Fig 7A: 500 Boost CAM) to cause a boost voltage on the common boost capacitor to be concurrently applied to the access line via the first assist circuit and to the voltage supply rail via the second assist circuit.
However, Sinangil fails to teach wherein the second assist circuit comprises a transistor having a source coupled to the voltage supply rail and a drain coupled to the common boost capacitor.
Zimmer teaches wherein the second assist circuit (Fig. 2A: 220) comprises a transistor (Fig. 2A: 233) having a source coupled to the voltage supply rail (Fig. 2A: Column Supply 221) and a drain coupled to the common boost capacitor (Fig. 2A: 240).
Zimmer teaches collapsing the supply voltage using the supply collapse circuit in combination with a negative boost on the bitlines allow for a lower energy write operation that does not lose reliability. Thus, applying these teachings to Sinangil would have represented an obvious improvement on the write circuit disclosed with word line boost.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Zimmer to the teachings of Sinangil to produce a write access circuit with a transistor with source coupled to the voltage supply rail of the cells and drain coupled to common boost capacitor.
Regarding Claim 2, Sinangil and Zimmer disclose the limitations of Claim 1. Zimmer further discloses the second assist circuit (Fig. 2A: 220) further comprises another transistor (Fig. 2A: 231) having another drain coupled to both the source of the transistor (Fig. 2A: 233) and the voltage supply rail (Fig. 2A: Column Supply 221); and
the another transistor (Fig. 2A: 231) comprises another source coupled to a supply voltage source (Fig. 2A: shows the symbol for a supply voltage source at the source of element 231).
Regarding claims 3, 10, and 16, Sinangil and Zimmer disclose wherein: the access line (Fig. 7A: 704) comprises a wordline of the SRAM cell array.
Regarding claims 4, 11, and 17, Sinangil and Zimmer disclose wherein: the voltage supply rail comprises an upper voltage supply rail of the SRAM cell array (Fig. 7A: 722 Column Supply Voltage).
Regarding claims 5 and 18, Sinangil and Zimmer disclose wherein: the common boost capacitor is a first boost capacitor providing a positive voltage boost (Fig. 4A: 404, but also see Fig. 4B: 404); the integrated circuitry further includes: a second boost capacitor providing a negative voltage boost (Figs. 3A: 318); and a third assist circuit (Fig. 7A: 300 Bitline Boost Sub-Circuit) coupled to the second boost capacitor and further coupled to selectively apply the negative voltage boost to a bitline of the SRAM cell array (Fig. 3A:318, but also see Fig. 3B:319).
Regarding claim 12, Sinangil and Zimmer disclose wherein: the common boost capacitor is a first boost capacitor providing a positive voltage boost(Fig. 2A: 216, but also see Fig. 4A: 404); the integrated circuitry further includes: a second boost capacitor providing a negative voltage boost(Fig. 3A: 318); a third assist circuit coupled (Fig. 3A: 300) to the second boost capacitor and further coupled to selectively apply the negative voltage boost to a bitline of the SRAM cell array;
and the method further includes applying the negative voltage boost to the bitline via the third assist circuit concurrently with the positive voltage boost provided by the first boost capacitor (Fig. 7A: 500 Boost CAM).
Regarding claim 6 and 19, Sinangil and Zimmer disclose wherein: the integrated circuit of Claim 1, further comprising a controller (Fig. 7A:502 Address) coupled to the first and second assist circuit (Fig. 7A: 500 Boost CAM) and configured to control selective application of the voltage boost to the access line and to the voltage supply rail.
Regarding claim 7 and 20, Sinangil and Zimmer disclose the integrated circuit of Claim 1, wherein: the boost capacitor includes a first plate and a second plate (Fig 4A: 404);
the boost capacitor is a component of a boost circuit including: a boost control input coupled to receive a boost control signal (Fig. 4B: 408 Boost Decode Logic);
a switch coupled between a cell supply voltage source and the second plate of the boost capacitor (Fig. 4B: 412), wherein the switch is configured to couple the second plate to the cell supply voltage source based on the boost control signal being deasserted;
and a logic circuit (Fig. 4B: 408 Boost Decode Logic) configured to switch a voltage state of the first plate based on the boost control signal being asserted in order to boost voltage on the second plate by capacitive coupling.
Regarding claim 13, Sinangil and Zimmer disclose the method of Claim 8, wherein: the boost capacitor includes a first plate and a second plate (Fig. 4A: 404);
the method further comprises:
based on a boost control signal being deasserted, coupling a cell supply voltage source to the second plate of the boost capacitor, wherein the switch is configured(Fig. 4B: 412) to couple the second plate to the cell supply voltage source;
and based on the boost control signal being asserted, switching a voltage state of the first plate to boost voltage on the second plate by capacitive coupling (Fig. 2B: 268).
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 14 have been considered but are moot because the new ground of rejection.
Applicants arguments solely concern overcoming the prior rejection by amending the independent claims 1, 8, and 14 to include the limitations “the second assist circuit comprises a transistor having a source coupled to the voltage supply rail and a drain coupled to the common boost capacitor.” However, a new search resulted in a reference which teaches the second assist circuit disclosed by applicant in its entirety. Therefore, the combination of references, which both refer to these kinds of circuits as “Supply collapse circuits” would have been obvious to combine as they both disclose similar methods of implementing write assist. Therefore, a new rejection of the claims is maintained now under 35 U.S.C. 103.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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