!7ReDETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/17/2026 was filed after the mailing date of the Non-Final Rejection on04/03/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant's arguments filed 06/30/2026, with respect to 35 USC 103 rejection have been fully considered but they are not persuasive.
Applicants states (Remarks/Arguments, pg. 6) “The independent claims require two distinct durations of pulses at a second level that signal two different events: a first duration conveying that a power state in a first sequence is ending and a new power state in that same first sequence is beginning (an intra-sequence transition), and a second duration indicating that the first sequence as a whole is ending and a second sequence is beginning (an inter-sequence transition). The claimed structure thus distinguishes transitions within a sequence from transitions between sequences using pulse duration alone.
Leray does not teach or suggest these limitations.”
The Office respectfully disagrees. Leray teaches (e.g. Fig. 5) two distinct durations of pulses (Fig. 5: first “SYNC OUT” “pulse duration 512” corresponding to MATCH state 518 and second “SYNC OUT” pulse duration corresponding to MATCH state 520) at a second level (Fig 5, Para. [0036]: at a “second sync level 510”): a first duration conveying that a power state in a first sequence is ending and a new power state in that same first sequence is beginning (an intra-sequence transition) (Fig. 5, Para. [0036]: first “SYNC OUT” “pulse duration 512” depicts end of power state 502 and starting of power state 504 in a “first sync cycle”) and a second duration (Fig. 5, Para. [0036]: second “SYNC OUT” pulse duration corresponding to MATCH state 520) indicating that…a second sequence is beginning (an inter-sequence transition) (Fig. 4, 5, Para. [0031]-[0036], [0042]: SYNC OUT 410 indicates second/next RF power sequence 402’-406’ is beginning or duration of 510 corresponding to “third state 520” are at low level indicates second/subsequent RF power sequence 502’-506’ is beginning)).
The Office agreed that Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal, e.g. second “SYNC OUT” pulse duration corresponding to MATCH state 520) indicates that the first sequence as a whole (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
However, the office asserted that Wei et al. teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating “ending” of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Wei et al. teaches (Fig. 5, Para. [0032]) that a pulse e.g. synchronization pulse, provides dual functionality of indicating “ending” of a data frame/sequence and beginning of the next data frame/sequence. With such teaching , a person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) thus “greatly improved system efficiency.”
Hence, the Office maintains that Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1 previously cited) teaches all limitations as addressed in detail below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6, 8, 9, 13 and 15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1 previously cited).
Regarding Claim 1, Leray discloses;
A power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power) comprising:
a power generation component configured to generate a power waveform for transmission to a secondary component (Fig. 1, Para. [0028]: an apparatus 100 comprising: frequency generator 104 includes/comprises power generation component generating RF power signal for transmissions to match network 102/secondary component); and
a synchronization component configured to generate a synchronization signal for transmission to the secondary component via a synchronization line (Fig. 4, 5, Para. [0028]: frequency generator 104 includes/comprises synchronization component generating a synchronization signal (SYNC OUT) for transmission to the match network 102 via a SYNC connection 108 [a synchronization line]), wherein the synchronization signal is formed with pulses “comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508 - high level and 510 – low level), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power of the power waveform/“RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about event (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [indicate information about event] can be transmitted from the frequency generator to the match network”), and wherein a first duration of a pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: first duration of a first pulse 410/510 in the SYNC OUT signal) conveys to the secondary component that a power state in a first sequence of power states is ending (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…” That is, RF power state 402 or 502 is ending) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”. That is, new power RF state 404 or 504 is beginning in the first sequence of power states 402-406 or 502-506) and a second duration of the pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: second duration of second pulse 412/510 in the SYNC OUT signal) indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ (“prime symbols for subsequent power cycles”) of power waveform 400/500 is beginning).
Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 8, Leray discloses;
A match network (Fig. 1, Para. [0028], [0036]: match network 102) comprising:
an input (Fig. 8: 860) configured to receive a power waveform from a primary component over a first signal path (Fig. 1, Para. [0028]: “RF connection 106 provides an analog RF power signal) for transmission to the plasma processing apparatus (Fig. 8, Para. [0045]: “frequency generators and match networks may be used in pairs to supply RF power to generate plasma in a process chamber”); and
a synchronization component configured to receive a synchronization signal via a synchronization line from the primary component over a second signal path (Para. [0028]: “A SYNC connection 108 (and 108′) [a synchronization line] provides an analog synchronization signal [SYNC OUT] to the match network 102”; Para. [0045]: the match network is located in the “RF power source 818 or biasing power source 822”), wherein the synchronization signal is formed with pulses “comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508 - high level and 510 – low level), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power of the power waveform/ “RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about event (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [indicate information about event] can be transmitted from the frequency generator to the match network”), and wherein a first duration of a pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: first duration of a first pulse 410/510 in the SYNC OUT signal) conveys to the secondary component that a power state in a first sequence of power states is ending (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…”) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”) and a second duration of the pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: second duration of second pulse 412/510 in the SYNC OUT signal) indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ (“prime symbols for subsequent power cycles”) of power waveform 400/500 is beginning).
Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 15, Leray;
A power system (Fig. 1) comprising:
a power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power);
a match network (Fig. 1, Para. [0028], [0036]: match network), wherein
the power generator is configured to provide a power waveform to the match network (Fig. 1, Para. [0028]: an apparatus 100 comprising: frequency generator 104 providing an analog RF power signal for transmissions to match network 102); and
a primary synchronization module configured to generate a synchronization signal for transmission via a synchronization line to the power generator and/or the match network, wherein the synchronization signal is formed with pulses comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508, 508’ - high level and 510, 510’ – low levels), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power state of the power waveform/”RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about events (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 [duration of pulses at the second level – low levels] and an RF power value 514 and frequency of the second RF power level 504 [i.e., indicate information about event] can be transmitted from the frequency generator to the match network.”) wherein a first duration of a pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: first duration of a first pulse 410/510 in the SYNC OUT signal) conveys to the match network that a power state in a first sequence of power states is ending (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…”) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”) and a second duration of the pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: second duration of second pulse 412/510 in the SYNC OUT signal) indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ (“prime symbols for subsequent power cycles”) of power waveform 400/500 is beginning).
Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 2, Leray in view of Wei et al. discloses all as applied to claim 1 above, where Leray further teaches;
wherein the secondary component is a matching network (Fig. 1, Para. [0028], [0036]: match network).
Regarding Claim 6 and 13, Leray in view of Wei et al. discloses all as applied to claim 1 and 8 above, where Leray further teaches;
wherein a third duration of the pulse at the second level (Fig. 4, 5: SYNC OUT 412 or 510 corresponding to “third state 520” are at low level) indicates the first sequence is ending (Fig. 4, [0031]-[0036], [0042]: SYNC OUT 410 indicates first power state 402 is ending or duration of 510 corresponding to “third state 520” are at low level indicates first RF power sequence, 502-506 is ending) and a second sequence is beginning (Fig. 4, Para. [0031]-[0036], [0042]: SYNC OUT 410 indicates second/next RF power sequence 402’-406’ is beginning or duration of 510 corresponding to “third state 520” are at low level indicates second/subsequent RF power sequence 502’-506’ is beginning).
Regarding Claim 9, Leray in view of Wei et al. discloses all as applied to claim 8 above, where Leray further teaches;
wherein the primary component is a power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power signal; Fig. 8, Para. [0045]: “RF power source 818 or biasing power source 822”).
Regarding Claim 18, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein the power generator comprises the primary synchronization module (Para. [0028], [0047]: frequency generator 104 may “utilize[d] alone or as a processing module [primary synchronization module] of an integrated semiconductor substrate processing system, or cluster tool”).
Regarding Claim 19, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein the match network comprises the primary synchronization module (Fig. 1, Para. [0028], [0036], [0047]: match network may “utilized alone or as a processing module [primary synchronization module] of an integrated semiconductor substrate processing system, or cluster tool”).
Regarding Claim 20, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein a centralized controller comprises the primary synchronization module (Para. [0047]: “The RF power source 818 may also include a controller 862”; Para. [0078]: “the RF power source 818 may be controlled by controller 840”).
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1 previously cited) further in view of Yamada et al. (US 20090189686 A1 previously cited).
Regarding Claim 7 and 14, Leray in view of Wei et al. discloses all as applied to claim 1 and 8 above, however they do not teach;
wherein a threshold time of inactivity of the pulse at the first power level indicates the power waveform is off.
On the other hand, Yamada et al. teaches:
wherein a threshold time of inactivity of the pulse at the first power level indicates the power waveform is off.
(Para. [0065]: “set a predetermined wait time before switching a power-on state to a power-off state, so that when the wait time expires, a power control signal indicating power-off is output to each unit”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the ON times and durations of the pulse at the first power level in Leray in view of Wei et al.’s invention can be set to expire after a predetermined threshold time to indication power-off state as taught by Yamada et al. where doing so would (Yamada et al., Para. [0007]) provide “for reducing power consumption” and preventing damage to the power generator, equipment in proximity to the load of the power supply, and potential costly damages by leaving the device ON for longer than the manufacturer designed it for.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMNEET SINGH whose telephone number is (571)272-2414. The examiner can normally be reached 9:30am to 5:30pm.
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633
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