DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/21/2026 has been entered.
Response to Arguments
Applicant's arguments filed 01/21/2026, with respect to 35 USC 103) rejection have been fully considered but they are not persuasive.
Applicants states (Remarks/Arguments, pg. 6) “In response, to advance prosecution and without acquiescing to any of the positions in the office action, independent claims 1, 8, and 15 have been amended to further distinguish the claims from the prior art; thus, rendering the rejection moot.… Applicant submits that Leray neither teaches nor suggests the claimed aspects of independent claims 1, 8, and 15, so Applicant respectfully requests reconsideration in view of the same”.
The Office respectfully disagrees. At least Leray teaches the newly added limitation of “pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508 and 510), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power of the power waveform/”RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about event (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [indicate information about event] can be transmitted from the frequency generator to the match network”)…power state in a first sequence of power states is ending (Fig. 4, 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…”. That is, RF power state 402 or 502 is ending) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”) and… a second duration of the pulse at the second level in the synchronization signal indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ of power waveform 400/500 is beginning).”
The Office agreed that Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
However, the office asserted that Wei et al. teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Hence, the Office maintains that Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1 previously cited) teaches the newly amended limitations as addressed in detail below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 6, 8, 9, 13 and 15, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1 previously cited).
Regarding Claim 1, Leray discloses;
A power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power) comprising:
a power generation component configured to generate a power waveform for transmission to a secondary component (Fig. 1, Para. [0028]: an apparatus 100 comprising: frequency generator 104 includes/comprises power generation component generating RF power signal for transmissions to match network 102/secondary component); and
a synchronization component configured to generate a synchronization signal for transmission to the secondary component via a synchronization line (Fig. 4, 5, Para. [0028]: frequency generator 104 includes/comprises synchronization component generating a synchronization signal (SYNC OUT) for transmission to the match network 102 via a SYNC connection 108 [a synchronization line]), wherein the synchronization signal is formed with pulses “comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508 - high level and 510 – low level), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power of the power waveform/”RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about event (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [indicate information about event] can be transmitted from the frequency generator to the match network”) at the second level in the synchronization signal (e.g. Fig. 4, 5: first duration of a first pulse 410/510 in the SYNC OUT signal) conveys to the secondary component that a power state in a first sequence of power states is ending (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…” That is, RF power state 402 or 502 is ending) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”. That is, new power RF state 404 or 504 is beginning in the first sequence of power states 402-406 or 502-506) and of the pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: second duration of second pulse 412/510 in the SYNC OUT signal) indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ (“prime symbols for subsequent power cycles”) of power waveform 400/500 is beginning).
Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 8, Leray discloses;
A match network (Fig. 1, Para. [0028], [0036]: match network 102) comprising:
an input (Fig. 8: 860) configured to receive a power waveform from a primary component over a first signal path (Fig. 1, Para. [0028]: “RF connection 106 provides an analog RF power signal) for transmission to the plasma processing apparatus (Fig. 8, Para. [0045]: “frequency generators and match networks may be used in pairs to supply RF power to generate plasma in a process chamber”); and
a synchronization component configured to receive a synchronization signal via a synchronization line from the primary component over a second signal path (Para. [0028]: “A SYNC connection 108 (and 108′) [a synchronization line] provides an analog synchronization signal [SYNC OUT] to the match network 102”; Para. [0045]: the match network is located in the “RF power source 818 or biasing power source 822”), wherein the synchronization signal is formed with pulses “comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508 - high level and 510 – low level), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power of the power waveform/”RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about event (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [indicate information about event] can be transmitted from the frequency generator to the match network”) at the second level in the synchronization signal (e.g. Fig. 4, 5: first duration of a first pulse 410/510 in the SYNC OUT signal) conveys to the secondary component that a power state in a first sequence of power states is ending (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508…”) and a new power state in the first sequence of power states is beginning (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 and an RF power value 514 and frequency of the second RF power level 504 [new power state 504 is beginning] can be transmitted from the frequency generator to the match network”) and of the pulse at the second level in the synchronization signal (e.g. Fig. 4, 5: second duration of second pulse 412/510 in the SYNC OUT signal) indicates…a second sequence of power states is beginning (Fig. 3-5, Para. [0032], [0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one...A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 412/510 conveys to the match network that a second sequence RF OUT state 402’-406’/502’-506’ (“prime symbols for subsequent power cycles”) of power waveform 400/500 is beginning).
Leary does not explicitly state that a second duration of the pulse at the second level in the synchronization signal (second pulse 412/510 in the SYNC OUT signal) indicates that the first sequence of power states (Fig. 4, 5, Para. [0036]: the first sequence of power states 402-406/502-506) is:
“ending.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/sequence and beginning of the next data frame/sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second pulse of a second duration in the synchronization signal (e.g. Fig. 4, 5: second duration of a second pulse 412/510 in the SYNC OUT signal) in Leray’s invention is further providing the functionality of indicating that the first sequence of power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of power states 402-406/502-506 are ending) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 15, Leray;
A power system (Fig. 1) comprising:
a power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power);
a match network (Fig. 1, Para. [0028], [0036]: match network), wherein
the power generator is configured to provide a power waveform to the match network (Fig. 1, Para. [0028]: an apparatus 100 comprising: frequency generator 104 providing an analog RF power signal for transmissions to match network 102); and
a primary synchronization module configured to generate a synchronization signal for transmission via a synchronization line to the comprising pulses at a first level and pulses at a second level (Fig. 5: “SYNC OUT” waveform with first and second pulse levels, e.g. 508, 508’ - high level and 510, 510’ – low levels), wherein the pulses at the first level indicate power of the power waveform is on (Fig. 5, Para. [0036]: first level pulse 508 indicate power state of the power waveform/”RF OUT”, e.g. , 502, is on) and a duration of pulses at the second level indicate information about events (Fig. 5, Para. [0036]: “a pulse duration 512 of the second RF power level relative to the end of the first sync level 508 [duration of pulses at the second level – low levels] and an RF power value 514 and frequency of the second RF power level 504 [i.e., indicate information about event] can be transmitted from the frequency generator to the match network.”) wherein a first duration of a pulse at the second level indicates a change in power states (Fig. 3-5, Para. [0032]-[0033], [0036]: “To reduce or eliminate delays in the semiconductor process system, the SYNC OUT, (e.g., two level TTL signal) arrives at the match network prior to the RF OUT signal”; “The relationship between the pulses of RF OUT and SYNC OUT is one for one…A state may contain an RF power value, a frequency, a timing duration (e.g., ON time), a timing starting point (e.g., relative to a particular sync pulse, etc.), and the like to allow the match network to easily recreate the RF power pulse waveform for each cycle.” As depicted in Fig. 4/5, SYNC OUT pulse 408/508 conveys to the match network that a first RF OUT state 402/502 of power waveform 400/500 is ending and/or a second RF OUT state 404/504 of power waveform 400/500 is beginning), wherein a second duration of a pulse at the second level (Fig. 4, 5, Para. [0033], [0036]: second duration of a pulse 412 or pulse duration of 510 corresponding to “third state 520” in the “first RF cycle”…
Leary does not explicitly state that the second duration of a pulses, 412 or pulse duration of 510 corresponding to “third state 520” in the “first RF cycle” indicates:
“a change in power sequences.”
On the other hand, Wei et al teaches (Fig. 5, Para. [0032]) “the Vsync signal provides a synchronization pulse which indicates the end of a data frame and the beginning of the next data frame.” That is, a single synchronization pulse, provides dual functionality of indicating ending of a data frame/state sequence and beginning of the next data frame/state sequence, i.e. indicates a change of a frame or a state sequence.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the second duration of a pulses, 412 or pulse duration of 510 corresponding to “third state 520” in the “first RF cycle” in Leray’s invention is further providing the functionality of indicating that the first sequence of RF power states is ending (Fig. 4, 5: second pulse 412/510 in the SYNC OUT signal indicates the first sequence of RF power states 402-406/502-506 are ending, that is indicate a change in RF power sequence) as taught by Wei et al. where doing so would (Wei et al. Para. [0037]) “greatly improved system efficiency.”
Regarding Claim 2, Leray in view of Wei et al. discloses all as applied to claim 1 above, where Leray further teaches;
wherein the secondary component is a matching network (Fig. 1, Para. [0028], [0036]: match network).
Regarding Claim 6 and 13, Leray in view of Wei et al. discloses all as applied to claim 1 and 8 above, where Leray further teaches;
wherein a of the pulse at the second level (Fig. 4, 5: SYNC OUT 412 or 510 corresponding to “third state 520” are at low level) indicates indicates first RF power sequence, 502-506 is ending) and a second sequence is beginning (Fig. 4, Para. [0031]-[0036], [0042]: SYNC OUT 410 indicates second/next RF power sequence 402’-406’ is beginning or duration of 510 corresponding to “third state 520” are at low level indicates second/subsequent RF power sequence 502’-506’ is beginning).
Regarding Claim 9, Leray in view of Wei et al. discloses all as applied to claim 8 above, where Leray further teaches;
wherein the primary component is a power generator (Fig. 1, Para. [0028]: frequency generator 104 providing an analog RF power signal; Fig. 8, Para. [0045]: “RF power source 818 or biasing power source 822”).
Regarding Claim 18, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein the power generator comprises the primary synchronization module (Para. [0028], [0047]: frequency generator 104 may “utilize[d] alone or as a processing module [primary synchronization module] of an integrated semiconductor substrate processing system, or cluster tool”).
Regarding Claim 19, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein the comprises the primary synchronization module (Fig. 1, Para. [0028], [0036], [0047]: match network may “utilized alone or as a processing module [primary synchronization module] of an integrated semiconductor substrate processing system, or cluster tool”).
Regarding Claim 20, Leray in view of Wei et al. discloses all as applied to claim 15 above, where Leray further teaches;
wherein a centralized controller comprises the primary synchronization module (Para. [0047]: “The RF power source 818 may also include a controller 862”; Para. [0078]: “the RF power source 818 may be controlled by controller 840”).
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Leray (US 20190304753 A1 previously cited) in view of Wei et al. (US 20150002629 A1) further in view of Yamada et al. (US 20090189686 A1 previously cited).
Regarding Claim 7 and 14, Leray in view of Wei et al. discloses all as applied to claim 1 and 8 above, however they do not teach;
wherein a threshold time of inactivity f the pulse at the first power level indicates the power waveform is off.
On the other hand, Yamada et al. teaches:
wherein a threshold time of inactivity of the pulse at the first power level indicates the power waveform is off.
(Para. [0065]: “set a predetermined wait time before switching a power-on state to a power-off state, so that when the wait time expires, a power control signal indicating power-off is output to each unit”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the ON times and durations of the pulse at the first power level in Leray in view of Wei et al.’s invention can be set to expire after a predetermined threshold time to indication power-off state as taught by Yamada et al. where doing so would (Yamada et al., Para. [0007]) provide “for reducing power consumption” and preventing damage to the power generator, equipment in proximity to the load of the power supply, and potential costly damages by leaving the device ON for longer than the manufacturer designed it for.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimizu et al. (US 9872373 B1) discloses (Abstract, Fig. 2A-2C, 5, 6, col. 10, line 22-49) “a method of operating a plasma enhanced substrate processing system using multi-level pulsed RF power includes providing a first multi-level RF power waveform to a process chamber, the first multi-level RF power waveform having at least a first power level, a second power level, and a third power level, providing, after a first delay period, a second multi-level RF power waveform to the process chamber, the second multi-level RF power waveform having at least a first power level, a second power level, and a third power level, and processing the substrate using the first multi-level RF power waveform and the second multi-level RF power waveform to produce a features on the substrate have an aspect ratio of greater than 60:1 while maintaining an etch rate of greater than 170 nm/min”
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/AMNEET SINGH/Examiner, Art Unit 2633 /SAM K AHN/Supervisory Patent Examiner, Art Unit 2633