DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
This action is in reply to the amendments filed on 08/28/2025.
Claims 1-20 are currently pending and have been examined.
Claims 1, 7, 11, and 16 are amended.
Claims 1-20 are currently rejected.
This action is made FINAL.
Response to Arguments
Applicant’s arguments filed 08/28/2025 have been fully considered but they are not persuasive.
Regarding the drawing objections, in light of the corrected drawings submitted the drawing objections are withdrawn.
Regarding the 112 rejections, in light of the amendments these rejections have been withdrawn.
Applicant’s arguments with regards to the art rejections have been considered and appear to be directed solely to the instant amendments to the claims. Accordingly, the claims are addressed in the body of the updated rejections below.
Claim Objections
A series of singular dependent claims is permissible in which a dependent claim refers to a preceding claim which, in turn, refers to another preceding claim.
A claim which depends from a dependent claim should not be separated by any claim which does not also depend from said dependent claim. It should be kept in mind that a dependent claim may refer to any preceding independent claim. In general, applicant's sequence will not be changed. See MPEP § 608.01(n).
The ordering of the claims will be corrected upon allowance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 10-15, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Immel et. al. (US 2018/0048142), herein Immel in view of Hoshino et. al. (JP 2017112779A) and Kikuchi et. al. (US 2016/0261202), herein Kikuchi.
Regarding claim 1:
Immel teaches:
A shut-off circuit (an electronic circuit breaker [abstract]) for use in a control system having a motor control module (a control unit configured to control the switching unit as a function of the determined value so as to interrupt the circuit [0008]), a relay (examiner notes that between the battery and the circuit there would inherently be a relay to connect/disconnect the battery.), an intelligent power device (fig. 3, controllable switching element 7), a computer processing unit (fig. 3, control device μC) and a motor (fig. 3, load 2), the motor control module configured to transmit commands to actuate the relay (When the battery voltage is applied the electronic circuit breaker 1 [0054]) and the intelligent power device (the controllable switching element has a control input [0017]), the intelligent power device coupled to a battery (fig. 3, energy storage device 4) to provide power to the motor (fig. 3, load 2), the shut-off circuit comprising:
a first transistor (fig. 3, pnp transistor) connected in series (see fig. 3) to a second transistor (fig. 3, npn-1 transistor) at a first node (see fig. 3), the second transistor having a source connected to a ground (The emitter of the transistor is electrically coupled to ground [0028]), the first transistor and the second transistor interposed between the relay and the intelligent power device (see fig. 3, with transistors pnp and npn-2 between the battery 4 (which would inherently have a relay) and switching element 7 (IPD));
a first input (the base of the pnp transistor pnp is electrically coupled via a first resistor R1 to the source of the MOSFET p-ch or the controllable switching element 7 [0046]) [configured to receive a first signal from the motor control module and] connected in series with the first transistor (pnp transistor pnp [0046]); and
a second input (the reset output of the control unit [0031]) [configured to receive a first signal from the computer processing unit and] connected in series with the second transistor (the base of the second npn transistor is coupled to the reset output of the control unit [0031]),
wherein the motor control module transmits the first signal to the first transistor so as to turn on the first transistor so as to direct power to the motor (The collector of the pnp transistor pnp is connected to the gate of the MOSFET or to the control input of the controllable switching element 7 [0046]), the computer processing unit [generates the second signal when an error is detected in the control system, and] the computer processing unit transmits the second signal to the second transistor so as to turn on the second transistor wherein power is directed to the ground (a TEST or OFF output of the control device μC is electrically coupled through a third diode D3 to the base of the first transistor npn-1 [0051]), turning off the intelligent power device (This causes the first npn transistor npn-1 to lose its triggering and the base of the pnp transistor pnp is pulled over the first resistor R1 to its emitter potential. This causes it to lock and the MOSFET p-ch/7 becomes conductive again [0054]).
Hoshino also teaches:
An intelligent power device (fig. 4, an IPD (intelligent power device) circuit 54)
Immel does not explicitly teach, however Hoshino teaches:
a relay (fig. 4, two relays (IGM relay 55 and IGP relay 56))
the motor control module configured to transmit commands to actuate the relay (a CPU 11 that controls the IGM relay 5 [abstract]; The IGP relay 6 is turned on / off by an ECU (Engine Control Unit) 13 [2nd paragraph of description])
the first transistor and the second transistor interposed between the relay and the intelligent power device (examiner notes how the circuit breaker as taught by Immel can be inserted into the circuit at point X in fig. 4 which is used to detect voltage);
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel to include the teachings as taught by Hoshino with a reasonable expectation of success. Applying the teachings of a relay connected to the battery and an IPD connected to a motor as taught by Hoshino to the circuit breaker as taught by Immel is combining prior art elements according to known methods to yield predictable results. Both arts teach controlling power from a battery to a motor using known circuit components, however each circuit does not teach all the components recited in the claims. Adding a relay to the battery side of the circuit of Immel would provide a means to physically disconnect a vehicles high voltage battery when not in use.
Kikuchi also teaches:
the second transistor having a source connected to a ground (The protection transistor 422 is interposed between the SH_OUT terminal and the GND terminal [0069])
wherein the motor control module (a primary side controller 202 [0007]) transmits the first signal to the first transistor (The primary side controller 202 adjusts the duty cycle of the switching transistor M1 [0010]) so as to turn on the first transistor so as to direct power to the motor (The isolated DC/DC converter 200r receives the DC voltage V.sub.IN input at its input terminal P1 to drop the DC voltage V.sub.IN down, and supplies an output voltage V.sub.OUT, which is stabilized at a target value, to a load (not shown) connected between its output terminal P2 [0006]),
the computer processing unit (An abnormality detection circuit 430 [0074]) transmits the second signal (asserts an abnormality detection signal S12 if the abnormality is detected [0074]) to the second transistor so as to turn on the second transistor wherein power is directed to the ground (For the protection circuit 420 with a latch function, if a state where the abnormality detection signal S11 is asserted lasts for a determination time, the latch/auto-restart circuit 424 latches that state and continues to turn on the protection transistor 422 [0069]), turning off the intelligent power device (examiner notes when activated transistor 422 sinks the power to ground instead of going to output P2 which could be an IPD as described in the other references supra.).
Immel in view of Hoshino does not explicitly teach, however Kikuchi teaches:
a first input (fig. 7, base of transistor M1) configured to receive a first signal (fig. 7, 202 - out) from the motor control module (fig. 7, controller 202) and connected in series with the first transistor (The primary side controller 202 adjusts the duty cycle of the switching transistor M1 based on a voltage (feedback voltage) V.sub.FB of the FB terminal. [0010]); and
a second input (fig. 8, base of transistor 422) configured to receive a first signal (generating the abnormality detection signal S12 indicating a result of the comparison [0077]) from the computer processing unit (fig. 7, abnormality detection circuit 430) and connected in series with the second transistor (The protection circuit 420 draws the second current I.sub.SINK2 when the abnormality detection signal S12 is asserted (for example, has a high level). [0077]),
the computer processing unit (fig. 7, abnormality detection circuit 430) generates the second signal when an error is detected in the control system (An abnormality detection circuit 430 determines whether or not abnormality occurs in the secondary side, based on the sense signal V.sub.SEN input to the SEN terminal, and asserts an abnormality detection signal S12 if the abnormality is detected. [0074]), and
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel and Hoshino to include the teachings as taught by Kikuchi with a reasonable expectation of success. All of the applied arts are in the same field of endeavor of controlling electrical flow in a circuit. Kikuchi also teaches the benefit of “The protection circuit may include a protection transistor having one end connected to the output terminal and the other end connected to the ground terminal. The protection transistor may be turned on when the abnormality is detected [Kikuchi, 0017]”.
Regarding claim 2:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
wherein the first transistor is a PNP transistor (fig. 3, pnp transistor).
Regarding claim 3:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
wherein the second transistor is an NPN transistor (fig. 3, npn-1 transistor).
Regarding claim 4:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
wherein the first signal has a lower voltage than the second signal (see fig. 3, the base of a pnp transistor has a lower voltage than the emitter and the emitter from the pnp transistor goes to the base of npn-1 transistor (second signal) which means it has a higher voltage then the first signal.).
Regarding claim 5:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
further including a first resistor (fig. 3, first resistor R1) and a second resistor (fig. 3, shunt resistor 3) connected in parallel at a second node (fig. 3, node between elements 3 and 7), the second node interposed between the first transistor and the first input (see fig. 3).
Regarding claim 6:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 5, upon which this claim is dependent.
Immel further teaches:
further including a first capacitor (fig. 4, capacitor 58) connected in parallel with both the first resistor and the first transistor, the first capacitor interposed between the first resistor and the first transistor (examiner notes that the capacitor of Hoshino would be in parallel between the first resistor and first transistor when combined as taught in claim 1. Additionally there are a finite amount of configurations in which to configure these three elements and it would be obvious through routine optimization to arrive at the claimed placement.).
Regarding claim 8:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
further including a fifth resistor (fig. 3, resistor R2) interposed between the first transistor and the first node (see fig. 3 between pnp transistor and switch 7).
Regarding claim 10:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel further teaches:
further including a second diode (fig. 3, diode 1) interposed between the first node and the intelligent power device (see fig. 3 showing diode 1 between the first node (right above diode 2) and the IPD 7), the second diode in parallel with the second transistor and the intelligent power device (see fig. 3).
Regarding claim 11:
Immel teaches:
A power distribution box for a vehicle system (An electronic circuit breaker 1 [0043]), the vehicle system including a control module configured to control the operation (a control unit configured to control the switching unit as a function of the determined value so as to interrupt the circuit [0008]) of a motor (fig. 1 load 2) and a battery for supplying power to the motor (fig. 1, battery 4), the power distribution box comprising:
a relay (examiner notes that between the battery and the circuit there would inherently be a relay to connect/disconnect the battery.)
an intelligent power device (fig. 3, controllable switching element 7)
a computer processing unit (fig. 3, control device μC) configured to transmit and receive instructions to and from the control module; and
a shut-off circuit (an electronic circuit breaker [abstract])
a first transistor (fig. 3, pnp transistor) connected in parallel to a second transistor (fig. 3, npn-1 transistor) at a first node (see fig. 3), the second transistor having a source connected to a ground (The emitter of the transistor is electrically coupled to ground [0028]), the first transistor and the second transistor interposed between the relay and the intelligent power device (see fig. 3, with transistors pnp and npn-2 between the battery 4 (which would inherently have a relay) and switching element 7 (IPD));
a first input (the base of the pnp transistor pnp is electrically coupled via a first resistor R1 to the source of the MOSFET p-ch or the controllable switching element 7 [0046]) [configured to receive a first signal from the motor control module and]connected in series with the first transistor (pnp transistor pnp [0046]); and
a second input (the reset output of the control unit [0031]) [configured to receive a first signal from the computer processing unit and]connected in series with the second transistor (the base of the second npn transistor is coupled to the reset output of the control unit [0031]),
wherein the control module transmits a first signal to the first transistor so as to turn on the first transistor so as to direct power to the motor (The collector of the pnp transistor pnp is connected to the gate of the MOSFET or to the control input of the controllable switching element 7 [0046]), the computer processing unit [generates the second signal when an error is detected in the control system, and] the computer processing unit transmits the second signal to the second transistor so as to turn on the second transistor wherein power is directed to the ground (a TEST or OFF output of the control device μC is electrically coupled through a third diode D3 to the base of the first transistor npn-1 [0051]), turning off the intelligent power device (This causes the first npn transistor npn-1 to lose its triggering and the base of the pnp transistor pnp is pulled over the first resistor R1 to its emitter potential. This causes it to lock and the MOSFET p-ch/7 becomes conductive again [0054]).
Hoshino also teaches:
An intelligent power device (fig. 4, an IPD (intelligent power device) circuit 54)
Immel does not explicitly teach, however Hoshino teaches:
a relay (fig. 4, two relays (IGM relay 55 and IGP relay 56))
electrically coupled to the battery and the control module, the control module configured to turn on and off the relay (a CPU 11 that controls the IGM relay 5 [abstract]; The IGP relay 6 is turned on / off by an ECU (Engine Control Unit) 13 [2nd paragraph of description])
disposed on the first electrical path and interposed between the relay and the intelligent power device, the shut-off circuit including (examiner notes how the circuit breaker as taught by Immel can be inserted into the circuit at point X in fig. 4 which is used to detect voltage);
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel to include the teachings as taught by Hoshino with a reasonable expectation of success. Applying the teachings of a relay connected to the battery and an IPD connected to a motor as taught by Hoshino to the circuit breaker as taught by Immel is combining prior art elements according to known methods to yield predictable results. Both arts teach controlling power from a battery to a motor using known circuit components, however each circuit does not teach all the components recited in the claims. Adding a relay to the battery side of the circuit of Immel would provide a means to physically disconnect a vehicles high voltage battery when not in use.
Kikuchi also teaches:
the second transistor having a source connected to a ground (The protection transistor 422 is interposed between the SH_OUT terminal and the GND terminal [0069])
wherein the motor control module (a primary side controller 202 [0007]) transmits the first signal to the first transistor (The primary side controller 202 adjusts the duty cycle of the switching transistor M1 [0010]) so as to turn on the first transistor so as to direct power to the motor (The isolated DC/DC converter 200r receives the DC voltage V.sub.IN input at its input terminal P1 to drop the DC voltage V.sub.IN down, and supplies an output voltage V.sub.OUT, which is stabilized at a target value, to a load (not shown) connected between its output terminal P2 [0006]),
the computer processing unit (An abnormality detection circuit 430 [0074]) generates the second signal (asserts an abnormality detection signal S12 if the abnormality is detected [0074]) to the second transistor so as to turn on the second transistor wherein power is directed to the ground (For the protection circuit 420 with a latch function, if a state where the abnormality detection signal S11 is asserted lasts for a determination time, the latch/auto-restart circuit 424 latches that state and continues to turn on the protection transistor 422 [0069]), turning off the intelligent power device (examiner notes when activated transistor 422 sinks the power to ground instead of going to output P2 which could be an IPD as described in the other references supra.).
Immel in view of Hoshino does not explicitly teach, however Kikuchi teaches:
a first input (fig. 7, base of transistor M1) configured to receive a first signal (fig. 7, 202 - out) from the motor control module (fig. 7, controller 202) and connected in series with the first transistor (The primary side controller 202 adjusts the duty cycle of the switching transistor M1 based on a voltage (feedback voltage) V.sub.FB of the FB terminal. [0010]); and
a second input (fig. 8, base of transistor 422) configured to receive a first signal (generating the abnormality detection signal S12 indicating a result of the comparison [0077]) from the computer processing unit (fig. 7, abnormality detection circuit 430) and connected in series with the second transistor (The protection circuit 420 draws the second current I.sub.SINK2 when the abnormality detection signal S12 is asserted (for example, has a high level). [0077]),
the computer processing unit (fig. 7, abnormality detection circuit 430) generates the second signal when an error is detected in the control system (An abnormality detection circuit 430 determines whether or not abnormality occurs in the secondary side, based on the sense signal V.sub.SEN input to the SEN terminal, and asserts an abnormality detection signal S12 if the abnormality is detected. [0074]), and
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel and Hoshino to include the teachings as taught by Kikuchi with a reasonable expectation of success. All of the applied arts are in the same field of endeavor of controlling electrical flow in a circuit. Kikuchi also teaches the benefit of “The protection circuit may include a protection transistor having one end connected to the output terminal and the other end connected to the ground terminal. The protection transistor may be turned on when the abnormality is detected [Kikuchi, 0017]”.
Regarding claim 12:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel further teaches:
wherein the first transistor is a PNP transistor (fig. 3, pnp transistor) and the second transistor is an NPN transistor (fig. 3, npn-1 transistor).
Regarding claim 13:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel further teaches:
wherein the first signal has a lower voltage than the second signal (see fig. 3, the base of a pnp transistor has a lower voltage than the emitter and the emitter from the pnp transistor goes to the base of npn-1 transistor (second signal) which means it has a higher voltage then the first signal.).
Regarding claim 14:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel further teaches:
further including a first resistor (fig. 3, first resistor R1) and a second resistor (fig. 3, shunt resistor 3) connected in parallel at a second node (fig. 3, node between elements 3 and 7), the second node interposed between the first transistor and the first input (see fig. 3).
Regarding claim 15:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 14, upon which this claim is dependent.
Immel further teaches:
further including a first capacitor (fig. 4, capacitor 58) connected in parallel with both the first resistor and the first transistor, the first capacitor interposed between the first resistor and the first transistor (examiner notes that the capacitor of Hoshino would be in parallel between the first resistor and first transistor when combined as taught in claim 1. Additionally there are a finite amount of configurations in which to configure these three elements and it would be obvious through routine optimization to arrive at the claimed placement.).
Regarding claim 17:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel further teaches:
further including a fifth resistor (fig. 3, resistor R2) interposed between the first transistor and the first node (see fig. 3 between pnp transistor and switch 7).
Regarding claim 19:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel further teaches:
further including a second diode (fig. 3, diode 1) interposed between the first node and the intelligent power device (see fig. 3 showing diode 1 between the first node (right above diode 2) and the IPD 7), the second diode in parallel with the second transistor and the intelligent power device (see fig. 3).
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Immel et. al. (US 2018/0048142), herein Immel in view of Hoshino et. al. (JP 2017112779A) and Kikuchi et. al. (US 2016/0261202), herein Kikuchi in further view of Melvin et. al. (US 6,288,881), herein Melvin.
Regarding claim 7:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 1, upon which this claim is dependent.
Immel in view of Hoshino and Kikuchi does not explicitly teach, however Melvin teaches:
further including a third resistor (fig. 3, resistor R19) and a fourth resistor (fig. 3, resistor R15) connected in series with each other (see fig. 3) and a third node interposed between the second input and the second transistor (The base input to transistor Q5 is connected to a voltage detector circuit 88, which is a voltage divider comprising resistor R19 and resistor R15, connected to a circuit node between the field terminal FLD and the series combination of the resettable fuse 80 and the controlled switch 82 [col 6, lines 23-28]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel in view of Hoshino and Kikuchi to include the teachings as taught by Melvin with a reasonable expectation of success. Melvin teaches the benefit of “A voltage regulator protecting both the regulator and the electrical system [Melvin, abstract]”.
Regarding claim 16:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel in view of Hoshino and Kikuchi does not explicitly teach, however Melvin teaches:
further including a third resistor (fig. 3, resistor R19) and a fourth resistor (fig. 3, resistor R15) connected in series with each other (see fig. 3) and a third node interposed between the second input and the second transistor (The base input to transistor Q5 is connected to a voltage detector circuit 88, which is a voltage divider comprising resistor R19 and resistor R15, connected to a circuit node between the field terminal FLD and the series combination of the resettable fuse 80 and the controlled switch 82 [col 6, lines 23-28]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel in view of Hoshino and Kikuchi to include the teachings as taught by Melvin with a reasonable expectation of success. Melvin teaches the benefit of “A voltage regulator protecting both the regulator and the electrical system [Melvin, abstract]”.
Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Immel et. al. (US 2018/0048142), herein Immel in view of Hoshino et. al. (JP 2017112779A) and Kikuchi et. al. (US 2016/0261202), herein Kikuchi in further view of Aoyama et. al. (US 11,217,410), herein Aoyama.
Regarding claim 9:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 5, upon which this claim is dependent.
Immel in view of Hoshino and Kikuchi does not explicitly teach, however Aoyama teaches:
further including a first diode (fig. 1, diode D2) interposed between the second node and the first input (see fig. 1, showing diode between pnp transistor input and the node between R5 and R6).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel in view of Hoshino and Kikuchi to include the teachings as taught by Aoyama with a reasonable expectation of success. Aoyama teaches the benefit of “The protective component is connected in the control input line to protect the semiconductor component. The buffer circuit is connected between the protective component in the control input line and the control terminal of the semiconductor component to compensate for a voltage drop due to the protective component. [Aoyama, abstract]”.
Regarding claim 18:
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 14, upon which this claim is dependent.
Immel in view of Hoshino and Kikuchi does not explicitly teach, however Aoyama teaches:
further including a first diode (fig. 1, diode D2) interposed between the second node and the first input (see fig. 1, showing diode between pnp transistor input and the node between R5 and R6).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel in view of Hoshino and Kikuchi to include the teachings as taught by Aoyama with a reasonable expectation of success. Aoyama teaches the benefit of “The protective component is connected in the control input line to protect the semiconductor component. The buffer circuit is connected between the protective component in the control input line and the control terminal of the semiconductor component to compensate for a voltage drop due to the protective component. [Aoyama, abstract]”.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Immel et. al. (US 2018/0048142), herein Immel in view of Hoshino et. al. (JP 2017112779A) and Kikuchi et. al. (US 2016/0261202), herein Kikuchi in further view of Noto et. al. (US 2016/0298761), herein Noto.
Immel in view of Hoshino and Kikuchi teaches all the limitations of claim 11, upon which this claim is dependent.
Immel in view of Hoshino and Kikuchi does not explicitly teach, however Noto teaches:
wherein the vehicle system is a park by wire system and the motor is a park by wire motor (an automatic transmission 1 to be installed in a vehicle includes an actuator (motor) 3 for park by wire (PBW) to drive a range switching valve [0022]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the claimed invention to have modified Immel in view of Hoshino and Kikuchi to include the teachings as taught by Noto with a reasonable expectation of success. Noto teaches the benefit of “in changing the range position of the transmission, the actuator is braked in accordance with the drawing force of the spring into the groove so that energy of the velocity can be controlled to approach zero when the roller reaches a target stop position. Thus, collision noise occurring when the roller collides with a groove of a detent plate can be reduced [Noto, 0011]”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tominaga (US 2023/0286412) discloses A control device includes a total characteristic value calculation part configured to calculate a total characteristic value showing a total characteristic change of a battery, a local characteristic value estimation part configured to estimate a local characteristic value showing a local characteristic change of the battery, and a current controller configured to control a current flowing to the battery on the basis of a ratio between the total characteristic value and the local characteristic value.
Tomioka (US 2022/0308614) discloses a shunt regulator including: multiple resistors, connected in series between an output terminal and a ground terminal and constituting a voltage divider circuit; an output transistor, connected between the output terminal and the ground terminal; a first drive circuit, including a first reference voltage circuit which outputs a first reference voltage and an error amplifier, and controlling the output transistor based on a voltage of a first output terminal of the voltage divider circuit; a second drive circuit, controlling the output transistor based on a voltage of a second output terminal of the voltage divider circuit; and an activation control circuit, switching operation of the first drive circuit and the second drive circuit based on the first reference voltage. The second drive circuit has a shorter activation time than the first drive circuit.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott R Jagolinzer whose telephone number is (571)272-4180. The examiner can normally be reached M-Th 8AM - 4PM Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christian Chace can be reached at (571)272-4190. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Scott R. Jagolinzer
Examiner
Art Unit 3665
/S.R.J./Examiner, Art Unit 3665 /CHRISTIAN CHACE/Supervisory Patent Examiner, Art Unit 3665
Prosecution Insights