DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Response to Arguments
3. Applicant’s arguments filed on 02/20/2026 with respect to claims 1-20 have been considered but are moot in view of the new ground(s) of rejection. In addition to, the Examiner maintained the reference of Zhu et al. (US 9,183,078 B1) since there is no further argument/s regarding to this reference.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
4. Claims 1, 2, 6-8, 10-12, 16-18, and 20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Zhu et al. (US 9,183,078 B1) "herein after as Zhu " in view of Russell at al. (US 2014/0195729 A1) "herein after as Russell."
As per claim 1: Zhu substantially teaches or discloses a memory unit comprising (see Fig. 1, memory 103): a first plurality of random access memories (RAMs) configured to store data bits of a data word written to the memory unit, the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n), and Fig. 4); and a second plurality of RAMs configured to store bits of ECC codes (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4), each ECC code associated with a unique group of the data bits (see abstract, and column 2, lines 1-6, herein An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word, and Figs. 3 & 4), such that the bits of each ECC code are distributed over the second plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach a reporting circuit configured, during a read operation, to report back to a processor a single bit error correction or a double bit error detection for the data word. However, Russell in the same the field of endeavor teaches a reporting circuit configured, during a read operation, to report back to a processor a single bit error correction or a double bit error detection for the data word (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu with the teachings of Russell by reporting back to a processor a single bit error correction or a double bit error detection for the data word. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor a single bit error correction or a double bit error detection for the data word would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 2: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 6: Zhu teaches that wherein the ECC codes are configured to detect and correct a single bit error in the group of data bits and to detect a double bit error in the group of data bits (see column 6, lines 60-66, herein the ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code, SEC-DED, or Bose-Chaudhuri-Hocquenghem (BCH) code. Using enhanced Hamming code or SEC-DED to protect a data block may provide the data block with 1-bit error correction and 2-bit error detection).
As per claim 7: Zhu teaches that further comprising a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 7, lines 1-4, herein the ECC controller may generate a 6-bit ECC segment for a 1-byte block of data using enhanced Hamming code, which provides 1-bit error correction and 2-bit error detection for the 1 byte of data).
As per claim 8: Zhu teaches that wherein the ECC codes are Hamming codes (see column 6, lines 60-62, herein The ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code).
As per claim 10: An error resistant memory system comprising one or more of the memory units of claim 1 (see Fig. 1, system 100).
As per claim 11: Zhu teaches or discloses a processing system comprising (see Fig. 1, memory 103): at least one processor configured to execute mission software (see Fig. 1, a central processing unit (CPU) 110); and an error resistant memory system (see Fig. 1, memory 103 & memory controller 101) coupled to the processor (see Fig. 1, CPU 110) and comprising one or more memory units (column 5, lines 39-43, and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); the memory units configured to store a data word written by the processor to the memory system, the memory units comprising: a first plurality of random access memories (RAMs) configured to store data bits of the data word, the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); and a second plurality of RAMs configured to store bits of ECC codes (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4), each ECC code associated with a unique group of the data bits (see abstract, and column 2, lines 1-6, herein An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word, and Figs. 3 & 4), such that the bits of each ECC code are distributed over the second plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach reporting circuit configured, during a read operation, to report back to the processor a single bit error correction or a double bit error detection for the data word. However, Russell in the same the field of endeavor teaches reporting circuit configured, during a read operation, to report back to the processor a single bit error correction or a double bit error detection for the data word (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu with the teachings of Russell by reporting back to a processor a single bit error correction or a double bit error detection for the data word. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor a single bit error correction or a double bit error detection for the data word would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 12: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 16: Zhu teaches that wherein the error resistant memory system further comprises a reporting circuit configured to report, to the processor, a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 7, lines 1-4, herein the ECC controller may generate a 6-bit ECC segment for a 1-byte block of data using enhanced Hamming code, which provides 1-bit error correction and 2-bit error detection for the 1 byte of data).
As per claim 17: Zhu teaches or discloses a method for providing radiation hardened memory, the method comprising: storing data bits in a first plurality of random access memories (RAMs) of a memory unit, the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); generating error correction codes (ECC codes), each of the ECC codes associated with a unique group of the data bits (see column 3, lines 44-50, herein generate error checking and correcting (ECC) information for the data word, the data word and ECC information forming an encoded word, and distribute bits of the encoded word across a plurality of concurrently accessible memory devices in accordance with one or more indications specifying a number of the bits of the encoded word to store in a wordline of each of the plurality of concurrently accessible memory devices); and storing bits of the ECC codes in a second plurality of RAMs of the memory unit (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4) such that the bits of the ECC codes are distributed over the second plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation. However, Russell in the same the field of endeavor teaches reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of ***with the teachings of *** by reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 18: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 20: Zhu teaches that wherein the ECC codes are configured to detect and correct a single bit error in the group of data bits and to detect a double bit error in the group of data bits, and the method further comprises reporting a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 6, lines 60-66, herein the ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code, SEC-DED, or Bose-Chaudhuri-Hocquenghem (BCH) code. Using enhanced Hamming code or SEC-DED to protect a data block may provide the data block with 1-bit error correction and 2-bit error detection).
5. Claim(s) 3-5, 13-15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu, in view of Russell in further view of Bandholz (US 2022/0190846 A1).
As per claims 3, 13, and 19: Zhu-Russell as combined substantially teaches or discloses wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits (Zhu, see column 6, lines 9-13, herein the memory devices 103(1), 103(2) to 103(n) may be ×8 memory devices. Each ×8 memory device has a data width of 8 bits. A set of four ×8 memory devices may form a rank to provide access to 32 bits of data at a time). Zhu-Russell as combined does not explicitly teach the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. However, Bandholz in the same the field of endeavor teaches the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits (see paragraph [0027], herein the memory controller 20 transmits the 64-bit data portions sequentially as part of the multiphase transaction. In each phase, the memory controller 20 transmits the 64-bit data portion along the data path 42, along with some of the ECC bits (no greater than 7 ECC bits) and one inversion bit, and Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits would have improved the error detection and correction capability.
As per claims 4 and 14: Zhu-Russell as combined teaches that wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits (Zhu, see column 6, lines 5-6, herein A set of sixteen ×4 memory devices may form a rank to provide access to 64 bits of data at a time). Zhu-Russell as combined does not explicitly teach second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits. Zhu does not explicitly teach the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. However, Bandholz in the same the field of endeavor teaches second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits (see paragraph [0028], herein the diagram generally shows that in each phase 32, a total of eight ECC bits are available per phase 32. Since only 9 ECC bits are required per block 30, a total of 7 spare bits per block 30 are available. The ECC bits and remaining (spare) bits may be distributed in any of a variety of ways. As diagrammed, one inversion bit is transmitted per phase, which leaves a total of 7 or fewer ECC bits per phase that may be used for error correction. For example, the 9 ECC bits may be distributed among the two phases 32 with 5 ECC bits sent in Phase 1 and 4 ECC bits sent in Phase 2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits would have improved the error detection and correction capability.
As per claims 5 and 15: Zhu-Russell as combined does not explicitly teach wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits. However, Bandholz in the same the field of endeavor teaches second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits (see paragraph [0016], A memory controller may generate ECC bits for a chunk of data that is larger than the 64-bit data path, such as a 128-bit chunk of data. The 128-bit chunk may be protected using fewer than the 16 ECC total bits that would be available over two phases. For example, applying SECDED, only 9 ECC bits may be required to protect the 128-bit chunk , and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits would have improved the error detection and correction capability.
6. Claim 9 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Zhu in view of Russell in further view of Imel (US 20220190846 A1).
As per claim 9: Zhu-Russell as combined does not teach wherein the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits. However, Imel in the same the field of endeavor teaches wherein the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits (see paragraph [0016], herein Hamming codes can correct a single bit error at any location in a data word and detect up to two random bit errors in the word. For such SECDED codes, the Hamming distance is equal to four, and the minimum number of parity check bits required corresponds to the relationship: log.sub.2(n)+2 (n-k)). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Imel by including the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits would have improved the error detection and correction efficiency.
Examiner Notes
7. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
8. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/OSMAN ALSHACK/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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