DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
2. Claims 1-20 are presented for examination.
Request for Continued Examination
3. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 08/26/2026 has been entered.
Response to Arguments
4. Applicant’s argument filed on 08/26/2026 with respect claims 1-20 have been fully considered but they are not persuasive.
The applicant contends that the office action fails to teach or suggest the limitation of "a first plurality of random access memories (RAMs), physically separated from each other and configured to store data bits of a data word written to the memory unit." As recited in independent claims 1, 11, and 17.
Examiner respectfully disagrees and asserts that Zhu et al. (US 9,183,078 B1) in column 2, lines 37-43 and column 10, lines 27-43 teaches such limitation. For example, as an example, a 72-bit encoded word may be protected from unrecoverable data loss using an advanced ECC memory that includes 4 memory modules each having 18 chips. The encoded word may be divided into four 18-bit segments. Each 18-bit segment may be stored in a separate memory module. Each bit of an 18-bit segment may be stored in a separate memory chip. See column 2, lines 37-43.
In some implementations, the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information. In some implementations, the ECC controller distributes the bits of the data word and the ECC information such that one or more memory devices store only checksum bits, and the remaining memory devices store both data bits and ECC bits. For a memory device that stores both data bits and ECC bits, the data bits and ECC bits are stored in separate locations of the memory device. In some implementations, the data bits and ECC bits may be stored in different banks of the memory device. In some implementations, the data bits and ECC bits may be stored in the same wordline of the memory device, but in different sections of the wordline. See column 10, lines 27-43.
Also, the applicant contends that the cited references fail to teach or suggest the feature of “wherein the unique group of the data bits comprises the data bits stored in a column of the first plurality of RAMs, such that the bits of each ECC code are distributed over the second plurality of RAMs in a column corresponding to the column of the first plurality of RAMs.” As recited in independent claims 1, 11, and 17.
The examiner respectfully disagrees and asserts the Zhu et al. (US 9,183,078 B1) in column 1, lines 53-67 & column 2 lines 1-11, column 8, lines 29-67 & column 9 lines 1-20, and column 11, lines 61-67 & column 12, lines 12-21 teaches such limitation. For example, A memory module may include ECC capability to detect and correct bit errors in data stored in the memory module. A memory module that includes ECC capability (referred to as an ECC memory) encodes data by generating ECC bits, e.g., redundancy bits or parity bits, that are stored along with the data in the memory module. A conventional ECC memory may use a Single Error Correct, Double Error Detect (SEC-DED) algorithm to detect and correct single-bit errors and detect, but not correct, double-bit errors in a data word. A data word as used in this disclosure is the largest unit of data, not including the ECC bits, that can be transferred to and from a memory module in a single operation. Enhanced Hamming Code, which generates 7 Hamming check bits and 1 parity bit, may be used to provide SEC-DED protection for each data word. An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word. For example, an ECC memory that can provide 8 ECC bits for each 32-bit data word may include a 40-bit wide interface to access a 40-bit encoded word. Similarly, an ECC memory that can provide 8 ECC bits for each 64-bit data word may include a 72-bit wide interface to access a 72-bit encoded word. See column 1, lines 53-67 & column 2 lines 1-11
FIG. 3 shows an example of data formats of encoded words that include interleaved data and interleaved ECC information. The ECC controller receives a data word 302. The data word 302 may be a 64-bit data word (the bytes are referenced in FIG. 3 using base 4 numbers). The ECC controller generates ECC information 304 for the data word 302. The ECC controller may generate 6 bits of the ECC information 304 for each byte of the data word 302 to generate 48 bits of ECC information. The ECC controller interleaves a first portion 306 of the data word and a second portion 308 of the data word. For example, the ECC controller may interleave bytes D00 and D10 as follows: D00′[7:0]={D10[6], D00[6], D10[4], D00[4], D10[2], D00[2], D10[0], D00[0]} and D10′[7:0]={D10[7], D00[7], D10[5], D00[5], D10[3], D00[3], D10[1], D00[1]}. The ECC controller may interleave bytes D01, D11, D02, D12, D03, D13 in a similar fashion to generate D01′, D11′, D02′, D12′, D03′, D13′. In this implementation, the odd bits of the first portion 306 and the odd bits of the second portion 308 are interleaved, and the even bits of the first portion 306 and the even bits of the second portion 308 are interleaved. The ECC controller interleaves a first portion 310 of the ECC information and a second portion 312 of the ECC information. For example, the ECC controller may interleave the 6 bits of ECC information E00 and the 6 bits of ECC information E10 as follows: E00″[5:0]={E10[4], E00[4], E10[2], E00[2], E10[0], E00[0]} and E10′[5:0]={E10[5], E00[5], E10[3], E00[3], E10[1], E00[1]}. The ECC controller may interleave E01, E11, E02, E12, E03, E13 in a similar fashion to generate E01′, E11′, E02′, E12′, E03′, E13′. In this implementation, the odd bits of the first portion 310 and the odd bits of the second portion 312 are interleaved, and the even bits of the first portion 310 and the even bits of the second portion 312 are interleaved. The ECC controller forms two 64-bit encoded words 314 and 316. Encoded word 314 includes a first portion of the interleaved data word and a first portion of the interleaved ECC information. Encoded word 316 includes a second portion of the interleaved data word and a second portion of the interleaved ECC information. The two encoded words 314 and 316 may each include a 1-byte checksum CS0 and CS1, which will be described in more detail later in this disclosure. Interleaving the data word and ECC information distributing the interleaved data word and ECC information across two encoded words may provide protection for some multi-bit error situations. For example, the encoded word 314 may have 2 bits that are in error. The error may have occurred when the encoded word 314 was being read from a memory, and bits D00′[0] and D00′[1] became flipped while being read. The 2-bit error in the encoded word 314 may not be correctable without de-interleaving the encoded word. Since bit D00′[0] corresponds to bit D00[0] of the first portion 306 and bit D00′[1] corresponds to bit D10[0] of the second portion 308, the encoded word 314 is de-interleaved to generate the first portion 306 and the second portion 308. The first portion 306 has 1 bit that is in error, and the second portion 308 has 1 bit that is in error. The single bit errors in each of the first portion 306 and the second portion 308 can now be corrected. See column 8, lines 29-67 & column 9 lines 1-20.
FIGS. 8 and 9 show examples of memories that store checksum bits in one or more memory devices and both data bits and ECC bits in each of the remaining memory devices. FIG. 8 shows an example of a 72-bit memory 802 that includes nine ×8 memory devices, e.g., Device 0, Device 1, Device 2, Device 3, Device 4, Device 5, Device 6, Device 7, and Device 8, that are in the same rank. Each of the nine memory devices has multiple banks, e.g., Bank0 to Bank7. Each of the memory devices provides access to 8 bits at a time. The set of nine memory devices provides access to 72 bits at a time. Device 0 through Device 7 are designated for storing both data bits and ECC bits. Device 8 is designated for storing checksum bits CS. Each memory device that stores both data bits and ECC bits may store the bits as shown in either device 804 or device 806. In device 804, the data bits and ECC bits are stored in different banks of the memory device. In device 806, the data bits and ECC bits are stored in the same wordline, but in different sections of the wordline. The ratio of data bits to ECC bits is based on the ECC algorithm used to generate the ECC bits. For example, the ratio may be 8 bytes of data to 1 byte of ECC, 8 bytes of data to 2 bytes of ECC, 4 bytes of data to 1 byte of ECC, and other ratios of data to ECC. The data and the ECC may each be distributed evenly across the eight memory devices that are designated for storing both data and ECC bits. Other implementations for distributing the bits across memory devices that are designated for storing both data and ECC bits are possible. See column 11, lines 61-67 & column 12, lines 12-21. For the Applicant’s convenience, see Fig. 3& 8 are reproduced below.
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
5. Claims 1, 2, 6-8, 10-12, 16-18, and 20 are rejected under 35 U.S.C. 103 (a) as being unpatentable over Zhu et al. (US 9,183,078 B1) "herein after as Zhu " in view of Russell at al. (US 2014/0195729 A1) "herein after as Russell."
As per claim 1: Zhu substantially teaches or discloses a memory unit comprising (see Fig. 1, memory 103): a first plurality of random access memories (RAMs) physically separated from each other (see column 2, lines 40-43, herein the encoded word may be divided into four 18-bit segments. Each 18-bit segment may be stored in a separate memory module. Each bit of an 18-bit segment may be stored in a separate memory chip , and Fig. 4) and configured to store data bits of a data word written to the memory unit, the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n), and Fig. 4); and a second plurality of RAMs configured to store bits of ECC codes (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4), each ECC code associated with a unique group of the data bits (see abstract, and column 2, lines 1-6, herein An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word, and Figs. 3 & 4), wherein the unique group of the data bits comprises the data bits stored in a column of the first plurality of RAMs (see column 1, lines 1-7, An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word; and column 12, lines 7-12, herein Each memory device that stores both data bits and ECC bits may store the bits as shown in either device 804 or device 806. In device 804, the data bits and ECC bits are stored in different banks of the memory device. In device 806, the data bits and ECC bits are stored in the same wordline, but in different sections of the wordline), such that the bits of each ECC code are distributed over the second plurality of RAMs in a column corresponding to the column of the first plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach a reporting circuit configured, during a read operation, to report back to a processor a single bit error correction or a double bit error detection for the data word. However, Russell in the same the field of endeavor teaches a reporting circuit configured, during a read operation, to report back to a processor a single bit error correction or a double bit error detection for the data word (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu with the teachings of Russell by reporting back to a processor a single bit error correction or a double bit error detection for the data word. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor a single bit error correction or a double bit error detection for the data word would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 2: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 6: Zhu teaches that wherein the ECC codes are configured to detect and correct a single bit error in the group of data bits and to detect a double bit error in the group of data bits (see column 6, lines 60-66, herein the ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code, SEC-DED, or Bose-Chaudhuri-Hocquenghem (BCH) code. Using enhanced Hamming code or SEC-DED to protect a data block may provide the data block with 1-bit error correction and 2-bit error detection).
As per claim 7: Zhu teaches that further comprising a reporting circuit configured to report a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 7, lines 1-4, herein the ECC controller may generate a 6-bit ECC segment for a 1-byte block of data using enhanced Hamming code, which provides 1-bit error correction and 2-bit error detection for the 1 byte of data).
As per claim 8: Zhu teaches that wherein the ECC codes are Hamming codes (see column 6, lines 60-62, herein The ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code).
As per claim 10: An error resistant memory system comprising one or more of the memory units of claim 1 (see Fig. 1, system 100).
As per claim 11: Zhu teaches or discloses a processing system comprising (see Fig. 1, memory 103): at least one processor configured to execute mission software (see Fig. 1, a central processing unit (CPU) 110); and an error resistant memory system (see Fig. 1, memory 103 & memory controller 101) coupled to the processor (see Fig. 1, CPU 110) and comprising one or more memory units (column 5, lines 39-43, and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); the memory units configured to store a data word written by the processor to the memory system, the memory units comprising: a first plurality of random access memories (RAMs) configured to store data bits of the data word, the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); and a second plurality of RAMs physically separated from each other (see column 2, lines 40-43, herein the encoded word may be divided into four 18-bit segments. Each 18-bit segment may be stored in a separate memory module. Each bit of an 18-bit segment may be stored in a separate memory chip , and Fig. 4) and configured to store bits of ECC codes (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4), each ECC code associated with a unique group of the data bits (see abstract, and column 2, lines 1-6, herein An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word, and Figs. 3 & 4), wherein the unique group of data bits comprises the data bits stored in a column of the first plurality of RAMs (see column 1, lines 1-7, An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word; and column 12, lines 7-12, herein Each memory device that stores both data bits and ECC bits may store the bits as shown in either device 804 or device 806. In device 804, the data bits and ECC bits are stored in different banks of the memory device. In device 806, the data bits and ECC bits are stored in the same wordline, but in different sections of the wordline), such that the bits of each ECC code are distributed over the second plurality of RAMs in a column corresponding to the column of the first plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach reporting circuit configured, during a read operation, to report back to the processor a single bit error correction or a double bit error detection for the data word. However, Russell in the same the field of endeavor teaches reporting circuit configured, during a read operation, to report back to the processor a single bit error correction or a double bit error detection for the data word (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu with the teachings of Russell by reporting back to a processor a single bit error correction or a double bit error detection for the data word. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor a single bit error correction or a double bit error detection for the data word would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 12: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four of the data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 16: Zhu teaches that wherein the error resistant memory system further comprises a reporting circuit configured to report, to the processor, a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 7, lines 1-4, herein the ECC controller may generate a 6-bit ECC segment for a 1-byte block of data using enhanced Hamming code, which provides 1-bit error correction and 2-bit error detection for the 1 byte of data).
As per claim 17: Zhu teaches or discloses a method for providing radiation hardened memory, the method comprising: storing data bits in a first plurality of random access memories (RAMs) physically separated from each other of a memory unit (see column 2, lines 40-43, herein the encoded word may be divided into four 18-bit segments. Each 18-bit segment may be stored in a separate memory module. Each bit of an 18-bit segment may be stored in a separate memory chip , and Fig. 4), the data bits distributed over the first plurality of RAMs (see abstract, column 3, lines 51-52, herein wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices, column 5, lines 39-42, herein the memory 103 may include any memory system for which it is desirable to provide ChipRaid-ECC capability. In some implementations, the memory 103 may include a volatile memory, such as random-access memory (RAM), and Fig. 1, the memory 103 includes multiple memory devices 103(1), 103(2) to 103(n)); generating error correction codes (ECC codes), each of the ECC codes associated with a unique group of the data bits (see column 3, lines 44-50, herein generate error checking and correcting (ECC) information for the data word, the data word and ECC information forming an encoded word, and distribute bits of the encoded word across a plurality of concurrently accessible memory devices in accordance with one or more indications specifying a number of the bits of the encoded word to store in a wordline of each of the plurality of concurrently accessible memory devices); wherein the unique group of the data bits comprise the data bits stored in a column of the first plurality of RAMs (see column 1, lines 1-7, An ECC memory typically includes 9 chips per side for storing data and ECC bits that can be used to detect and correct errors in the data. An ECC memory can also include an interface that can provide simultaneous access of a data word and its corresponding ECC bits. A data word and its corresponding ECC bits are referred to as an encoded word; and column 12, lines 7-12, herein Each memory device that stores both data bits and ECC bits may store the bits as shown in either device 804 or device 806. In device 804, the data bits and ECC bits are stored in different banks of the memory device. In device 806, the data bits and ECC bits are stored in the same wordline, but in different sections of the wordline); storing bits of the ECC codes in a second plurality of RAMs of the memory unit (see abstract, column 3, lines 52-54, herein bits of the ECC information are to be stored in two or more memory devices of the plurality of memory devices, and column 6, lines 41-47, herein the ECC controller generates one or more bits of ECC information for the data word. The ECC information may include ECC bits that can be used to detect and correct bit errors in the data word. The ECC controller may generate a set of ECC bits (referred to ECC segments) for each data block (e.g., 1 byte of data, 4 bytes of data, 8 bytes of data, 16 bytes of data, or other numbers of bytes of data) of the data word, and Fig. 4) such that the bits of the ECC codes are distributed over the second plurality of RAMs in a column corresponding to the column of the first plurality of RAMs (see column 4, lines 3-4, herein ChipRaid-ECC may distribute a data word and ECC information across memory chips in a same rank; column 10, lines 6-12, herein the ECC controller distributes the encoded word and the one or more checksums across memory devices in the same rank. The ECC controller may distribute the bits of the encoded word across the memory devices such that each memory device stores more than one bit of the data word, the ECC information, or both the data word and the ECC information; and column 12, lines 16-21; and Figs. 3-4).
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Zhu does not explicitly teach reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation. However, Russell in the same the field of endeavor teaches reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation (see paragraph [0023], herein the data input and the corresponding correction code are both provided to and stored within the cache memory 210 (e.g., an n+k bit wide input). The ECC logic 216 also receives data and correction code information from the cache memory 210 (e.g., an n+k bit wide data output) and generates a data output (e.g., an n-bit wide data output) after confirming that the data is correct based upon the correction code information. In certain embodiments, the ECC logic 216 uses a hamming code to provide single error correction and double error detection (SEC-DED), and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of ***with the teachings of *** by reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the reporting back to a processor any single bit error corrections and/or double bit error detections resulting from a read operation would have improved the error resilience of memories (see paragraph [0005] of Russell).
As per claim 18: Zhu teaches that wherein each of the RAMs of the first plurality of RAMs is configured to store four data bits, and each of the RAMs of the second plurality of RAMs is configured to store four bits of the ECC codes (see column 10, lines 27-32, herein the ECC controller distributes the bits of the data word across a first set of the memory devices that are designated for storing only data bits and distributes the bits of the ECC information across a second, different set of memory devices that are designated for storing only ECC information; column 10, lines 52-55, herein the encoded word 404 includes a 32-bit data word, 24 ECC bits, and an 8-bit checksum. Each 6 bits of the 24 ECC bits correspond to a byte of the data word, e.g., E0[0:5] corresponds to D0[7:0], and Fig. 4)).
As per claim 20: Zhu teaches that wherein the ECC codes are configured to detect and correct a single bit error in the group of data bits and to detect a double bit error in the group of data bits, and the method further comprises reporting a single bit error correction or a double bit error detection, resulting from a read operation on the memory unit (see column 6, lines 60-66, herein the ECC controller 102 may use any suitable ECC algorithm to generate the ECC segments for each data block of the data word, such as enhanced Hamming code, SEC-DED, or Bose-Chaudhuri-Hocquenghem (BCH) code. Using enhanced Hamming code or SEC-DED to protect a data block may provide the data block with 1-bit error correction and 2-bit error detection).
6. Claim(s) 3-5, 13-15, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu, in view of Russell in further view of Bandholz (US 2022/0190846 A1).
As per claims 3, 13, and 19: Zhu-Russell as combined substantially teaches or discloses wherein the first plurality of RAMs comprises eight RAMs such that the memory unit is configured to store 32 of the data bits (Zhu, see column 6, lines 9-13, herein the memory devices 103(1), 103(2) to 103(n) may be ×8 memory devices. Each ×8 memory device has a data width of 8 bits. A set of four ×8 memory devices may form a rank to provide access to 32 bits of data at a time). Zhu-Russell as combined does not explicitly teach the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. However, Bandholz in the same the field of endeavor teaches the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits (see paragraph [0027], herein the memory controller 20 transmits the 64-bit data portions sequentially as part of the multiphase transaction. In each phase, the memory controller 20 transmits the 64-bit data portion along the data path 42, along with some of the ECC bits (no greater than 7 ECC bits) and one inversion bit, and Fig. 1). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits would have improved the error detection and correction capability.
As per claims 4 and 14: Zhu-Russell as combined teaches that wherein the first plurality of RAMs comprises 16 RAMs such that the memory unit is configured to store 64 of the data bits (Zhu, see column 6, lines 5-6, herein A set of sixteen ×4 memory devices may form a rank to provide access to 64 bits of data at a time). Zhu-Russell as combined does not explicitly teach second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits. Zhu does not explicitly teach the second plurality of RAMs comprise five RAMs such that the memory unit is configured to store four ECC codes of length five bits. However, Bandholz in the same the field of endeavor teaches second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits (see paragraph [0028], herein the diagram generally shows that in each phase 32, a total of eight ECC bits are available per phase 32. Since only 9 ECC bits are required per block 30, a total of 7 spare bits per block 30 are available. The ECC bits and remaining (spare) bits may be distributed in any of a variety of ways. As diagrammed, one inversion bit is transmitted per phase, which leaves a total of 7 or fewer ECC bits per phase that may be used for error correction. For example, the 9 ECC bits may be distributed among the two phases 32 with 5 ECC bits sent in Phase 1 and 4 ECC bits sent in Phase 2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits would have improved the error detection and correction capability.
As per claims 5 and 15: Zhu-Russell as combined does not explicitly teach wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits. However, Bandholz in the same the field of endeavor teaches second plurality of RAMs comprise six RAMs such that the memory unit is configured to store four ECC codes of length six bits (see paragraph [0016], A memory controller may generate ECC bits for a chunk of data that is larger than the 64-bit data path, such as a 128-bit chunk of data. The 128-bit chunk may be protected using fewer than the 16 ECC total bits that would be available over two phases. For example, applying SECDED, only 9 ECC bits may be required to protect the 128-bit chunk , and Fig.2). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Bandholz by including wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the wherein the first plurality of RAMs comprises 32 RAMs such that the memory unit is configured to store 128 of the data bits, and the second plurality of RAMs comprise seven RAMs such that the memory unit is configured to store four ECC codes of length seven bits would have improved the error detection and correction capability.
7. Claim 9 is rejected under 35 U.S.C. 103 (a) as being unpatentable over Zhu in view of Russell in further view of Imel (US 20220190846 A1).
As per claim 9: Zhu-Russell as combined does not teach wherein the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits. However, Imel in the same the field of endeavor teaches wherein the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits (see paragraph [0016], herein Hamming codes can correct a single bit error at any location in a data word and detect up to two random bit errors in the word. For such SECDED codes, the Hamming distance is equal to four, and the minimum number of parity check bits required corresponds to the relationship: log.sub.2(n)+2 (n-k)). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the system of Zhu-Russell as combined with the teachings of Imel by including the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the ECC codes are of length log2(N) + 2 bits, where N is the number of bits in the group of the data bits would have improved the error detection and correction efficiency.
Examiner Notes
8. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Prior Art
9. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OSMAN M ALSHACK/Examiner, Art Unit 2112
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