Prosecution Insights
Last updated: April 19, 2026
Application No. 18/304,001

VIA GROUND STRUCTURES

Final Rejection §103
Filed
Apr 20, 2023
Examiner
MOVVA, AMAR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cisco Technology Inc.
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
2y 11m
To Grant
94%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
606 granted / 764 resolved
+11.3% vs TC avg
Strong +15% interview lift
Without
With
+15.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
18 currently pending
Career history
782
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
13.8%
-26.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 764 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 5-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 11510937 A, please note for the purpose of the rejection the corresponding US PG PUB 2024/0222888 will be referenced, note both publications refer to same application number CN 202111081149.3) in view of Kim (US 10,595,394). [claim 1] Cao discloses an apparatus (figs. 8, 13, 4, 5) comprising: a semiconductor device substrate material (11, fig. 4, base structure 11 is capable of acting as a substrate material for a semiconductor device such as when the base structure acts a connector between a mother board and a daughter board [0051]); a first signal conductor (top 12, fig. 8, [0053]) incorporated into the semiconductor device substrate material; a second signal conductor (bottom 12, fig. 8, [0053]) incorporated into the semiconductor device substrate material immediately adjacent to the first signal conductor; and a ground conductor (16, fig. 8, [0065]) incorporated into the semiconductor device substrate material between the first signal conductor and the second signal conductor (fig. 8), wherein the ground conductor comprises a first elongated portion and a second elongated portion arranged at an angle relative to the first elongated portion (T-shaped ground via 16, fig. 8). Cao, however, does not expressly disclose a repeating alternating signal and ground conductor configuration. Kim discloses a interconnect apparatus with a repeating alternating signal and ground conductor configuration (see e.g. top row direction of alternating signal and ground vias, fig. 1A). It would have been obvious to one of ordinary skill in the art before the time of filing to have used a repeating alternating signal and ground conductor configuration in Cao’s device in order to allow for a greater number of signal interconnections to be able to be formed in a single area. With this modification Cao discloses: [claim 1] a third signal conductor (the third signal conductor would be the next adjacent signal conductor above the top signal conductor 12 in fig. 8 which upon modification have a repeating configuration) incorporated into the semiconductor device substrate material immediately adjacent to the first signal conductor, and a second ground conductor (the second ground conductor would be the next adjacent ground conductor above the ground conductor 16 in fig. 8 which upon modification would have a repeating configuration) incorporated into the semiconductor device substrate material between the first signal conductor and the third signal conductor, wherein the second ground conductor comprises a third elongated portion and a fourth elongated portion arranged at an additional angle relative to the third elongated portion (T-shaped ground via 16 of the next adjacent ground via, fig. 8). [claim 2] The apparatus of claim 1, wherein the first signal conductor comprises a first circular signal via and the second signal conductor comprises a second circular signal conductor (fig. 8). [claim 3] The apparatus of claim 1, wherein the ground conductor comprises a ground via [0065]. [claim 5] The apparatus of claim 1, wherein the first elongated portion and the second elongated portion form an "L" shape, a "V" shape or a "T" shape (T-shaped ground via 16, fig. 8). [claim 6] The apparatus of claim 1, wherein the first signal conductor comprises a first signal via of a first differential pair of signal vias (e.g. top signal vias/holes on top side of T shaped grounding via holes on each side of the structure in fig. 13) and the second signal conductor comprises a second signal via of a second differential pair of signal vias (e.g. bottom signal vias/holes on bottom side of T shaped grounding via holes on each side of the structure in fig. 13). [claim 7] The apparatus of claim 1, wherein the apparatus comprises a ball grid array (e.g as can be seen in fig. 13, the signal vias may be the ball grid array when combined with the ground vias on either side of the structure, moreover the solder posts 22 also can be part of the ball grid array) . [claim 8] The apparatus of claim 1, wherein the apparatus comprises a board-to-board connection area of a printed circuit board (direct connection may be optionally realized by the lack of spring arm or solder ball, see e.g. [0089]). [claim 9] The apparatus of claim 1, wherein the apparatus comprises a backplane connector area of a printed circuit board (the connector apparatus connects to a motherboard and daughter board where the motherboard acts as a backplane, see e.g. [0051][0042]). [claim 10] The apparatus of claim 1, wherein the apparatus comprises a high speed digital change layer (the signal vias are capable of high speed digital link between the daughter and motherboard see e.g. [0051][0042] which describes the high speed system, also note that the term high speed is subjective term which using the broadest reasonable interpretation that the instant signal vias are capable of). Claim(s) 16-21, 24, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 11510937 A, please note for the purpose of the rejection the corresponding US PG PUB 2024/0222888 will be referenced, note both publications refer to same application number CN 202111081149.3) in view of Kim (US 10,595,394). [claim 16] Cao discloses an apparatus (figs. 8, 13, 4, 5) comprising: a semiconductor device substrate material (11, fig. 4, base structure 11 is capable of acting as a substrate material for a semiconductor device such as when the base structure acts a connector between a mother board and a daughter board [0051]); a first signal conductor (top 12, fig. 8, [0053]) incorporated into the semiconductor device substrate material; a second signal conductor (bottom 12, fig. 8, [0053]) incorporated into the semiconductor device substrate material immediately adjacent to the first signal conductor; and a ground conductor (16, fig. 8, [0065]) incorporated into the semiconductor device substrate material between the first signal conductor and the second signal conductor (fig. 8), wherein the ground conductor comprises a first elongated portion and a second elongated portion arranged at an angle relative to the first elongated portion (T-shaped ground via 16, fig. 8). Cao, however, does not expressly disclose a repeating alternating signal and ground conductor configuration. Kim discloses a interconnect apparatus with a repeating alternating signal and ground conductor configuration (see e.g. top row direction of alternating signal and ground vias, fig. 1A). It would have been obvious to one of ordinary skill in the art before the time of filing to have used a repeating alternating signal and ground conductor configuration in Cao’s device in order to allow for a greater number of signal interconnections to be able to be formed in a single area. With this modification Cao discloses: [claim 16] a repeating pattern (the additional signal and ground conductors would be disposed adjacent to the first signal conductor which upon modification have a repeating configuration) formed in the semiconductor device substrate material, wherein the repeating pattern comprises plurality of signal conductors and a plurality of conductors (the additional signal and ground conductors would be disposed adjacent to the first signal conductor which upon modification have a repeating configuration), wherein the at least one ground conductor comprises a first elongated portion and a second elongated portion arranged at an angle relative to the first elongated portion (T-shaped grounding via, fig. 8, 13). [claim 17] The apparatus of claim 16, wherein the at least one signal conductor comprises a circular via (fig. 8). [claim 18] The apparatus of claim 16, wherein the repeating pattern forms a ball grid array pinfield (e.g. as can be seen in fig. 13, the signal vias may be the ball grid array when combined with the ground vias on either side of the structure, moreover the solder posts 22 also can be part of the ball grid array). [claim 19] The apparatus of claim 16, wherein the repeating pattern forms a board-to- board connector area or a backplane connector area of a printed circuit board (the connector apparatus connects to a motherboard and daughter board where the motherboard acts as a backplane, see e.g. [0051][0042]). [claim 20] The apparatus of claim 16, wherein the repeating pattern forms a high speed digital change layer (the signal vias are capable of high speed digital link between the daughter and motherboard see e.g. [0051][0042] which describes the high speed system, also note that the term high speed is subjective term which using the broadest reasonable interpretation that the instant signal vias are capable of.). [claim 21] The apparatus of claim 16, wherein the angle at which the second elongated portion is arranged relative to the first elongated portion is a right angle (fig. 8). [claim 24] The apparatus of claim 16, wherein a first end of the first elongated portion intersects a second end of the second elongated portion (side end of one elongated portion intersects top/bottom end of the other elongated portion fig. 8) . [claim 25] The apparatus of claim 16, wherein a first midpoint of the first elongated portion intersects a second midpoint of the second elongated portion (fig. 8). Claim(s) 4, 22, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cao (CN 11510937 A, please note for the purpose of the rejection the corresponding US PG PUB 2024/0222888 will be referenced, note both publications refer to same application number CN 202111081149.3) in view of Kim (US 10,595,394). Cao discloses the apparatus of claims 1 and 16 but does not expressly disclose that the grounding via has an elongated X shape with one direction having an acute angle (as opposed to the disclosed T shape). Nevertheless it would have been obvious to one of ordinary skill in the art to have made Cao’s grounding in an elongated X shape , since it has been held that a particular shape configuration (elongated X shape) was a matter of choice which a person of ordinary skill in the art before the time of filing would have found obvious absent evidence that the particular configuration was critical. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Specifically applicant specification in [0031] that the various shapes X, +, V, L, T may in the alternative be used to improve crosstalk therefore there is no criticality in an X shape vs a T shape. With this modification Cao discloses: [claim 4] The apparatus of claim 1, wherein the first elongated portion and the second elongated portion form an "X" shape or a cross shape (upon modification an elongated X shape is realized). [claim 22] The apparatus of claim 16, wherein the angle at which the second elongated portion is arranged relative to the first elongated portion is an oblique angle (upon modification an elongated X shape is realized). [claim 23] The apparatus of claim 22, wherein the oblique angle is an acute angle (upon modification an elongated X shape is realized). Response to Arguments Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any rejection applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMAR MOVVA whose telephone number is (571)272-9009. The examiner can normally be reached Monday-Friday 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMAR MOVVA/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Apr 20, 2023
Application Filed
Oct 14, 2025
Non-Final Rejection — §103
Dec 12, 2025
Applicant Interview (Telephonic)
Dec 12, 2025
Examiner Interview Summary
Jan 12, 2026
Response Filed
Mar 05, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
94%
With Interview (+15.1%)
2y 11m
Median Time to Grant
Moderate
PTA Risk
Based on 764 resolved cases by this examiner. Grant probability derived from career allow rate.

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