DETAILED ACTION
This office action is in response to applicant’s amendment filed on March 31, 2026. Claims 1-21 are under consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2022/0179159 A1, herein “Wu”) in view of Hong et al. (KR-20170077541-A, herein “Hong”) and Cao et al. (CN-102347248-A, herein “Cao”).
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Regarding claims 1 and 13, Wu discloses in Fig. 9A an apparatus comprising:
a circuit interconnection structure (land grid array LGA substrate 904, Para [0197]) comprising a first surface and a second surface, with a cavity (opening 910) formed through an entire thickness between the first surface and the second surface;
a first integrated circuit (laser modules 212) comprising a first port (conductively coupled to (904 via submount), the first integrated circuit mounted on the first surface of the circuit interconnection structure;
a device carrier (photonic integrated circuit 902 and HBM 906) comprising a first portion of the device carrier that fits within at least a portion of the cavity (high bandwidth memory HBM stack or digital modules 906), wherein a second portion (902) of the device carrier rigidly connected to the first portion of the device carrier is attached to the first surface of the circuit interconnection structure (LGA 904); and
a device (HBM 906) positioned within the first portion of the device carrier and mounted to a mounting surface of the device carrier that is substantially parallel to the first surface of the circuit interconnection structure (904), the device comprising a second integrated circuit (HBM stack of two or more dynamic random access memory integrated circuits, Para [0046]) comprising a second port (conductive contacts, Para [0217]).
Wu further teaches photonic computing platform integrates photonic integrated circuit, hybrid/digital analog integrated circuits, laser modules etc. in an environment that is compatible with various thermal dissipation mechanisms that result in more controllable thermal environment (Para [0131]). This disclosures suggests Wu’s design is concerned with the devices with varying thermal expansion coefficient that can affect device integrity.
Regarding the method steps of claims 13-21, the steps of forming, mounting, inserting, positioning etc. is not patentably distinct from the apparatus. The assembly of the apparatus would necessarily disclose the generic method steps of claims 13-21. Therefore, the rejection of the method claims are included with the rejection of the device claims.
However, Wu does not explicitly teach the device mounted to the mounting surface such that thermal expansion of the device carrier offsets thermal expansion of the device to maintain a substantially constant relative position between the first port and the second port across the temperature range.
Hong teaches a heat dissipating carrier surface shown in module (100). The device carrier comprising a first portion of the device carrier (chip carrier 140) that fits within at least a portion of a cavity (formed on the insulating substrate 120). The chip carrier (140) is connected to the first portion of the device carrier (radiator plate 110 and insulating substrate 120) is attached to the first surface via bonding layer (150). This configuration would providing the thermal expansion of the device carrier (140) offsets thermal expansion of the device (130) to maintain a substantially constant relative position in accordance to the offsetting difference as disclosed in the Specification (Para [0042]: The carrier thermal expansion contribution of the gullwing arm 117A from the carrier 118A expanding downward and the device thermal expansion contribution on the second gullwing arm 117B expanding upward). Since Hong’s device carrier is formed in the cavity of the substrate having the bottom surface and the side walls, and a portion extending over the top surface of the substrate and mounted by bonding material inasmuch as applicant’s device carrier, the examiner considers the offset thermal expansion function of the Hong’s carrier would function and perform in the same manner as broadly recited in claim 1.
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Wu in view of Hong do not explicitly teach the device mounted to the mounting surface over a temperature range of -40 degrees Celsius to 85 degrees Celsius.
Cao teaches the temperature range -40 degrees centigrade to 85 degrees centigrade is industrial temperature rating of semiconductor device along with the vehicle temperature rating devices in the temperature range of -40 degrees centigrade to 125 degrees centigrade (Para [0003]).
It would have been obvious to one having ordinary skill at the time of filing to recognize the heat dissipating carrier (140) of Hong would be modifiable to the cavity in Wu’s invention by mounting it in the cavity accommodating digital module 906 and mounting the two side arms of the carrier (140) to the surface of the circuit interconnection structure (Wu’s LGA substrate 904). Since the semiconductor device of Hong and photonic integrated circuits of Wu fall into the general category of semiconductor components, it would have been obvious to have the components be thermally stable and functioning in the industrial temperature range of -40 degrees Celsius to 85 degrees Celsius to conform with industry standards. Therefore, the modified invention of Wu with the teachings of Hong and Cao would necessarily yield a device carrier offsets thermal expansion of the device to maintain a substantially constant relative position between the first port and the second port across the temperature range. One would be motivated to mount the integrated circuit indirectly to the substrate via a rigid metal carrier to prevent thermal expansion mismatch between the device and substrate and to prevent deterioration of the bonding interface between the device and the substrate that is caused by excessive thermal energy.
Claims 2 and 14, Wu in view of Hong and Cao (herein “Wu / Hong / Cao”) teach the invention of claim 1, Wu further discloses the connection between the first port of the first integrated circuit (laser module 212) and the second port of the second integrated circuit (HBM 906) comprises an optical beam that is emitted from the first port of the first integrated circuit (laser 212 to prism 230, and coupled into the device carrier 902 also PIC device) and received into the second port of the second integrated circuit (Para [0204]-[0205], [0208], [0215]-[0217]),.
Claim 3, Wu / Hong / Cao teach the invention of claim 2, Wu further discloses the apparatus comprising one or more optical components mounted to the device carrier and configured to focus, expand, or change a direction of propagation the optical beam (lens 220 focuses (collimates) the beam, prism 230 changes a direction of the beam, and the grating coupler 228 expands the beam into various wavelengths).
Claims 4 and 15, Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the connection between the first port of the first integrated circuit and the second port of the second integrated circuit comprises a wirebond connected to the first port of the first integrated circuit and connected to the second port of the second integrated circuit (Para [0202]-[0203]).
Claim 5, Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the connection between the first port of the first integrated circuit (laser 212) and the second port of the second integrated circuit (HBM 906) corresponds to an alignment between the first port of the first integrated circuit (laser 212) and the second port of the second integrated circuit associated with a specific height relative to the first surface. Fig. 9A shows the components (212, 220, 230) are calibrated, aligned, and mounted/couple to the first surface of the circuit interconnection structure which have waveguides therein for receiving the incoming light signals (Para [0125]).
Claims 6 and 16, Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the circuit interconnection structure (904) comprises a printed circuit board (PCB). Land Grid Array (LGA 904), similar to LGA substrate 202, provides an array of contacts 204 on the top (e.g., in the form of pins, or contacts for solder-based mounting) for providing electrical connectivity for an array of input/output signals provided by an array of contacts 206 that form an LGA footprint on the bottom of the interposer 208. Alternatively, any other surface-mount packaging structure can be used to provide electrical input/output connectivity. Thus, the examiner considers the LGA 202 or 904 to be a PCB (Para [0197]).
Claims 7 and 17, Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the PCB comprises at least one of a high-density interconnect (HDI) PCB, a high-density buildup (HDBU) substrate, a semi-rigid flex, or a substrate-like PCB (SLP). Wu discloses the LGA substrate can have an interposer 208 on the top of the LGA substrate that provides electrical signal paths for communication among different devices that are mounted on top of the interposer wherein the input/output connectivity is arrayed (Para [0197]). Thus, the examiner considers the LGA in Wu discloses high-density interconnect.
Regarding claims 8, 9, and 18, , Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the device comprises a temperature control element thermally, thermos-electric cooler, (heat sink not shown in the figure or another thermoelectric cooler 272 shown in Fig. 2G) coupled to the mounting surface of the device carrier and thermally coupled to the second integrated circuit (Fig. 2G, Para [0200]).
Claims 10 and 19, Wu / Hong / Cao teach the invention of claim 1, Wu further discloses the circuit interconnection structure provides one or more electrical connections with one or more respective electrical contacts on the first integrated circuit (Para [0197]).
Claims 11 and 20, Wu / Hong / Cao teach the invention of claim 1, Hong further discloses the second portion of the device carrier (140) rigidly connected to the first portion (bottom portion) of the device carrier comprises a structure extending horizontally from a substantially vertical wall of the device carrier, wherein the device carrier comprises a gull-wing shape (Description of the Preferred Embodiments translation, 7th full paragraph) including at least two laterally extending portions (Hong: Fig. 1). Regarding the limitation “that provide respective reference planes for alignment of the first port and the second port” is considered intended use.
Claims 12 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wu / Hong / Cao as applied to claim 11 above, and further in view of Suppelsa et al. (US 5,455,446, herein “Suppelsa”.
Claims 12 and 21. Wu / Hong / Cao teach the invention of claim 11 and 20, but do not teach the wall of the device carrier comprises a plurality of materials having different coefficients of thermal expansion, the plurality of materials being selected to provide an effective coefficient of thermal expansion of the device carrier that offsets thermal expansion of the device to maintain alignment between the first port and the second port over the temperature range.
Suppelsa teaches an IC package having a “gull wing” or s-shaped lead (Fig. 5) that combines two or more electrically conductive metals or alloys, each metal having different TCE (“coefficient of thermal expansion”) values. A second metal section is attached to the upper and lower surfaces of the leads so that it becomes an integral part of the lead. The second metal has a TCE larger than the TCE of the first lead material and is located on the upper surface and the lower surface of the lead in the precise location of the inner radius surface of the S shaped lead such that it will straight and lengthen the lead during increased thermal excursions, and better match the thermal expansion of the printed wiring board to which it is interconnected. Conversely, the second metal having a TCE less than the TCE of the first lead material will cause the S shape lead to bend and shorten during increased thermal excursions (Col. 2, lines 1-27).
It would have been obvious to one having ordinary skill at the time of filing to recognize the general teaching of Suppelsa for manipulating the length of the lead to lengthen or shorten by selecting plurality of materials to provide and effective coefficient of thermal expansion that offsets thermal expansion of the device would be modifiable by selected the metal or metal alloy with the known CTE selected to offset the expansion within the cavity of the device carrier. The chosen selection of plurality of material would better ensure alignment of the first and second port in the invention of Wu / Hong / Cao since Wu / Hong / Cao being practitioner in the art would be well aware of coefficient of thermal expansion would cause optical misalignment in the photonic integrated circuits. One would be motivated selected plurality of materials to provide an effective coefficient of thermal expansion of the device carrier that offsets thermal expansion of the device to prolong the life time of the device.
Response to Arguments
Applicant’s arguments with respect to claims 1-21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. PTO-892:U: White paper on Deploying Industrial Temperature Rated Equipment for Reliable Network Operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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