CTNF 18/305,525 CTNF 78634 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al. (U.S. Patent Application Publication 20190164944) in view of Chen et al. (U.S. Patent Application Publication 20220365294) . PNG media_image1.png 364 470 media_image1.png Greyscale As per claims 1 and 15, Chae et al. disclose a microelectronic assembly, comprising: a first layer (23) comprising a first array of micro light-emitting diodes (micro-LEDs) ( ¶ [0192]); a second layer (33) comprising a second array of micro-LEDs ( ¶ [0192]); a third layer (43) (see Fig. 2B above; ¶¶ [0186-0189]; [0195]); and a pillar electrically coupled to the first layer and the second layer, in the form of through-hole vias (63b 65a, 65b, 67a, and 67b) wherein the first layer is substantially parallel to the second layer or the third layer, and the pillar extends in a direction substantially perpendicular to the first layer, the second layer, or the third layer ¶¶ [205-210]). Chae et al. do not explicitly disclose a third layer between the first layer and the second layer, the third layer comprising an optical interconnect. Chen et al. teach an optical interconnect in the form of polymer waveguide layers. Chen et al. further teach an optical interconnect disposed between adjacent layers (¶¶ [0056-0061]; Fig. 2E (not shown above)]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the microelectronic assembly of Chae et al. such that it incorporated an optical interconnect between a first layer and second layer. One would have been motivated to make such a modification in order to integrate the optical interconnect of Chen et al. within the stacked structure taught by Chae et al., to provide optical connectivity and communication of signals between layers (¶¶ [0056-0061]; Fig. 2E (not shown above)]). [Examiner note : Claims 1 and 15 are treated together because claim 15 recites the same stacked microelectronic assembly of claim 1 using broader structural terminology and the combined teachings applied to claim 1 likewise teach the corresponding light source structures, optical interconnect structure and electrically conductive structure recited in claim 15 ] . As per claim 8, Chae et al. disclose a microelectronic assembly comprising: a first sub-assembly, the first sub-assembly comprising a first array of micro light-emitting diodes (micro-LEDs) and a second array of micro-LEDs, wherein Chae et al. disclosed stacked micro-LED structures including first LED stack (23), second LED stack (33) and third LED stack (43)(see Fig. 2B above; ¶¶ [0191-0194]), a second sub-assembly over the first sub-assembly in a direction, wherein the stacked LED structures are vertically arranged to overlap one another (see Fig. 2B; ¶ [0194]); a structure crossing the first sub assembly and the second subassembly in the direction, in the form of through-hole vias (63b, 65a, 65b, 67a and 67b) extending through the stacked structure (see Fig. 2B; ¶¶ [0205-0210]). Chae et al. do not explicitly disclose a first optical interconnect plane between first array of micro-LEDs and the second array of micro-LEDs and a second optical interconnect plane between a third array of micro-LEDs and fourth array of micro-LEDs. Chen et al. teach an optical interconnect in the form of polymer waveguide layers. Chen et al. further teach an optical interconnect disposed between adjacent layers (¶¶ [0056-0061]; Fig. 2E (not shown above)]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the microelectronic assembly of Chae et al. such that it incorporated the optical interconnect of Chen et al. between adjacent layers of stacked LED structures of Chae et al., including between arrays within the stacked sub-assemblies. One would have been motivated to make such a modification in order to provide optical connectivity and communication of signals between layers (¶¶ [0056-0061]; Fig. 2E (not shown above)]) . As per claims 2-4 and 12-13, further recite: additional stacked layers, channels between adjacent layers or sub-assemblies, and selected channel spacing, including fluid-filled channels. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the microelectronic assembly of Chae et al. such that it incorporated additional stacked layers, channels between adjacent layers or sub-assemblies, and selected channel spacing, including fluid-filled channels, as predictable modifications of the stacked microelectronic assembly of Chae et al. and Chen et al. in order to accommodate the arrangement of additional components within the assembly. As per claims 5-7, further recite: selecting the orientation of the micro-LED arrays relative to a surface of a layer and to position semiconductor devices between layers or on an optical interconnect layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the microelectronic assembly of Chae et al. to select the orientation of the micro-LED arrays relative to a surface of a layer and to position semiconductor devices between layers or on an optical interconnect layer as predictable implementations of the stacked microelectronic architecture taught by Chae et al. and Chen et al. in order to electrically interconnect components of the assembly. As per claims 9-11 and 14, further recite: providing additional sub-assemblies, layers, optical elements, and electrical coupling structures. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the microelectronic assembly of Chae et al. to provide additional sub-assemblies, layers, optical elements, and electrical coupling structures as predictable extensions of the stacked microelectronic assembly taught by Chae et al. and Chen et al. in order to increase functionality of the assembly. As per claims 16-20, further recite: associating light emitters with optical lenses, implementing the light emitters as micro-LEDs, providing communication between light source structures, orienting emitter-bearing surfaces toward one another, and selecting a particular spacing between structures. It would have been obvious to one having ordinary skill in the art at the time the invention was made to further modify the microelectronic assembly of Chae et al. to associate light emitters with optical lenses, implement the light emitters as micro-LEDs, provide communication between light source structures, orient emitter-bearing surfaces toward one another, and select a particular spacing between structures as predictable design choices for a stacked light-emitting assembly. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY D THOMAS whose telephone number is (571)272-2496. The examiner can normally be reached M-F: 9 AM - 5 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, David Makiya can be reached at 571-272-2273. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COURTNEY D THOMAS/Primary Examiner, Art Unit 2884 Application/Control Number: 18/305,525 Page 2 Art Unit: 2884 Application/Control Number: 18/305,525 Page 3 Art Unit: 2884 Application/Control Number: 18/305,525 Page 4 Art Unit: 2884 Application/Control Number: 18/305,525 Page 5 Art Unit: 2884 Application/Control Number: 18/305,525 Page 6 Art Unit: 2884 Application/Control Number: 18/305,525 Page 7 Art Unit: 2884
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