DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, lines 2-3 recite: “and the third portion has a width less than the width of the second portion of the gate structure.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, there is insufficient antecedent basis for “the width of the second portion of the gate structure”. Does “the width of the second portion of the gate structure” mean the “the maximal width of the second portion of the gate structure” or is it referring to a different width of the second portion of the gate structure? For purpose of examination, the Examiner is interpreting lines 2-3 of claim 12 as reciting “and the third portion has a width less than the maximal width of the second portion of the gate structure” because of this ambiguity.
Regarding claim 13, lines 1-2 recite: “wherein the width of the third portion of the gate structure is less than the width of the first portion of the gate structure.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, there is insufficient antecedent basis for “the width of the first portion of the gate structure”. Does “the width of the first portion of the gate structure” mean the “the maximal width of the first portion of the gate structure” or is it referring to a different width of the first portion of the gate structure? For purpose of examination, the Examiner is interpreting lines 1-2 of claim 13 as reciting “wherein the width of the third portion of the gate structure is less than the maximal width of the first portion of the gate structure” because of this ambiguity.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, and 11-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0299086 A1 (Yu).
Regarding claim 1, Yu discloses, A device (FIG. 2A) comprising:
a first semiconductor layer (first semiconductor layer (R1); FIG. 2A; [0019]) over a substrate (substrate (100); FIG. 2A; [0018]), the first semiconductor layer (R1) comprising a first channel region (first channel region (CHd); FIG. 2A; [0022]) and first source/drain regions (first source/drain regions (SDd); FIG. 2A; [0022]) on opposite sides of the first channel region (CHd);
a dielectric layer (dielectric layer (110); FIG. 2A; [0028]) over the first semiconductor layer (R1);
a second semiconductor layer (second semiconductor layer (R2); FIG. 2A; [0019]) over the dielectric layer (110), the second semiconductor layer (R2) comprising a second channel region (second channel region (CHu); FIG. 2A; [0022]) and second source/drain regions (second source/drain regions (SDu); FIG. 2A; [0022]) on opposite sides of the second channel region (Chu); and
a gate structure (gate structure (GE and GI); FIG. 2A; [0023]; [0036]) comprising a first portion (first annotated FIG. 2A, below) extending in the dielectric layer (110), a second portion (first annotated FIG. 2A, below) wrapping around the first channel region (CHd) of the first semiconductor layer (R1), and a third portion (first annotated FIG. 2A, below) wrapping around the second channel region (CHu) of the second semiconductor layer (R2), wherein the first portion (first annotated FIG. 2A, below) of the gate structure (GE and GI) in the dielectric layer (110) has a maximal width (maximal width (W1); first annotated FIG. 2A, below) less than a maximal width (maximal width (W2); first annotated FIG. 2A, below) of the second portion (first annotated FIG. 2A, below) of the gate structure (GE and GI) wrapping around the first channel region (CHd).
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Regarding claim 3, Yu discloses, The device (FIG. 2A) of claim 1, wherein the first portion (first annotated FIG. 2A, above) of the gate structure (GE and GI) in the dielectric layer (110) has the maximal width (width (W1); first annotated FIG. 2A, above) less than a maximal width (width (W3); first annotated FIG. 2A, above) of the third portion (first annotated FIG. 2A, above) of the gate structure (GE and GI) wrapping around the second channel region (CHu).
Regarding claim 4, Yu discloses, The device (FIG. 2A) of claim 1, wherein the first source/drain regions (SDd) are of n-type ([0022]), and the second source/drain regions (SDu) are of p-type ([0022]).
Regarding claim 5, Yu discloses, The device (FIG. 2A) of claim 1, wherein the first source/drain regions (SDd) are of p-type ([0022]—“However, example embodiments are not limited thereto”—meaning that first source/drain regions (SDd) can be p-type), and the second source/drain regions (SDu) are of n-type ([0022]—“However, example embodiments are not limited thereto”—meaning that second source/drain regions (SDu) can be n-type).
Regarding claim 11, Yu discloses, A device (FIG. 2A) comprising:
an n-type transistor (n-type transistor (R1); FIG. 2A; [0019]; [0022]) over a substrate (substrate (100); FIG. 2A; [0018]);
a p-type transistor (p-type transistor (R2); FIG. 2A; [0019]; [0022]) at a different level height (FIG. 2A) than the n-type transistor (R1);
a dielectric layer (dielectric layer (110); FIG. 2A; [0028]) interposing the n-type transistor (R1) and the p-type transistor (R2) (FIG. 2A); and
a gate structure (gate structure (GE and GI); FIG. 2A; [0023]; [0036]) shared by the n-type transistor (R1) and the p-type transistor (R2), wherein the gate structure (GE and GI) comprises a first portion (second annotated FIG. 2A, below) around a channel region (channel region (CHd); FIG. 2A; [0022]) of the n-type transistor (R1) and a second portion (second annotated FIG. 2A, below) around a channel region (channel region (CHu); FIG. 2A; [0022]) of the p-type transistor (R2), and the second portion (second annotated FIG. 2A, below) of the gate structure (GE and GI) has a maximal width (maximal width (W2); second annotated FIG. 2A, below) greater than a maximal width (maximal width (W1); second annotated FIG. 2A, below) of the first portion (second annotated FIG. 2A, below) of the gate structure (GE and GI).
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Regarding claim 12, Yu discloses, The device (FIG. 2A) of claim 11, wherein the gate structure (GE and GI) further comprises a third portion (second annotated FIG. 2A, above) in the dielectric layer (110), and the third portion (second annotated FIG. 2A, above) has a width (width (W3); second annotated FIG. 2A, above) less than the width (W2) of the second portion (second annotated FIG. 2A, above) of the gate structure (GE and GI).1
Regarding claim 13, Yu discloses, The device (FIG. 2A) of claim 12, wherein the width (W3) of the third portion (second annotated FIG. 2A, above) of the gate structure (GE and GI) is less than the width (W1) of the first portion (second annotated FIG. 2A, above) of the gate structure (GE and GI).2
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the Examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, as applied to claim 1, above, in view of US 2023/0420518 A1 (Kim).
Regarding claim 6, Yu does not appear to explicitly disclose, The device of claim 1, further comprising:
first dopant source layers sandwiching the first source/drain regions of the first semiconductor layer, the first dopant source layers having a same dopant as the first source/drain regions.
However, in analogous art, Kim discloses, that it is well-known that a device (device (100); FIGs. 2B and 2C; [0022]) that can be predicably formed to include first dopant source layers (first dopant source layers (132, 134 and/or 138); annotated FIG. 2B, below, and FIG. 2C; [0041]) sandwiching first source/drain regions (first source/drain regions (136); annotated FIG. 2B, below, and FIG. 2C; [0041]) of first semiconductor layer (first semiconductor layer (130); annotated FIG. 2B, below, and FIG. 2C; [0041]). Kim also discloses that it is well-known that first dopant source layers (132, 134 and/or 138) can be predicably formed to have a same dopant (dopant (p-type dopant); [0051]; [0057]) as first source/drain regions (136). Kim additionally discloses that it is well-known that first source layers (132, 134 and/or 138) improve reliability of device (100) during manufacture by reducing failures such as the deterioration of first semiconductor layer (130) resulting from external attacks or the occurrence of a short circuit between first semiconductor layer (130) and a conductive region adjacent thereto ([0064]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Kim before him/her, that the device (FIG. 2A) of Yu can be predicably formed to include first dopant source layers sandwiching the first source/drain regions of the first semiconductor layer of Yu, as taught by Kim, the first dopant source layers having a same dopant as the first source/drain regions of Yu, as also taught by Kim, thereby improving reliability of the device (FIG. 2A) of Yu during manufacture by reducing failures such as the deterioration of first semiconductor layer (R1) resulting from external attacks or the occurrence of a short circuit between first semiconductor layer (R1) and a conductive region adjacent thereto, as additionally taught by Kim.
Regarding claim 7, Yu does not appear to explicitly disclose, The device of claim 6, further comprising:
second dopant source layers sandwiching the second source/drain regions of the second semiconductor layer, the second dopant source layers having a same dopant as the second source/drain regions.
However, in analogous art, Kim discloses, that it is well-known that a device (device (100); FIGs. 2B and 2C; [0022]) that can be predicably formed to include second dopant source layers (second dopant source layers (132, 134 and/or 138); annotated FIG. 2B, above, and FIG. 2C; [0041]) sandwiching second source/drain regions (second source/drain regions (136); annotated FIG. 2B, above, and FIG. 2C; [0041]) of second semiconductor layer (second semiconductor layer (130); annotated FIG. 2B, above, and FIG. 2C; [0041]). Kim also discloses that it is well-known that second dopant source layers (132, 134 and/or 138) can be predicably formed to have a same dopant (dopant (p-type dopant); [0051]; [0057]) as second source/drain regions (136). Kim additionally discloses that it is well-known that second source layers (132, 134 and/or 138) improve reliability of device (100) during manufacture by reducing failures such as the deterioration of second semiconductor layer (130) resulting from external attacks or the occurrence of a short circuit between second semiconductor layer (130) and a conductive region adjacent thereto ([0064]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Kim before him/her, that the device (FIG. 2A) of Yu can be predicably formed to include second dopant source layers sandwiching the second source/drain regions of the second semiconductor layer of Yu, as taught by Kim, the second dopant source layers having a same dopant as the second source/drain regions of Yu, as also taught by Kim, thereby improving reliability of the device (FIG. 2A) of Yu during manufacture by reducing failures such as the deterioration of second semiconductor layer (R2) resulting from external attacks or the occurrence of a short circuit between second semiconductor layer (R2) and a conductive region adjacent thereto, as additionally taught by Kim.
Regarding claim 8, Yu in view of Kim does not appear to explicitly disclose, The device of claim 7, wherein the first dopant source layers and the second dopant layers are of opposite conductivity types.
However, there are a finite number of predicable solutions regarding the conductivity type of the first dopant source layers relative to the second dopant source layers—i.e., they can be the same or opposite (as recited in claim 8)—and, absent unexpected results, it would, therefore, have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try each of them with a reasonable expectation of success, one of which is: wherein the first dopant source layers and the second dopant layers are of opposite conductivity types, as recited in claim 8. See, MPEP 2143(E)—“Obvious To Try”—Choosing From a Finite Number of Identified, Predictable Solutions, With a Reasonable Expectation of Success.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kim, as applied to claim 7, above, and further in view of Shou et al., Feasibility Study of Single-Crystal Si Island Manufacturing by Microscale Printing of Nanoparticles and Laser Crystallization, August 23, 2019, American Chemical Society (ACS) Publications, ACS Applied Materials & Interfaces, pages 34416-34423 (Shou).
Regarding claim 9, Yu in view of Kim does not appear to explicitly disclose, The device of claim 7, further comprising:
a single-crystalline island between the dielectric layer and a lower one of the second dopant source layers.
However, in analogous art, Shou discloses that it is well-known that single-crystal islands can be predicably formed in an electronic device and that they provide high-performance devices due to their high mobility ([page 34416]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu, Kim, and Shou before him/her, that a single-crystalline island can be predicably formed between the dielectric layer (110) and a lower one of the second dopant source layers (132, 134 and/or 138) of Yu in view of Kim to provide high mobility in the device (FIG. 2A) of Yu in view of Kim, as taught by Shou.
Regarding claim 10, Yu in view of Kim and further in view of Shou discloses, The device (FIG. 2A) of claim 9, wherein the gate structure (GE and GI) further comprises a fourth portion (first annotated FIG. 2A, above) in the single-crystalline island, and the fourth portion (first annotated FIG. 2A, above) has a maximal width (width (W4)) greater than the maximal width (W1) of the first portion (first annotated FIG. 2A, above) of the gate structure (GE and GI).
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, as applied to claim 11, above, in view of Shou.
Regarding claim 14, Yu does not appear to explicitly disclose, The device of claim 11, further comprising:
a single-crystalline island on the dielectric layer.
However, in analogous art, Shou discloses that it is well-known that single-crystal islands can be predicably formed in an electronic device and that they provide high-performance devices due to their high mobility ([page 34416]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Shou before him/her, that a single-crystalline island can be predicably formed on the dielectric layer (110) of Yu to provide high mobility in the device (FIG. 2A) of Yu, as taught by Shou.
Regarding claim 15, Yu in view of Shou discloses, The device of claim 14, wherein the gate structure (GE and GI) further comprises a third portion (second annotated FIG. 2A, above) in the single-crystalline island, and the third portion (second annotated FIG. 2A, above) has a width (width (W3)) less than a width (W4) of the second portion (second annotated FIG. 2A, above) of the gate structure (GE and GI).
Claims 16, 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Seebauer et al., Formation of Ultra-Shallow Junctions, February 4, 2011,Comprehensive Semiconductor Science and Technology, Volume 4, pages 86-131 (Seebauer)
Regarding claim 16, Yu discloses, A method ([0075]) comprising:
forming a first epitaxial stack (first epitaxial stack (SDd); FIG. 2A; [0026]) on a substrate (substrate (100); FIG. 2A; [0018]), the first epitaxial stack (SDd) comprising first doped layers (first doped layers (n-type); [0026]) and a first semiconductor layer (first semiconductor layer (LSP1, LSP2 and/or LSP3); FIG. 2A; [0023]) interposing the first doped layers (n-type doped SDd), wherein the first semiconductor layer (LSP1, LSP2 and/or LSP3) has a top surface (third annotated FIG. 2A, below and paragraph [0025] of Applicant’s specification) covered by one of the first doped layers (n-type doped SDd);
forming a dielectric layer (dielectric layer (110); FIG. 2A; [0028]) over the first epitaxial stack (SDd);
forming a second epitaxial stack (second epitaxial stack (SDu); FIG. 2A; [0029]) over the dielectric layer (110), the second epitaxial stack (SDu) comprising second doped layers (second doped layers (p-type); [0029]) and a second semiconductor layer (second semiconductor layer (USP1, USP2 and/or USP3); FIG. 2A; [0023]) interposing the second doped layers (p-type doped SDu);
removing portions of the first doped layers (n-type doped SDd) and portions of the second doped layers (p-type doped SDu), such that a channel region (channel region (CHd); FIG. 2A; [0022]) of the first semiconductor layer (LSP1, LSP2 and/or LSP3) and a channel region (channel region (CHu); FIG. 2A; [0022]) of the second semiconductor layer (USP1, USP2 and/or USP3) are suspended above the substrate (100); and
forming a gate structure (gate structure (GE and GI); FIG. 2A; [0023]; [0036]) surrounding the channel region (channel region (CHd); FIG. 2A; [0022]) of the first semiconductor layer (LSP1, LSP2 and/or LSP3) and the channel region (channel region (CHu); FIG. 2A; [0022]) of the second semiconductor layer (USP1, USP2 and/or USP3).
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But Yu does not appear to explicitly disclose, performing a first annealing process to diffuse a first dopant from the first doped layers to source/drain regions of the first semiconductor layer and to diffuse a second dopant from the second doped layers to source/drain regions of the second semiconductor layer.
However, in analogous art, Seebauer discloses, that it is well-known that an annealing process can be predicably used to diffuse a dopant and thereby electrically activate the dopant resulting in charge carriers becoming available for current transport (page 109).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Seebauer before him/her, that it is well-known to perform a first annealing process to diffuse a first dopant (first dopant (n-type); [0026]) from the first doped layers of Yu to source/drain regions (source/drain regions (SDd); FIG. 2A; ([0022])) of the first semiconductor layer (LSP1, LSP2 and/or LSP3) of Yu, as taught by Seebauer, and to diffuse a second dopant (second dopant (p-type); [0029]) from the second doped layers of Yu to source/drain regions (source/drain regions (SDu); FIG. 2A; ([0022])) of the second semiconductor layer (USP1, USP2 and/or USP3) of Yu, as also taught by Seebauer, to electrically activate these dopants so that charge carriers become available for current transport, as additionally taught by Seebauer.
Regarding claim 17, Yu in view of Seebauer discloses, The method (0075]) of claim 16, wherein the first dopant (n-type) and the second dopant (p-type) are of opposite conductivity types.
Regarding claim 19, Yu in view of Seebauer discloses, The method ([0075]) of claim 16, further comprising:
forming a first source/drain contact (first source/drain contact (AC1); FIG. 2A; [0053]) on a first one of the source/drain regions (SDu) of the second semiconductor layer (USP1, USP2 and/or USP3) (FIG. 2A); and
forming a second source/drain contact (second source/drain contact (AC3); FIG. 2A; [0053]) extending through a second one of the source/drain regions (SDu) of the second semiconductor layer (USP1, USP2 and/or USP3) (FIG. 2A) to a first one of the source/drain regions (SDd) of the first semiconductor layer (LSP1, LSP2 and/or LSP3) (FIG. 2A).
Regarding claim 20, Yu in view of Seebauer discloses, The method ([0075]) of claim 19, further comprising:
forming contact spacers (contact spacers (110 and 120); FIG. 2A [0028]; [0031]) lining opposite sidewalls (fourth annotated FIG. 2A, below) of the second source/drain contact (AC3).
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Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Seebauer, as applied to claim 16, above, and further in view of Herman et al., Epitaxy Physical Principles and Technical Implementation, 2004, Springer-Verlag Berlin Heidelberg GmbH, Chapter 4 (Solid Phase Epitaxy), pages 45-62 (Herman).
Regarding claim 18, Yu in view of Seebauer discloses, The method ([0075]) of claim 16, further comprising:
depositing a non-single crystalline semiconductor material (non-single crystalline semiconductor material (ACL1); FIG. 5; [0078] ) in the hole (hole (RSR); FIG. 4; [0077]).
But Yu in view of Seebauer does not appear to explicitly disclose,
performing an etching process on the dielectric layer to form a hole in the dielectric layer; and
performing a second annealing process to crystallize the non-single crystalline semiconductor material into a single-crystalline semiconductor material, wherein the second epitaxial stack is formed on the single-crystalline semiconductor material.
However, Yu in view of Seebauer does disclose that it is well-known that an etching process can be predicably used to form a hole (hole (RSR); FIG. 4; [0077]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu and Seebauer before him/her, that an etching process can be predicably performed on the dielectric layer (110) thereof to form a hole in the dielectric layer (110) thereof with no change in the established function of etching. See, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods to Yield Predicable Results.
But Yu in view of Seebauer still does not appear to explicitly disclose, performing a second annealing process to crystallize the non-single crystalline semiconductor material into a single-crystalline semiconductor material, wherein the second epitaxial stack is formed on the single-crystalline semiconductor material.
However, in analogous art, Herman discloses, that it is well-known that an annealing process (i.e., heating) may be predicably performed to crystallize a non-single crystalline semiconductor material (e.g., a disordered amorphous material) into a single-crystalline semiconductor material (page 45).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu, Seebauer, and Herman before him/her, that a second annealing process can be predicably performed to crystallize the non-single crystalline semiconductor material (ACL1) of Yu in view of Seebauer into a single-crystalline semiconductor material, as taught by Herman, with no change in the established function of annealing (see MPEP 2143(A), above), wherein the second epitaxial stack (SDu) is formed on the single-crystalline semiconductor material (because second epitaxial stack (SDu) is over dielectric layer (110) and the single-crystalline semiconductor material is in a hole in dielectric layer (110)). See, MPEP 2143(A), above.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, as applied to claim 1, above.
Regarding claim 21, Applicant may argue that Yu does not specifically disclose, wherein the dielectric layer has a thickness measured in a direction perpendicular to the substrate greater than a than a thickness of the first source/drain regions measured in the direction.
However, there are a finite number of identified, predicable ways to fabricate a thickness of the dielectric layer (110) of Yu measured in a direction perpendicular to the substrate (100) thereof relative to a thickness of the first source/drain regions (SDd) of Yu measured in the direction—i.e., the thickness of the dielectric layer (110) of Yu measured in a direction perpendicular to the substrate (100) can be: (i) less than a thickness of the first source/drain regions (SDd) of Yu measured in the direction, (ii) the same as a thickness of the first source/drain regions (SDd) of Yu measured in the direction, or (iii) greater than a thickness of the first source/drain regions (SDd) of Yu measured in the direction—and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Yu before him/her to try each of these fabrication steps with a reasonable expectation of success, one of which is wherein the dielectric layer (110) has a thickness measured in a direction perpendicular to the substrate (100) greater than a than a thickness of the first source/drain regions (SDd) measured in the direction, as recited in claim 21. Please see, MPEP 2143(E), above.
Response to Arguments
Applicant’s amendment of independent claims 1, 11, and 16 and dependent claims 3 and 10; addition of new claim 21; and remarks with respect thereto in the “Amendment Under 37 C.F.R. § 1.111” filed on February 4, 2026 (hereinafter “the Response”) have been reviewed and considered by the Examiner. However, they are not deemed persuasive for at least the reasons provided above in the rejections of claims 1 and 3-21 in this Final Office Action and as discussed below.
For example, regarding amended independent claim 1, page 14 of the Response states:
However, as illustrated in Fig. 2A of Yu, the maximal width of the alleged first portion of gate structure is the same as the maximal width of the alleged second portion of gate structure, not less than the maximal width of the alleged second portion of gate structure as claimed.
The Examiner respectfully disagrees at least because the maximal width of the first portion of the gate structure and the maximal width of the second portion of the gate structure of Yu shown above, for example, in first annotated FIG. 2A thereof are not the same. Rather, as shown, for example, in first annotated FIG. 2A, above, the maximal width of the first portion of the gate structure is less than the maximal width of the second portion of the gate structure, as recited in amended independent claim 1.
As another example, regarding amended independent claim 11, pages 15-16 of the Response state:
However, as illustrated in Fig. 2A of Yu, the maximal width of the alleged second portion of gate structure is the same as the maximal width of the alleged first portion of gate structure, not greater than the maximal width of the alleged first portion of gate structure, as recited in amended claim 11.
The Examiner respectfully disagrees at least because the maximal width of the second portion of the gate structure and the maximal width of the first portion of the gate structure of Yu shown above, for example, in second annotated FIG. 2A thereof are not the same. Rather, as shown, for example, in second annotated FIG. 2A, above, the maximal width of the second portion of the gate structure is greater than the maximal width of the first portion of the gate structure, as recited in amended independent claim 11.
As an additional example, regarding amended independent claim 16, page 18 of the Response states:
However, as illustrated in FIG. 2A of Yu, the top surface of the alleged first semiconductor layer LSP1, LSP2 and/or LSP3 is entirely laterally offset from the alleged first doped layers SDb, not covered by one of the alleged first doped layers SDb, as recited in amended claim 16. Seebauer is merely cited to discuss an annealing process and thus does not cure this deficiency in Yu.
For at least these reasons, Applicant respectfully requests that the rejection of claim 16 be withdrawn and thus respectfully requests allowance of claim 16.
The Examiner respectfully disagrees at least because paragraph [0025] of Applicant’s specification makes it clear that spatially relative terms such as “top” recited in amended independent claim 16 regarding the “surface covered by one of the first doped layers” “are intended to encompass different orientations” including rotations of “90 degrees or at other orientations”, as shown, for example, in third annotated FIG. 2A of Yu, above. Paragraph [0025] of Applicant’s specification also makes it clear that “the spatially relative descriptors used herein may likewise be interpreted accordingly.“
Notwithstanding the above, in an effort to advance prosecution, the Examiner respectfully requests that Applicant please consider initiating a telephone interview with the Examiner to discuss amendments that Applicant would like to propose to overcome the rejection of claims 1 and 3-21 in this Final Office Action prior to submitting a written response thereto. The Examiner would welcome such a conversation and is available at the telephone number indicated below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of claim 12 under 35 U.S.C. 112(b) above for how this language of claim 12 is being interpreted for purpose of examination.
2 Please see the rejection of claim 13 under 35 U.S.C. 112(b) above for how this language of claim 13 is being interpreted for purpose of examination.