Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments, filed on 9/30/2025, have been received and made of record. In response to the most recent Office Action, dated 6/30/2025, claims 1, 2, 6, 12, 13, 16, 19, and 20 have been amended. Claims 1-20 are currently pending
Prior Office action contained objection to the specification for several informalities.
The application has been amended with paragraphs [0110]. Amendments address all of the
aforementioned objections. Specification objection has been withdrawn.
Prior Office action contained objections to the claims for several informalities. The
application has been amended with updated Claims, making modifications to Claim 6. Amendments
address all of the aforementioned objections, but do not change the scope of the claim language. Claim
objection has been withdrawn.
Prior Office action contained objections to the drawings for several informalities under 37 CFR 1.83(a) due to missing features. The application has been amended with updated Claims, making modifications to Claim 16 to address missing features. Amendments address all of the aforementioned drawing objections, but do not change the scope of the claim language. Drawing objection has been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1-18 and 20 have been considered but are
moot because the new ground of rejection does not rely on the combination of references applied in the
prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments with respect to claim 19 has been fully considered but they are not persuasive. Applicant argues that cited reference Jo et al. (US 20230067265) no longer reads on claim 19 after amendment, specifying component 710 is constructed of non-conductive dielectric material. While the amended claim 19 adds the distinction of being made of a conductive material. While examiner does acknowledge that reference paragraph [0175] does specify that component 710 is made of non-conductive dielectric material, Examiner notes, however, paragraph [0180] additionally teaches that the material of component 710 may be made of conductive material. Rejection is maintained, as the amendments to claim 19 are not sufficient to circumvent rejection. Maintained rejection to claim 19 will be made below, with clarifications made to address Applicant’s amendment.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Jo et al. (US 20230062765).
Regarding Claim 19, Jo et al. teaches:
An electronic device (Fig 3a, 300) comprising: a display (Fig 3a, 301); peripheral conductive housing structures (Fig 3a, 310, 320, 3211 and Fig 13a, 710, 730) mounted to the display (Fig 3a, 301) and extending along a periphery (Fig 3a) of the display ()Fig 3a, 301); an aperture defining a cavity (Fig 13a, 711) in the peripheral conductive housing structures; a first substrate (Fig 13a, Fig 8a, 590); a second substrate (Fig 13a, Fig 8a, 610) surface-mounted to the first substrate (Fig 13a, Fig 8a, 590), the second substrate (Fig 13a, Fig 8a, 610) being smaller (Fig 8a) than the first substrate (Fig 13a, Fig 8a, 590) and extending into the cavity (Fig 13a, 711); and an antenna (Fig 8b, 500) having a first patch (Fig 8a, 510) in the first substrate (Fig 13a, Fig 8a, 590) and a second patch (Fig 8a, 661) in the second substrate (Fig 13a, Fig 8a, 610), the antenna (Fig 8b, 500) being configured to convey radio-frequency signals through the aperture, wherein the second substrate (Fig 13a, Fig 8a 610) is interposed between (Fig 13A) conductive material (paragraph 180, 710 made of conductive material) in the peripheral conductive housing structure (Fig 3a, 310, 320, 3211 and Fig 13a, 710, 730).
Regarding Claim 20, Jo et al. teaches:
wherein the peripheral conductive housing structures (Fig 3a, 310, 320, 3211 and Fig 13a, 710, 730) comprise a first ledge and a second ledge, the display (Fig 3a, 301) is mounted to the first ledge (annotated Fig 3A, 13A and 13B), and the electronic device further comprises: a housing wall (Fig 3A, 311) mounted to the second ledge (annotated Fig 3A, 13A and 13B) opposite the display (Fig 3a, 301), wherein the first substrate (annotated Fig 3A, 13A and 13B, 590) is interposed between (paragraph 118, facing toward side, aligned with 711 on 310c) the first (annotated Fig 3A, 13A and 13B) and second ledges (annotated Fig 3A, 13A and 13B).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 202030062765) in view of Kim et al. (US 20190165449).
Regarding Claim 1, Jo et al. teaches:
An electronic device comprising: a first substrate (Fig 8a, 590); a second substrate(Fig 8a, 610) mounted to a surface (Fig 8a, 5901) of the first substrate (Fig 8a, 590) by an interconnect (Fig 8a, 5912 and 6112); a first patch (Fig 8a, 510) in the first substrate (Fig 8a, 590) and configured to radiate at a first frequency (Para 147); a first antenna feed terminal (see annotated Fig 8a) on the first patch (Fig 8a, 510); a second patch (Fig 8a, 661) in the second substrate (Fig 8a, 610) and overlapping the first patch in the first substrate, the second patch (Fig 8a, 661) being configured to radiate at a second frequency (Para 147); and a second antenna feed terminal (see annotated Fig 8a) on the second patch (Fig 8a, 661) and coupled (Coupled via 6612) to the interconnect (Fig 8a, 5912 and 6112); a first signal trace (Fig 8a, 5904) in the first substrate (Fig 8a, 590); a first conductive via (Fig 8a, 511) in the first substrate (Fig 8a, 590) that couples the first signal trace (Fig 8a, 5904) to the first antenna feed terminal (see annotated Fig 8a);
Jo et al. does not teach:
A capacitor in the first substrate and disposed on the first conductive via
Kim et al. does teach
A capacitor (Fig 2, 144a and 145a) in the first substrate (Fig 2, 141) and disposed on the first conductive via (Fig 2, 144b and 145b)
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “A capacitor in the first substrate and disposed on the first conductive via” as taught by Kim et al., in the electronic device of Jo et al. Doing so would allow one to filter a transmit signal or a receive signal in a specified frequency band, for desired frequency response. (Kim et al. paragraph 52).
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Regarding Claim 2, Jo et al. teaches:
Further comprising: a second signal trace (Fig 8a, 5905) in the first substrate (Fig 8a, 590); and a second conductive via (Fig 8a, 512) in the first substrate (Fig 8a, 590) that couples the second signal trace (Fig 8a, 5905) to the interconnect (Fig 8a, 5912 and 6112).
Regarding Claim 3, Jo et al. teaches:
Further comprising: ground traces (Fig 8a, G layers) in the first substrate (Fig 8a, 590), the first patch (Fig 8a, 510) being interposed between the ground traces (Fig 8a, G layers) and the surface (Fig 8a, 5901) of the first substrate (Fig 8a, 590).
Regarding Claim 4, Jo et al. teaches:
Wherein the second conductive via (Fig 8a, 512) extends through a hole (Fig 8a, 510a) in the first patch (Fig 8a, 510).
Regarding Claim 8, Jo et al. teaches:
Wherein the interconnect (Fig 8a, 5912 and 6112) comprises a solder ball (para 146, bonded through soldering).
Regarding Claim 9, Jo et al. teaches:
Wherein the second substrate (Fig 8a, 610) is smaller (Fig 8a) than the first substrate (Fig 8a, 590).
Regarding Claim 10, Jo et al. teaches:
further comprising: peripheral conductive housing structures (Fig 13a, 730 and 710); and an aperture (Fig 13a, 711) in the peripheral conductive housing structures (Fig 13a, 730 and 710), wherein the first patch (Fig 8a, 510) and the second patch (Fig 8a, 661) are aligned with the aperture (Fig 13a, 711) and the second substrate (Fig 13a, 610) protrudes into the aperture (Fig 13a, 711).
Regarding Claim 11, Jo et al. teaches:
wherein the first substrate (Fig 6b, 590) comprises a cavity (Fig 6b, 5901a) and the second substrate (Fig 6b, 610) is mounted to the surface (Fig 6b, 5901) of the first substrate (Fig 6b, 590) within the cavity (Fig 6b, 5901a).
Claims 5,6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 20230062765) in view of Kim et al. (US 20190165449) and further in view of Yetisir et al. (US 20190252800).
Regarding Claim 5, Jo et al. in view of Kim et al. does not disclose:
further comprising: a set of conductive vias that couples the first patch to the ground traces and that laterally surrounds the hole in the first patch.
Yetisir does teach:
further comprising: a set of conductive vias (Yetisir Fig 12A and 12C, 1257) that couples the first patch (Yetisir Fig 12A and 12C, 1223) to the ground traces (Yetisir Fig 12A and 12C, 1225) and that laterally surrounds the hole (annotated Yetisir 12A and 12C) in the first patch.
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “further comprising: a set of conductive vias that couples the first patch to the ground traces and that laterally surrounds the hole in the first patch.” as taught by Yetisir et al., in the electronic device of Jo et al. in view of Kim et al. Doing so would allow for the frequency of the first patch to be tuned while additionally shielding of the second conductive via feed (Yetisir Para 164).
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.
Regarding claim 6, Jo et al. in view of Kim et al. does not teach:
a parasitic patch in the first substrate and interposed between the first patch and the surface of the first substrate, wherein the second conductive via extends through a hole in the parasitic patch.
Yetisir et al. teaches:
further comprising: a parasitic patch (Yetisir Fig 12A, 1245 and Fig 6a, 645) in the first substrate (Yetisir Para 108) and interposed between the first patch (Yetisir Fig 12A, 1223 and Fig 6a, 623) and the surface of the first substrate, wherein the second conductive via (Yetisir Fig 12A, 1223 and Fig 6a, 656) extends through a hole (Annotated Yetisir Fig 12A) in the parasitic patch (Yetisir Fig 12A, 1245).
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “a parasitic patch in the first substrate and interposed between the first patch and the surface of the first substrate, wherein the second conductive via extends through a hole in the parasitic patch.” as taught by Yetisir et al., in the electronic device of Jo et al. in view of Kim et al. Doing so would allow for the parasitic patch to create a resonant cavity with the first patch, allowing for additional bandwidth tuning, and further isolation between the first patch and second patch antennas (Yetisir Para 132-136, Fig 6a, 631).
Examiner’s note: Yetisir’s specification denotes component 1245 as a ground reflector for the second patch antenna, 1243. While not explicitly stated as a “parasitic patch”, the placement and formfactor is shared with the Applicant’s claimed invention. Additionally, Paragraph 110 of Applicant’s Specification states “some or all of parasitic patch 60 and/or patch element 58-1 may form part of the reference ground (antenna ground) for patch element 58-2 at the resonant frequencies of patch element 58-2”. As such, the stated “ground reflector” of Yetisir is seen to have equivalent form factor, placement and functionality to the Applicant’s Parasitic Patch, despite the naming convention used.
Regarding claim 7, Jo et al. in view of Kim et al. does not teach:
wherein the set of conductive vias couples the parasitic patch to the first patch.
Yetisir et al. teaches:
wherein the set of conductive vias (Yetisir Fig 12A and 12C, 1257) couples (Annotated Yetisir Fig 12A and 12 C) the parasitic patch (Annotated Yetisir Fig 12A and 12C, 1245) to the first patch (Yetisir Fig 12A and 12C, 1223).
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “wherein the set of conductive vias couples the parasitic patch to the first patch.” as taught by Yetisir et al., in the electronic device of Jo et al. in view of Kim et al. Doing so would allow for the parasitic patch to further isolate the first patch and second patch, as well as form part of the reference ground for the second patch, in addition to allowing further impedance tuning of the second patch antenna (Yetisir Para 164).
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Claims 12-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 202030062765) in view of Rajagopalan et al. (US 20200021019).
Regarding Claim 12, Jo et al. teaches:
An electronic device comprising: a first substrate (Fig 8b, 590); a second substrate (Fig 8b, 610 OR Alternatively, Para 159 & Fig 10c, 610, 620 and 680) mounted to the first substrate (Fig 8b, 590); solder (para 146) that couples the first substrate to the second substrate; an antenna having a first patch (Fig 8b, 510) in the first substrate (Fig 8b, 590) and a second patch (Fig 8b, 661) in the second substrate (Fig 8b, 610), the second patch overlapping the first patch (Fig 8b); first (Fig 8b, 5904) and second signal traces (Fig 8b, 5905) in the first substrate (Fig 8b, 590); first (Fig 8b, 511) and second conductive vias (Fig 8b, 512) in the first substrate (Fig 8b, 590), wherein the first conductive via (Fig 8b, 511) couples the first signal trace (Fig 8b, 5904) to the first patch (Fig 8b, 590): a third conductive via (Fig 8b, 6611) in the second substrate (Fig 8b, 610); the third conductive via (Fig 8b, 6611) couples the solder (Fig 8b and Para 146); The second conductive via (Fig 8b, 512) couples the second signal trace (Fig 8b, 5905) to the solder (Fig 8b and Para 146).
Jo et al. does not teach:
a conductive trace in the second substrate; and third and fourth conductive vias in the second substrate, wherein the third conductive via is laterally offset from the fourth conductive via, the third conductive via couples the conductive trace, the fourth conductive via is coupled to the second patch, the conductive trace couples the third conductive via to the fourth conductive via,
Rajagopalan et al. does teach:
a conductive trace (Fig 7, 134) in the second substrate (Fig 7, 122-4, 122-5 and 122-6); and third (Fig 7, 124b) and fourth conductive vias (Fig 7, 138) in the second substrate (Fig 7, 122-4, 122-5 and 122-6), wherein the third conductive via (Fig 7, 124b) is laterally offset (Fig 7, offset by 136) from the fourth conductive via (Fig 7, 138), the third conductive via (Fig 7, 124b) couples the conductive trace (Fig 7, 134), the fourth conductive via (Fig 7, 138) is coupled to the second patch (Fig 7, 104b), the conductive trace (Fig 7, 134) couples the third conductive via (Fig 7, 124b) to the fourth conductive via (Fig 7, 138),
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “a conductive trace in the second substrate; and third and fourth conductive vias in the second substrate, wherein the third conductive via is laterally offset from the fourth conductive via, the third conductive via couples the conductive trace, the fourth conductive via is coupled to the second patch, the conductive trace couples the third conductive via to the fourth conductive via,” as taught by Rajagopalan et al., in the electronic device of Jo et al. Doing so would allow for the antenna feed to include an way to match the impedance of the patch and the signal trace, improving efficiency (Rajagopalan et al. Paragraph 76).
Regarding Claim 13, Jo et al. does not teach:
An impedance matching structure that includes the third conductive via, the fourth conductive via and the conductive trace.
Rajagopalan et al. does teach:
An impedance matching structure (paragraph 76) that includes the third conductive via (Fig 7, 124b), the fourth conductive via (Fig 7, 138) and the conductive trace (Fig 7, 134).
It would have been obvious to one having ordinary skill in the art before the invention was
effectively filed to include “An impedance matching structure that includes the third conductive via, the fourth conductive via and the conductive trace.” as taught by Rajagopalan et al., in the electronic device of Jo et al. Doing so would allow for matching the impedance of the patch and the signal trace, improving efficiency (Rajagopalan et al. Paragraph 76).
Regarding Claim 14, Jo et al. teaches:
Further comprising: an additional antenna having a third patch (Fig 8b, 520) in the first substrate (Fig 8b, 590) and a fourth patch (Fig 8b, 662) in the second substrate (Para 159 & Fig 10c, 610, 620, and 680; Examiners Note: Para 159 states 680 may share the dielectric constant of 610 and 620. When 610 and 620 are capped with 680, the collective unit may be seen as a singular “second substrate” and electrically acts equivalent), the fourth patch (Fig 8b, 662) overlapping the third patch (Fig 8b, 520), and the antenna and the additional antenna forming part of a phased antenna array (Fig 10c, AR2, and Para 81, Phase shifters).
Regarding Claim 15, Jo et al. teaches:
Further comprising: a third substrate (Fig 8b, 620) mounted to the first substrate (Fig 8b, 590); additional solder (Fig 8b, 5922 and 6212) that couples the first substrate (Fig 8b, 590) to the third substrate (Fig 8b, 620); and an additional antenna having a third patch (Fig 8b, 520) in the first substrate (Fig 8b, 590) and a fourth patch (Fig 8b, 662) in the third substrate (Fig 8b, 620), the fourth patch overlapping the third patch.
Regarding Claim 18, Jo et al. teaches:
wherein the second conductive via (Fig 8b, 512) passes through a hole (Fig 8b, 510a) in the first patch (Fig 8b, 510).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 20230062765) in view of Rajagopalan et al. (US 20200021019) and further in view of Han et al. (US 20210280959).
Regarding Claim 16, Jo et al. and Rajagopalan et al. does not disclose:
wherein the first substrate has a first portion with a first thickness, a second portion with the first thickness, and a third portion that couples the first portion to the second portion and that has a second thickness less than the first thickness, the second substrate being mounted to the first portion and the third substrate being mounted to the second portion.
Han et al. teaches: wherein the first substrate has a first portion with a first thickness (annotated Han Fig 2), a second portion with a second thickness (annotated Han Fig 2), and a third portion (annotated Han Fig 2, 206) that couples the first portion to the second portion (annotated Han Fig 2) and that has a third thickness less than the first and second thicknesses (annotated Han Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jo et al. in view of Rajagopalan et al. to incorporate the teachings of Han et al. to add a third portion with a third, less than, thickness to the first substrate, that couples the first portion with a first thickness and second portion with a second thickness, while maintaining the second substrate and third substrate mounting to the first substrate. Doing so would allow the first substrate to be shaped around the limited interior space of the electronic device; as well as providing a flexible portion that would permit the various antennas to be aligned in multiple and different directions providing better performance (Han et al. Para 32).
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US 20230062765) in view of Rajagopalan et al. (US 20200021019) and further in view of JAE YOUB et al. (KR 20100053761).
Regarding Claim 17, Jo et al. and Rajagopalan et al. does not disclose: an integrated circuit mounted to the second substrate and interposed between the first and second substrates.
JAE YOUB et al. teaches: an integrated circuit (annotated JAE YOUB Fig 6b, 40) mounted to the second substrate (annotated JAE YOUB Fig 6b, 31) and interposed between the first (annotated JAE YOUB Fig 6b, 11) and second substrates (annotated JAE YOUB Fig 6b, 31).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Jo et al. in view of Rajagopalan et al. to incorporate the teachings of JAE YOUB et al. to add an integrated circuit mounted to the second substrate and interposed between the first and second substrates. Doing so would allow for one to increase the density of wiring and electronic parts in a printed circuit board without the need of surface mounting components and without changing the exterior surface of the substrate (JAE YOUB, Paragraph 53).
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID ANDREW KUBERA whose telephone number is (571)272-5605. The examiner can normally be reached Monday-Friday 0430-1400 PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at (571) 272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAMEON E LEVI/Supervisory Patent Examiner, Art Unit 2845
/DAVID ANDREW KUBERA/Examiner, Art Unit 2845