DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on March 2, 2026 is acknowledged.
Response to Amendment
The amendment filed March 2, 2026 has been entered. Claims 1-10 and 26-28 remain pending in the application.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description: “706” (Fig. 7).
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
On Paragraph 47, line 3, replace “PMOS transistor M2” with “PMOS transistor M3”.
On Paragraph 62, line 12, replace “same” with “Same”.
Appropriate correction is required.
Claim Objections
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a copy of current at the first transistor” in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “a copy of a current at the first transistor” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 2-9 are likewise rejected under this logic by virtue of their dependency on claim 1.
Claim 3 recites the limitation “the OTA sets the drain-source voltage of the pass transistor” in lines 1-2. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the OTA to set the drain-source voltage of the pass transistor” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claims 7 and 8 recites the limitation “the controlled current” in line 2 of both claims. There is insufficient antecedent basis for this limitation in the claims. Amending the limitation to “a further controlled current” (for claim 7) and “the further controlled current” (for claim 8) is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 9-10 are likewise rejected under this logic by virtue of their dependency on claim 8.
Claim 7 recites the limitation “a copy of current at the further first transistor” in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “a copy of a current at the further first transistor” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 8-10 are likewise rejected under this logic by virtue of their dependency on claim 7.
Claim 8 recites the limitation “input current” in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “an input current” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 9-10 are likewise rejected under this logic by virtue of their dependency on claim 8.
Claim 27 recites the limitation “the current source” in lines 5 and 6. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the tuning current source” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 26 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kashmiri (Patent Publication Number US 2021/0156974 A1), as cited by applicant, hereafter referred to as Kashmiri.
Regarding claim 1, Kashmiri discloses:
An apparatus (Kashmiri, Fig. 15), comprising: a first transistor (Fig. 15, see P1 in modified Fig. 15 below) and a second transistor (Fig. 15, see P2 in modified Fig. 15 below) to provide a controlled current at the second transistor that is a copy of current at the first transistor (Paragraph 119, lines 1-6) when respective drain-source voltages of the first transistor and the second transistor are substantially equal (Paragraph 122, lines 1-7); and a feedback loop (Fig. 15, see P3 and A1 in modified Fig. 15 below) to set the respective drain-source voltages of the first transistor and the second transistor to be substantially equal (Paragraph 122, lines 1-7), wherein a responsiveness of the feedback loop is proportional to a set transconductance of an operational transconductance amplifier (OTA) of the feedback loop (Fig. 15, see A1 in modified Fig. 15 below and Paragraph 122, lines 1-7).
PNG
media_image1.png
804
650
media_image1.png
Greyscale
Regarding claim 2, Kashmiri further discloses:
wherein the feedback loop comprises: a pass transistor (Kashmiri, Fig. 15, see P3 in modified Fig. 15 above); and the OTA (Fig. 15, see A1 in modified Fig. 15 above), wherein the OTA to set a drain-source voltage of the pass transistor utilizing an output voltage generated by the OTA (Paragraph 122, lines 1-7).
Regarding claim 3, Kashmiri further discloses:
wherein the OTA sets the drain-source voltage of the pass transistor is at least partially responsive to a relationship between voltages at respective drains of the first transistor and the second transistor (Kashmiri, Paragraph 122, lines 1-7).
Regarding claim 4, Kashmiri further discloses:
wherein one of an inverting or non-inverting input of the OTA receives a drain voltage of the first transistor (Kashmiri, Fig. 15, see connection between A1 and drain of P1), and the other one of the inverting input or the non-inverting input of the OTA receives a drain voltage of the second transistor (Fig. 15, see connection between A1 and drain of P2).
Regarding claim 26, Kashmiri discloses:
A method (Kashmiri, Fig. 15), comprising: setting respective drain voltages of a first transistor (Fig. 15, see P1 in modified Fig. 15 above) and a second transistor (Fig. 15, see P2 in modified Fig. 15 above) to be substantially equal (Paragraph 122, lines 1-7) utilizing an operational transconductance amplifier (OTA) (Fig. 15, see A1 in modified Fig. 15 above) having a set bandwidth (Paragraph 122, lines 1-7); and providing a controlled current at the second transistor that is a copy of a current at the first transistor (Paragraph 119, lines 1-6) when respective drain-source voltages of the first transistor and the second transistor are substantially equal (Paragraph 122, lines 1-7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kashmiri as applied to claims 2 and 26, respectively, above, and further in view of Cui et al. (Patent Publication Number WO 2019/213973 A1), hereafter referred to as Cui.
Regarding claim 5, Kashmiri fails to disclose:
wherein the feedback loop comprises: a controlled current source coupled with a bias input of the OTA.
However, Cui teaches wherein the feedback loop comprises: a controlled current source (Cui, Fig. 10, R1 and Vbias) coupled with a bias input of the OTA (Fig. 10, see connection between R1 and gate of M1).
Kashmiri and Cui are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kashmiri to incorporate the teachings of Cui to include the bias circuit of Cui to bias the amplifiers of Kashmiri, which would have the effect of enabling varying the gain of the amplifiers of Kashmiri (Cui, Page 12, Paragraph 5, lines 1-2).
Regarding claim 6, Kashmiri fails to disclose:
wherein the controlled current source is a variable current source to generate a current proportional to a control signal.
However, Cui further teaches wherein the controlled current source is a variable current source to generate a current proportional to a control signal (Cui, Page 12, Paragraph 5, lines 1-2).
Kashmiri and Cui are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kashmiri to incorporate the teachings of Cui to include the bias circuit of Cui to bias the amplifiers of Kashmiri, which would have the effect of enabling varying the gain of the amplifiers of Kashmiri (Cui, Page 12, Paragraph 5, lines 1-2).
Regarding claim 27, Kashmiri fails to disclose:
comprising: sweeping, in a stepwise increasing or decreasing manner, the current generated by a tuning current source coupled to a bias input of the OTA; observing one or more of bandwidth or transconductance of the OTA while sweeping the current generated by the current source; and setting the current source to a current corresponding to one or more of an observed predetermined bandwidth or an observed predetermined transconductance.
However, Cui teaches comprising: sweeping, in a stepwise increasing or decreasing manner, the current generated by a tuning current source coupled to a bias input of the OTA (Cui, Page 12, Paragraph 5, lines 3-8); observing one or more of bandwidth or transconductance of the OTA while sweeping the current generated by the current source (Page 12, Paragraph 5, lines 3-8, see also Page 12, Paragraph 4, lines 1-6); and setting the current source to a current corresponding to one or more of an observed predetermined bandwidth or an observed predetermined transconductance (Page 12, Paragraph 4, lines 6-10).
Kashmiri and Cui are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kashmiri to incorporate the teachings of Cui to include the bias circuit of Cui to bias the amplifiers of Kashmiri, which would have the effect of enabling varying the gain of the amplifiers of Kashmiri (Cui, Page 12, Paragraph 5, lines 1-2).
Regarding claim 28, Kashmiri fails to disclose:
comprising: sweeping, in a stepwise increasing or decreasing manner, the current generated by a current source coupled to a bias input of the OTA; observing an output signal at least partially based on the controlled current at the second transistor while sweeping the current generated by the current source; and setting the current source to the current corresponding to the smallest observed output signal.
However, Cui teaches comprising: sweeping, in a stepwise increasing or decreasing manner, the current generated by a current source coupled to a bias input of the OTA (Cui, Page 12, Paragraph 5, lines 3-8); observing an output signal at least partially based on the controlled current at the second transistor while sweeping the current generated by the current source (Page 12, Paragraph 5, lines 3-8, see also Page 12, Paragraph 4, lines 6-10); and setting the current source to the current corresponding to the smallest observed output signal (Page 12, Paragraph 4, lines 6-10).
Kashmiri and Cui are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kashmiri to incorporate the teachings of Cui to include the bias circuit of Cui to bias the amplifiers of Kashmiri, which would have the effect of enabling varying the gain of the amplifiers of Kashmiri (Cui, Page 12, Paragraph 5, lines 1-2).
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kashmiri as applied to claim 1 above, and further in view of Nagata (Patent Publication Number JP 2012/221169 A), hereafter referred to as Nagata.
Regarding claim 7, Kashmiri further discloses:
comprising: a further first transistor (Kashmiri, Fig. 15, see N1 in modified Fig. 15 above) and a further second transistor (Fig. 15, see N2 in modified Fig. 15 above) to provide the controlled current at the further second transistor that is a copy of current at the further first transistor (Paragraph 119, lines 1-6) when the respective drain-source voltages of the further first transistor and the further second transistor are substantially equal (Paragraph 122, lines 1-7); a further feedback loop (Fig. 15, see N3 and A2 in modified Fig. 15 above) to set respective source voltages of the further first transistor and the further second transistor to be substantially equal (Paragraph 122, lines 1-7); but fails to disclose and a translinear loop to provide a DC bias current to the first transistor and the further first transistor.
However, Nagata teaches and a translinear loop (Nagata, Fig. 5, Q1-Q4) to provide a DC bias current to the first transistor and the further first transistor (Page 5, Paragraph 5, lines 6-8).
Kashmiri and Nagata are both considered to be analogous to the claimed invention because they are in the same field of improving amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Kashmiri to incorporate the teachings of Nagata to include the translinear loop of Nagata in the circuit of Kashmiri, which would have the effect of controlling the bias current of the transistors of Kashmiri (Nagata, Page 5, Paragraph 5, lines 12-17).
Regarding claim 8, Kashmiri further discloses:
wherein the further first transistor and the further second transistor to provide the controlled current at the further second transistor at least partially responsive to input current received at an input terminal of the apparatus exhibiting a first current direction (Kashmiri, Paragraph 122, lines 1-7), wherein the first transistor and the second transistor to provide the controlled current at the second transistor at least partially responsive to the input current received at the input terminal of the apparatus exhibiting a second current direction (Paragraph 122, lines 1-7), wherein the second current direction is different than the first current direction (Fig. 15, consider different activations of transistors P1 and N1 in modified Fig. 15 above).
Regarding claim 9, Kashmiri further discloses:
wherein: the first transistor and the second transistor are PMOS transistors (Kashmiri, Fig. 15, see that P1 and P2 are PMOS transistors in modified Fig. 15 above); and the further first transistor and the further second transistor are NMOS transistors (Fig. 15, see that N1 and N2 are NMOS transistors in modified Fig. 15 above).
Regarding claim 10, Kashmiri further discloses:
wherein respective sources of the first transistor and the second transistor to receive a first supply voltage (Kashmiri, Fig. 15, see supply voltage coupled to P1 and P2 via Rdeg/MPb), and wherein the respective sources of the further first transistor and the further second transistor to receive a second supply voltage (Fig. 15, see ground voltage coupled to N1 and N2 via Rdeg/MNb), wherein the first supply voltage and the second supply voltage are different (Fig. 15, see that supply voltage and ground voltage are different).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bell et al. (Patent Publication Number CN 105,339,857 A) discloses (Fig. 1A) a bidirectional current mirror transistor amplifier.
Basilico et al. (Patent Publication Number US 2020/0186098 A1) discloses (Fig. 6) an inverting amplifier.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843