Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. Claims 1-20 are presented for examination.
Claim Objections
2. Claim 16 is objected to because of the following informalities:
As per Claim 16, it recites the limitation “applying,” in line 4 which would be better as “to apply,”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claim 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per Claim 1, 8, and 15, they recite the limitation “sensitive component” which is a relative term which renders the claim indefinite. The term “sensitive” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
As per Claims 5, 12, and 19, they recite the limitation “the model of the electronics device” which lacks proper antecedent basis, because claims 1, 8, and 15 recite identifying the sensitive component “in an electronics device,” not in a model of the electronics device, and the product model is generated only after the identifying step. For examination purposes, the Office is interpreting “the model of the electronics device” as the electronics device recited in the identifying step of claims 1, 8, and 15, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
4. Claims 1, 7, 8, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2010/0241373 A1) in view of Muchaidze (US 10,325,057 B2).
As per Claim 1, 8, and 15, Watanabe teaches A computer-implemented method/system/program for building a product model that indicates an electrostatic discharge (ESD) sensitivity level (Fig. 1-4, [0043]: a program-controlled ESD protection verification apparatus operates on the design layout data of a semiconductor integrated circuit, an electronics device), comprising:
identifying a sensitive component in an electronics device and mapping the sensitive component to a location in the electronics device ([0044] “a first element extraction unit 11 for extracting layout data for an element connected to the selected pad among a plurality of elements included in the design layout data”; [0057] “the error detection unit 13 considers that ESD breakdown may be caused in this diode, and detects this element as a design error”: elements that may suffer ESD breakdown corresponding to the “sensitive component” as claimed, are identified and their layout data, i.e., their ”location” in the device design, is extracted);
obtaining ESD metadata for the sensitive component from an ESD database ([0041] “a database (hereinafter referred to as an ESD withstand voltage database) regarding ESD withstand voltages is stored in the storage device 3”: per-element ESD withstand-voltage data, corresponding to the “ESD metadata” as claimed, is obtained from the stored ESD database); and
determining an ESD voltage threshold for the sensitive component based on the ESD metadata for the sensitive component ([0041] “That is, if the area or circumference of an element is found, the ESD withstand voltage of the element can be found”; [0056] “If the error detection unit 13 determines that the calculated operating value is greater than or equal to the reference value, the diode is regarded as satisfying the required ESD withstand voltage and determined as a diode free of ESD breakdown”: the element’s ESD withstand voltage corresponding to the “ESD voltage threshold” as claimed, is determined for the element from the database information). In particular, Watanabe teaches a computer-implemented verification apparatus that extracts the elements connected to each selected pad from the design layout data of a semiconductor integrated circuit, obtains ESD withstand-voltage information for those elements from an ESD withstand voltage database, determines element by element whether the required ESD withstand voltage is satisfied, and saves positional information in the layout data for each element detected as an error.
However, Watanabe fails to teach explicitly generating a product model of the electronics device, wherein the product model includes a plurality of sensitive components mapped to a plurality of locations in the electronics device and an indication of the ESD voltage threshold for each sensitive component at a respective mapped location in the electronic device.
Muchaidze teaches generating a product model of the electronics device, wherein the product model includes a plurality of sensitive components mapped to a plurality of locations in the electronics device and an indication of the ESD voltage threshold for each sensitive component at a respective mapped location in the electronic device (col. 7, lines 27-67 “In operation, the visualization module 142 combines the measurement data made at the various sampling locations about the DUT and the computer-aided design layout of the DUT”, “The measurement data is then added to the CAD DUT layout at the right locations in the CAD DUT layout space that correspond to the actual sampling locations in real space”, “FIG. 5C is another perspective view of the CAD PCB layout with measurements in which the measurements have contours, which may indicate radio frequency (RF) emission levels, electrostatic discharge (ESD) susceptibility levels, ESD current density, antenna parameters etc., depending on the scanning technology used.”; col. 8, lines 63-66 “the processing system 110 will “know” the position of the DUT on the scanning plate as well as the position of various components of the DUT on the scanning plate”: a model of the device is generated in which per-location electrostatic discharge (ESD) susceptibility values are indicated on the computer-aided design layout at locations corresponding to the device’s components, i. e. the “product model” with an “indication of the ESD voltage threshold” at each “respective mapped location” as claimed, the indicated per-element values in the combination being Watanabe’s withstand-voltage determinations). In particular, Muchaidze teaches combining measurement data with a computer-aided design layout of a device under test and displaying the combined layout, in which the displayed contours may indicate electrostatic discharge (ESD) susceptibility levels and the position of every component of the device on the layout is known to the processing system.
Watanabe and Muchaidze are analogous art because they are both from the same field of endeavor, computer-aided electrostatic discharge analysis of electronic devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to incorporate Muchaidze into Watanabe’s invention for the purpose of verifying ESD protection in a semiconductor integrated-circuit design to provide information regarding a particular component of the DUT that can be readily available for the user since the computer-aided design layout of the DUT can contain information regarding all the components of the DUT, regardless of whether or not the component is visible from the outside of the DUT so that the DUT can be analyzed efficiently and effectively (Muchaidze: col. 3, lines 21-24, col. 7, lines 17-23).
As per Claim 7 and 14, Watanabe teaches wherein the ESD database comprises data selected from a group consisting of: historical ESD test data for the sensitive component, historical ESD test data for the electronics device, and a regulatory specification related to ESD. ([0042] “information on the ESD withstand voltage of the element may be included in the element information data”; [0041] “The ESD withstand voltage of the element is correlated with the dimension and operating characteristics of the element”: the ESD withstand voltage database holds per-element ESD withstand-voltage characterization data, corresponding to the “historical ESD test data for the sensitive component” as claimed, an element’s withstand voltage being established by ESD characterization of that element).
5. Claims 2, 3, 9, 10, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2010/0241373 A1) in view of Muchaidze (US 10,325,057 B2), further in view of Min (US 8,823,383 B2).
Watanabe as modified by Muchaidze teaches most all the instant invention as applied to claims 1, 7, 8, 14, and 15 above.
As per Claim 2, 9, and 16, Watanabe as modified by Muchaidze fails to teach explicitly transmitting the product model to an ESD test simulation system; and applying, by the ESD test simulation system, ESD discharges to each respective mapped location in the electronics device.
Min teaches transmitting the product model to an ESD test simulation system (col. 5, lines 23-33 “The ESD testing system allows the user to save the project to file and use it in the future without redefinition of test points, scenarios, gun settings and test flow”: the saved project carrying the device’s mapped test points and gun settings, i.e., the “product model” of the combination, is supplied to and reused by the automated ESD test system, an “ESD test simulation system” as claimed); and
applying, by the ESD test simulation system, ESD discharges to each respective mapped location in the electronics device. (col. 5, lines 23-33 “the ESD testing system moves the ESD gun to test point positions, makes zaps, brushes, presses keys, and detects different types of failures”: ESD discharges are applied by the test system at each mapped test-point location on the device).
Watanabe, Muchaidze, and Min are analogous art because they are all from the same field of endeavor, electrostatic discharge evaluation of electronic devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to incorporate Min into Watanabe as modified by Muchaidze’s invention for the purpose of verifying ESD protection in a semiconductor integrated-circuit design to provide information regarding a particular component of the DUT that can be readily available for the user since the computer-aided design layout of the DUT can contain information regarding all the components of the DUT, regardless of whether or not the component is visible from the outside of the DUT so that the DUT can be analyzed efficiently and effectively (Muchaidze: col. 3, lines 21-24, col. 7, lines 17-23) and to provide a universal system for identifying problematic areas in any type of DUTs (Min: col. 3, lines 63-67).
As per Claim 3, 10, and 17, Watanabe as modified by Muchaidze fails to teach explicitly monitoring user interactions with the product model, wherein a user selects the location in the electronics device on the product model; and mapping the sensitive component to the location in the electronics device based on the user interactions.
Min teaches monitoring user interactions with the product model, wherein a user selects the location in the electronics device on the product model (col. 5, lines 1-11 “a user defines test points on the DUT surface using the 3D positions definition module 306 of the ESD testing software and the cameras 114 of the system”: the testing software monitors the user’s selections of locations on the device); and
mapping the sensitive component to the location in the electronics device based on the user interactions. (col. 8, lines 56-61 “each view shows an image from a corresponding camera. The user can reconstruct 3D space position by clicking on these views”: the user’s clicked selection is mapped into a position on the device in 3D space).
6. Claims 4-6, 11- 13, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (US 2010/0241373 A1) in view of Muchaidze (US 10,325,057 B2), further in view of Yamane (US 2022/0138381 A1).
Watanabe as modified by Muchaidze teaches most all the instant invention as applied to claims 1, 7, 8, 14, and 15 above.
As per Claim 4, 11, and 18, Watanabe as modified by Muchaidze fails to teach explicitly identifying an ESD regulatory specification in the ESD metadata, wherein the ESD regulatory specification includes a geographical region; and modifying the ESD voltage threshold based on the geographical region of the ESD regulatory specification.
Yamane teaches identifying an ESD regulatory specification in the ESD metadata, wherein the ESD regulatory specification includes a geographical region ([0051] “The model estimates, on the basis of the circuit data of an electronic circuit, the intensity of electromagnetic waves at a position apart from the electronic circuit by a predetermined distance (for example, 10 meters). For example, the distance is determined according to regulations of electromagnetic radiation set in individual country”: Yamane’s regulation of electromagnetic radiation set in individual country corresponds to the claimed “ESD regulatory specification” that “includes a geographical region,” electrostatic discharge immunity being a species of electromagnetic-disturbance compliance); and
modifying the ESD voltage threshold based on the geographical region of the ESD regulatory specification. ([0003] “there may be a regulation that the intensity of radiated electromagnetic waves needs to be less than a threshold. Therefore, the electronic circuits are designed so as to meet the regulation of electromagnetic waves.”; [0051] “The model estimates, on the basis of the circuit data of an electronic circuit, the intensity of electromagnetic waves at a position apart from the electronic circuit by a predetermined distance (for example, 10 meters). For example, the distance is determined according to regulations of electromagnetic radiation set in individual country.”; [0103]: the evaluation criterion applied to the design is set according to the regulation of the individual country, so that the compliance threshold applied to the device is modified per the geographical region’s regulation).
Watanabe, Muchaidze, and Yamane are analogous art because they are all from the same field of endeavor, computer-aided electromagnetic-compliance analysis of electronic designs.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of cited references. Thus, one of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to incorporate Yamane into Watanabe as modified by Muchaidze’s invention for the purpose of verifying ESD protection in a semiconductor integrated-circuit design to provide information regarding a particular component of the DUT that can be readily available for the user since the computer-aided design layout of the DUT can contain information regarding all the components of the DUT, regardless of whether or not the component is visible from the outside of the DUT (Muchaidze: col. 7, lines 17-23) and to provide estimation of the intensity of electromagnetic waves on the basis of circuit data by using a model created with machine learning, rather than a physical simulation that has problems that are high computational load and long execution time (Yamane: [0004]).
As per Claim 5, 11, and 19, Watanabe as modified by Muchaidze fails to teach explicitly wherein the identifying the sensitive component in the model of the electronics device uses a machine learning model that predicts ESD test points for the electronics device based on an ESD regulatory specification and technical specifications of the electronics device..
Yamane teaches wherein the identifying the sensitive component in the model of the electronics device uses a machine learning model that predicts ESD test points for the electronics device based on an ESD regulatory specification and technical specifications of the electronics device. ([0029] “The control unit 12 performs machine learning for a model using the training data 15”, “The model may be a neural network. The machine learning may be deep learning”; [0051]: the positions at which Yamane’s model estimates the regulated electromagnetic intensity correspond to the “ESD test points” as claimed, and the country-set regulation corresponds to the “ESD regulatory specification”).
As per Claim 6, 12, and 19, Watanabe as modified by Muchaidze fails to teach explicitly wherein the determining the ESD voltage threshold for the sensitive component based on the ESD metadata for the sensitive component uses a machine learning model that predicts an ESD testing level for the sensitive component based on an ESD regulatory specification and historical ESD testing information for the electronics device.
Yamane teaches wherein the determining the ESD voltage threshold for the sensitive component based on the ESD metadata for the sensitive component uses a machine learning model that predicts an ESD testing level for the sensitive component based on an ESD regulatory specification and historical ESD testing information for the electronics device. ([0029] “The correct intensity of electromagnetic waves may be measured using an electronic circuit implemented based on the circuit data 13”; [0051]: the model is trained on intensities measured from implemented circuits, corresponding to the “historical ESD testing information” as claimed, and predicts the regulated level to be met under the country-set regulation, corresponding to the “ESD testing level” as claimed).
Conclusion
7. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Strickland (US 7,237,209 B2) teaches evaluation of the electrostatic discharge tolerance of routes between nodes of an integrated circuit design against an ESD protection specification.
Esmark (US 7,694,247 B2) teaches identification of ESD and latch-up weak points in an integrated circuit design using a database of ESD-characterized circuit elements.
Boselli (US 8,589,839 B2) teaches validating ESD protection for an integrated circuit by comparing component information of the circuit with predefined ESD protection elements and requirements.
Simonov (US 5,818,235 A) teaches supplying electrostatic discharges to a device under test at preselected position points stored in a controller memory.
Bortolini (US 5,912,559 A) teaches detection and localization of electrostatic discharge susceptible areas of electronic systems.
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUNHEE KIM whose telephone number is (571)272-2164. The examiner can normally be reached Monday-Friday 9am-5pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached at (571)272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EUNHEE KIM
Primary Examiner
Art Unit 2188
/EUNHEE KIM/Primary Examiner, Art Unit 2188
Prosecution Insights