DETAILED ACTION
This office action is responsive to communication filed on January 21, 2026.
Response to Arguments
Applicant's arguments filed January 21, 2026 have been fully considered but they are not persuasive.
Applicant argues, with respect to claim 1, that Basavalingappa does not disclose or suggest positioning the transfer MOS transistors or the overflow or charge drainage MOS transistors such that they extend into the planar footprint of the photoelectric conversion device itself, as required by the amended claims.
The Examiner respectfully disagrees. Basavalingappa et al. clearly shows in figure 8 that the transfer MOS transistors (TG0, TG1, TG2, TG3) and the charge drainage MOS transistors (OFG) extend into the planar footprint of the photoelectric conversion device (PD). Figures 3-5 also show such an overlapping configuration between the transfer/drainage transistors and the photoelectric conversion device (PD).
Applicant additionally argues, with respect to claim 1, that Basavalingappa also fails to disclose or suggest the claimed side-specific arrangement and symmetry of the transfer MOS transistors and charge drainage MOS transistors relative to the rectangular photoelectric conversion device, further demonstrating that the cited references do not teach the claimed pixel circuit architecture.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The primary reference, Jin et al. teaches the claimed side-specific arrangement and symmetry of the transfer MOS transistors and charge drainage MOS transistors relative to the rectangular photoelectric conversion device (see claim 1 rationale). As such, whether or not Basavalingappa et al. teaches these features is inconsequential, as Basavalingappa et al. is not relied upon to teach these features.
Applicant additionally argues, with respect to claim 1, that Jin (even in combination with Basavalingappa) does not teach or suggest transfer MOS transistors that include an n-type diffusion layer of the photoelectric conversion device as a source.
The Examiner respectfully disagrees. Jim et al. teaches that the transfer MOS transistors (TGA, TGB, TGC, TGD) include an n-type diffusion layer of the photoelectric conversion device as a source (As detailed in paragraph 0055, the photoelectric conversion device comprises a photodiode PD doped with N-type impurities (i.e. an n-type diffusion layer). As shown in figure 13, this photodiode (PD) is at the source of the transfer MOS transistors (TGA, TGB, TGC, TGD), and is thus included as a source of the transfer MOS transistors (TGA, TGB, TGC, TGD).).
Therefore, the rejection is maintained by the Examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 3, 9, 10 and 17 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 3 is amended to recite “the M transfer MOS transistors each extend at least halfway into the planar footprint of the photoelectric conversion device when viewed in a plan view”. Applicant refers to pages 2 and 36 of the specification, as well as FIGS. 4 and 5 of the drawings for providing support for the amended claim limitations. Figures 4 and 5 show that the M transfer MOS transistors (G1, G2, G3, G4) partially extend into the planar footprint of the photoelectric conversion device (PD). However, figures 4 and 5 do not show the M transfer MOS transistors (G1, G2, G3, G4) extending at least halfway into the planar footprint of the photoelectric conversion device (PD). In order for the M transfer MOS transistors (G1, G2, G3, G4) to extend at least halfway, they would have to extend at least to the X-axis. The Examiner has found no support for this in the portions cited by Applicant or elsewhere in the original disclosure. As such, claim 3 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 9, 10 and 17 depend from or otherwise require all of the limitations of claim 3, and thus contain the same new matter as claim 3.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4-8, 11-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jin et al. (US 2022/0021831) in view of Basavalingappa et al. (US 2022/0238577).
Consider claim 1, Jin et al. teaches:
A range imaging device (see figures 13 and 14), comprising:
a semiconductor substrate (“a semiconductor substrate”, paragraph 0114); and
a pixel circuit formed at a surface of the semiconductor substrate (see figures 13 and 14, paragraph 0114) and comprising a photoelectric conversion device (common photo gate, CPG, paragraph 0115) configured to generate charge carriers based on light incident from a space targeted for measurement (“a photo charge collected by the common photogate CPG” paragraph 0047), a plurality of charge storages (storage gates, SG1, SG2, figure 14) each configured to store at least part of the charge carriers (“The storage gates SG1 and SG2 are one of charge storing structures to temporarily store the photo charge transferred from the common photogate CPG before transferring the photo charge to the floating diffusion regions FDA, FDB, FDC and FDD.” paragraph 0117), a plurality of transfer MOS transistors (transfer gates TGA, TGB, TGC, TGD) positioned on a transfer path (see figures 13 and 14) and configured to transfer at least part of the charge carriers from the photoelectric conversion device (CPG) to a corresponding one of the charge storages (SG1, SG2) through the transfer path (see figures 13 and 14, paragraphs 0115 and 0117), wherein the transfer MOS transistors (TGA, TGB, TGC, TGD) include an n-type diffusion layer of the photoelectric conversion device as a source (As detailed in paragraph 0055, the photoelectric conversion device comprises a photodiode PD doped with N-type impurities (i.e. an n-type diffusion layer). As shown in figure 13, this photodiode (PD) is at the source of the transfer MOS transistors (TGA, TGB, TGC, TGD), and is thus included as a source of the transfer MOS transistors (TGA, TGB, TGC, TGD).), and a plurality of charge drainage MOS transistors (overflow gates, OG1, OG2) positioned on a drainage path (see figures 13 and 14) and configured to drain the charge carriers from the photoelectric conversion device (CPG) through the drainage path (“the plurality of overflow gates OG1 and OG2 may drain the photo charge collected by the common photogate CPG”, paragraph 0047),
wherein the photoelectric conversion device (CPG) has a rectangular shape on the surface of the photoelectric conversion device (see figure 14), the plurality of transfer MOS transistors (TGA, TGB, TGC, TGD) comprises 2M transfer MOS transistors (i.e. four transistors), and the plurality of charge drainage MOS transistors (OG1, OG2) comprises 2N charge drainage MOS transistors (i.e. two transistors), where M is an integer greater than or equal to 2 (i.e. is 2), and N is an integer greater than or equal to 1 (i.e. is 1), M transfer MOS transistors of the 2M transfer MOS transistors (TGA, TGB, TGC, TGD) are positioned on each of long sides of the photoelectric conversion device (CPG) symmetrically with respect to an x-axis (HLY) that is parallel to the long sides and passes through a center of the photoelectric conversion device (CPG, see figure 14), the M transfer MOS transistors on one of the long sides face the M transfer MOS transistors on the other of the long sides (see figure 14), the 2N charge drainage MOS transistors (OG1, OG2) are positioned on respective short sides of the photoelectric conversion device (CPG, see figure 14), and the pixel circuit includes a plurality of selection transistors (see SEL1 and SEL2, figures 13 and 14, paragraph 0115) formed such that the selection transistors are positioned symmetrically with respect to the x-axis (HLY, see figure 14).
Jin et al. does not explicitly teach that the M transfer MOS transistors each extend into a planar footprint of the photoelectric conversion device when viewed in a plan view, wherein the charge drainage MOS transistors each extend into the planar footprint of the photoelectric conversion device when viewed in the plan view.
Basavalingappa et al. similarly teaches:
A range imaging device (see figures 1 and 8), comprising:
a semiconductor substrate (“semiconductor substrate”, paragraph 0043); and
a pixel circuit formed at a surface of the semiconductor substrate (A pixel array unit (20) is formed on the semiconductor substrate, paragraph 0043. The pixel array unit includes pixels (51) as shown in figure 8, paragraph 0045.) and comprising (see figure 8) a photoelectric conversion device (photoelectric conversion region, PD, paragraph 0079) configured to generate charge carriers based on light incident from a space targeted for measurement (see paragraphs 0045 and 0046), a plurality of charge storages (floating diffusions, FD0, FD1, FD2, FD3) each configured to store at least part of the charge carriers (see paragraph 0079), a plurality of transfer MOS transistors (transfer transistors, TG0, TG1, TG2, TG3) positioned on a transfer path (see figure 8) and configured to transfer at least part of the charge carriers from the photoelectric conversion device (PD) to a corresponding one of the charge storages (FD0, FD1, FD2, FD3) through the transfer path (see figure 8, paragraphs 0079 and 0080), and a plurality of charge drainage MOS transistors (fifth and sixth transistor, OFG, paragraph 0109) positioned on a drainage path (see figure 8) and configured to drain the charge carriers from the photoelectric conversion device (PD) through the drainage path (see paragraph 0109),
wherein the photoelectric conversion device (PD) has a rectangular shape on the surface of the photoelectric conversion device (see figure 8), the plurality of transfer MOS transistors comprises (TG0, TG1, TG2, TG3) 2M transfer MOS transistors (i.e. 4 transistors), and the plurality of charge drainage MOS transistors (TG) comprises 2N charge drainage MOS transistors (i.e. 2 transistors), where M is an integer greater than or equal to 2 (i.e. 2), and N is an integer greater than or equal to 1 (i.e. 1, see figure 8), M transfer MOS transistors of the 2M transfer MOS transistors are positioned on each of long sides of the photoelectric conversion device (PD) symmetrically with respect to an x-axis (A2) that is parallel to the long sides and passes through a center of the photoelectric conversion device (PD, see figure 8), the M transfer MOS transistors on one of the long sides (e.g. TG0 and TG1) face the M transfer MOS transistors on the other of the long sides (e.g. TG2 and TG3, see figure 8), and the 2N charge drainage MOS transistors (OFG) are positioned on respective short sides of the photoelectric conversion device (PD, see figure 8).
However, Basavalingappa et al. additionally teaches that the M transfer MOS transistors (TG0, TG1, TG2, TG3) each extend into a planar footprint of the photoelectric conversion device (PD) when viewed in a plan view (See figures 8 and 3-5.), wherein the charge drainage MOS transistors (OFG) each extend into the planar footprint of the photoelectric conversion device (PD) when viewed in the plan view (See figures 8 and 3-5.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the photoelectric conversion device taught by Jin et al. be a photoelectric conversion device that is at least partially overlapped by the M transfer MOS transistors and the charge drainage MOS transistors in a plan view as taught by Basavalingappa et al. for the benefit of enabling fast charge transfer from the photodiodes to the pixel circuits and fast overflow (Basavalingappa et al., paragraph 0003).
Consider claim 2, and as applied to claim 1 above, Jin et al. further teaches that the transfer MOS transistors (TGA, TGB, TGC, TGD) are positioned symmetrically with respect to a y-axis (HLX) that is parallel to the short sides and passes through the center of the photoelectric conversion device (CPG, see figure 14), or
wherein the charge storages (SG1, SG2) are positioned symmetrically with respect to the x-axis (HLY, see figure 14).
Consider claim 6, and as applied to claim 2 above, Jin et al. further teaches that the charge storages (SG1, SG2) are positioned symmetrically with respect to the x-axis (HLY, see figure 14).
Consider claim 7, and as applied to claim 2 above, Jin et al. further teaches a microlens (MLN) facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light (see figure 30A, paragraph 0156), the microlens (MLN) has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device (CPG, PD) and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (see figure 30A, paragraphs 0156 and 0158).
Consider claim 8, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 2 (sensing unit, paragraph 0084, see claim 2 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Consider claim 15, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 7 (sensing unit, paragraph 0084, see claim 7 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Consider claim 12, and as applied to claim 6 above, Jin et al. further teaches a microlens (MLN) facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light (see figure 30A, paragraph 0156), the microlens (MLN) has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device (CPG, PD) and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (see figure 30A, paragraphs 0156 and 0158).
Consider claim 14, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 12 (sensing unit, paragraph 0084, see claim 12 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Consider claim 13, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 6 (sensing unit, paragraph 0084, see claim 6 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Consider claim 4, and as applied to claim 1 above, Jin et al. further teaches a microlens (MLN) facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light (see figure 30A, paragraph 0156), the microlens (MLN) has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device (CPG, PD) and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (see figure 30A, paragraphs 0156 and 0158).
Consider claim 11, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 4 (sensing unit, paragraph 0084, see claim 4 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Consider claim 16, and as applied to claim 1 above, Jin et al. further teaches that the pixel circuit includes a plurality of source follower transistors (TSF1, TSF2) formed such that the source follower transistors (TSF1, TSF2) are positioned symmetrically with respect to the x-axis (see figure 14, paragraph 0113).
Consider claim 20, and as applied to claim 16 above, Jin et al. further teaches that the pixel circuit includes a plurality of reset transistors (reset gates, RG1, RG2, paragraph 0114) formed such that the reset transistors (RG1, RG2) are positioned symmetrically with respect to the x-axis (HLY, see figure 14) and linearly aligned with the selection transistors (SEL1, SEL2) and the source follower transistors (TSF1, TSF2), respectively (See figure 14. A straight line may be drawn through RG1, SEL1 and TSF1, for instance.).
Consider claim 18, and as applied to claim 1 above, Jin et al. further teaches that the pixel circuit includes a plurality of reset transistors (reset gates, RG1, RG2, paragraph 0114) formed such that the reset transistors (RG1, RG2) are positioned symmetrically with respect to the x-axis (HLY, see figure 14).
Consider claim 19, and as applied to claim 1 above, Jin et al. further teaches that the pixel circuit includes a plurality of reset transistors (reset gates, RG1, RG2, paragraph 0114) formed such that the reset transistors (RG1, RG2) are positioned symmetrically with respect to the x-axis (HLY, see figure 14) and linearly aligned with the selection transistors (SEL1, SEL2), respectively (See figure 14. A straight line may be drawn through RG1 and SEL1, for instance.).
Consider claim 5, Jin et al. teaches:
A range imaging apparatus (ToF sensor, 100, figure 10, paragraphs 0083 and 0084), comprising:
a light receiving unit including the range imaging device of claim 1 (sensing unit, paragraph 0084, see claim 1 rationale); and
a distance image processing unit (controller, 150) comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (“The controller 150 may calculate a distance of the object OBJ from the ToF sensor 100, a horizontal position of the object OBJ, a vertical position of the object OBJ and/or a size of the object OBJ based on the sample data SDATA.” paragraphs 0094 and 0095).
Prior Art
Consider claim 3, the prior art of record does not teach nor reasonably suggest that the M transfer MOS transistors each extend at least halfway into a planar footprint of the photoelectric conversion device when viewed in a plan view, in combination with the other elements recited in parent claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637
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