Prosecution Insights
Last updated: August 18, 2026
Application No. 18/306,631

RANGE IMAGING DEVICE AND RANGE IMAGING APPARATUS

Non-Final OA §103
Filed
Apr 25, 2023
Priority
Oct 28, 2020 — JP 2020-180564 +1 more
Examiner
CHILTON, CLARA GRACE
Art Unit
3645
Tech Center
3600 — Transportation & Electronic Commerce
Assignee
Toppan Holdings Inc.
OA Round
2 (Non-Final)
54%
Grant Probability
Moderate
2-3
OA Rounds
9m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 54% of resolved cases
54%
Career Allowance Rate
39 granted / 72 resolved
+2.2% vs TC avg
Moderate +12% lift
Without
With
+12.2%
Interview Lift
resolved cases with interview
Typical timeline
4y 1m
Avg Prosecution
35 currently pending
Career history
101
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
60.7%
+20.7% vs TC avg
§102
22.5%
-17.5% vs TC avg
§112
14.7%
-25.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 72 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, filed 6/18/2026, with respect to the rejections of independent claims, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kondo (US 20210194444 A1). Thus, this action is made non-final. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, 6, 7, 9, 11, 13, 16, and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe (WO 2020202779 A1) in view of Kondo (US 20210194444 A1). Claim 1: Watanabe teaches a range imaging device, comprising: a semiconductor substrate (Fig. 24, substrate 31); and a pixel circuit formed at a surface of the semiconductor substrate (pg 4, pg 5-6 of attached PDF and Fig. 2) and including a photoelectric conversion device configured to generate charge carriers based on light incident thereon from a space targeted for measurement (highlight spanning pg 4-5), a plurality of pixel signal reading circuits, each pixel reading circuit connected with the photoelectric conversion device through a corresponding one of transfer paths (pg 4 – multiple pixels in pixel array) and each including a charge storage each configured to store at least part of the charge carriers (pg 19, storing and discharging taps), a transfer MOS transistor each positioned on the corresponding one of the transfer paths and configured to transfer at least part of the charge carriers from the photoelectric conversion device to the charge storage through the transfer path (pg 5, transfer control mechanisms are MOS transistors), and a reset transistor (Fig. 11, reset transistors RT1-RT4), a source follower transistor (Fig. 11, source follow transistors SF1-SF4), and a selection transistor (Fig. 11, selection transistors SL1-SL4) each operatively connected with the transfer MOS transistor to output a signal indicating an amount of the charge carriers distributed to the pixel signal reading circuit (pg 7-8), and at least one charge drainage MOS transistor positioned on a drainage path and configured to drain the charge carriers from the photoelectric conversion device through the drainage path (pg 18, charge discharge mechanism GD), wherein the photoelectric conversion device formed at the surface of the semiconductor substrate has an N-sided polygonal shape in plain view(Fig. 31, polygon), a total number of the transfer MOS transistors and the at least one charge drainage MOS transistor is N or more (Fig. 31, GD1, GD2, G1-G3). where N is an integer greater than or equal to 5 (Fig. 31, polygon), and the N-sided polygonal shape of the photoelectric conversion device has N sides including at least one first side at which the at least one charge drainage MOS transistor is positioned (Fig. 30, transistors GD1, GD2), and second sides other than the at least one first side such that each of the second sides is a side at which a corresponding one of the transfer MOS transistors is positioned (Fig. 31, GD1, GD2, G1-G3), the reset transistors of the plurality of pixel signal reading circuits are positioned symmetrically with respect to an axis that passes through a center of the N-sided polygonal shape and is perpendicular to one of the sides of the N-sided polygonal shape (Fig. 31, transfer MOS G1-G3 inside shaded region positioned perpendicularly to polygon), the source follower transistors of the plurality of pixel signal reading circuits are positioned symmetrically with respect to the axis, and the selection transistors of the plurality of pixel signal reading circuits are positioned symmetrically with respect to the axis (Fig. 11, showing discharge mechanisms GD(n), taken along with Fig. 31). Watanabe does not teach, but Kondo does teach, a total number of the transfer MOS transistors and the at least one charge drainage MOS transistor is N or more, and the N-sided polygonal shape of the photoelectric conversion device has N sides including at least one first side at which the at least one charge drainage MOS transistor is positioned (Fig. 15, transistor rows 12 positioned around polygon). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the configuration, as taught by Kondo, in the device as taught by Watanabe (instead of Watanabe’s configuration shown in Fig. 31) because this is simply a rearrangement of parts which would yield predictable results (as circuitry and arrangement of circuit components is well known in the art). Claim 2: Watanabe, as modified, teaches the range imaging device according to claim 1, wherein each of the transfer MOS transistors is positioned perpendicular to a corresponding one of the sides of the N-sided polygonal shape, and the transfer MOS transistors are positioned symmetrically with respect to the axis (Fig. 31, transfer MOS G1-G3 inside shaded region positioned perpendicularly to polygon). Claim 3: Watanabe, as modified, teaches the range imaging device according to claim 1, wherein the one of the sides of the N-sided polygonal shape is the at least one first side on which the at least one charge drainage MOS transistor is positioned (Fig. 31, GD1, GD2 positioned on two sides of polygon). Claim 4: Watanabe, as modified, teaches the range imaging device according to claim 1, wherein the charge storages of the plurality of signal reading circuits are positioned symmetrically with respect to the axis (Fig. 31, GD1 and GD2 inside shaded area positioned symmetrically with respect to z (up-down) axis). Claim 6: Watanabe, as modified, teaches a range imaging apparatus, comprising: a light receiving unit including the range imaging device of claim 1; and a distance image processing unit comprising circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (pg 4, TOF device). Claim 7: Watanabe, as modified, teaches the range imaging device according to claim 3, wherein the charge storages of the plurality of pixel reading circuits are positioned symmetrically with respect to the axis (Fig. 31, GD1 and GD2 inside shaded area positioned symmetrically with respect to z (up-down) axis). Claim 9: Watanabe, as modified, teaches a range imaging apparatus, comprising: a light receiving circuit including the range imaging device of claim 2; and distance image processing circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (pg 4, TOF device). Claim 11: Watanabe, as modified, teaches a range imaging apparatus, comprising: a light receiving circuit including the range imaging device of claim 3; and distance image processing circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (pg 4, TOF device). Claim 13: Watanabe, as modified, teaches a range imaging apparatus, comprising: a light receiving circuit including the range imaging device of claim 4; and distance image processing circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (pg 4, TOF device). Claim 16: Watanabe, as modified, teaches a range imaging apparatus, comprising: light receiving circuit including the range imaging device of claim 7; and a distance image processing circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (pg 4, TOF device). Claim 18: Watanabe, as modified, teaches the range imaging device according to Claim 1. Watanabe, as modified, does not teach wherein the N-sided polygonal shape is a hexagon, the transfer MOS transistors of the plurality of pixel signal reading circuits comprise two pairs of transfer MOS transistors symmetrically positioned with respect to the axis, and the at least one charge drainage MOS transistor comprises two charge drainage MOS transistors respectively located on a pair of opposed sides of the hexagon perpendicular to the axis. However, Kondo does teach that the polygonal shape can be any polygonal shape ([0118], [0146]). This, along with Fig. 15 of Kondo, showing the orientation of transistors 12, and previously discussed rejection of Claim 1, specifically regarding Watanabe and the configuration of individual transistors, would render the claim obvious. Different configurations of transistors (i.e.: in different polygonal shapes) would be obvious as this would simply be a rearrangement of parts. The function of the device, and the transistors, would be predictable no matter what configuration they are in, as transistors are well known in the art. Claim 19: Watanabe, as modified, teaches the range imaging device according to claim 18 the reset transistors of the plurality of pixel signal reading circuits comprise two pairs of reset transistors symmetrically positioned with respect to the axis, the source follower transistors of the plurality of pixel signal reading circuits comprise two pairs of source follower transistors symmetrically positioned with respect to the axis, and the selection transistors of the plurality of pixel signal reading circuits comprise two pairs of selection transistors symmetrically positioned with respect to the axis (Watanabe, Fig. 31, discharge mechanisms GD(n) positioned symmetrically, along with Fig. 3, showing all transistors (see rejection of Claim 1), positioned symmetrically. Claim 20: Watanabe, as modified, teaches the range imaging device according to Claim 1. Watanabe, as modified, does not wherein the N-sided polygonal shape is a pentagon, the transfer MOS transistors of the plurality of pixel signal reading circuits comprise two pairs of transfer MOS transistors symmetrically located with respect to the axis, and the at least one charge drainage MOS transistor comprises a charge drainage MOS transistor located on a side of the pentagon perpendicular to the axis. However, Kondo does teach that the polygonal shape can be any polygonal shape ([0118], [0146]). This, along with Fig. 15 of Kondo, showing the orientation of transistors 12, and previously discussed rejection of Claim 1, specifically regarding Watanabe and the configuration of individual transistors, would render the claim obvious. Different configurations of transistors (i.e.: in different polygonal shapes) would be obvious as this would simply be a rearrangement of parts. The function of the device, and the transistors, would be predictable no matter what configuration they are in, as transistors are well known in the art. Claim 21: Watanabe, as modified, teaches the range imaging device according to claim 18 the reset transistors of the plurality of pixel signal reading circuits comprise two pairs of reset transistors symmetrically positioned with respect to the axis, the source follower transistors of the plurality of pixel signal reading circuits comprise two pairs of source follower transistors symmetrically positioned with respect to the axis, and the selection transistors of the plurality of pixel signal reading circuits comprise two pairs of selection transistors symmetrically positioned with respect to the axis (Watanabe, Fig. 31, discharge mechanisms GD(n) positioned symmetrically, along with Fig. 3, showing all transistors (see rejection of Claim 1), positioned symmetrically. Claims 5, 8, 10, 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, in view of Kondo, in view of Kawahito (US 20190206915 A1). Claim 5: Watanabe, as modified, teaches the range imaging device according to Claim 1. Watanabe, as modified, does not teach, but Kawahito does teach, a microlens facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light, the microlens has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (Fig. 30, microlens 17 and [0144]). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the microlens as taught by Kawahito in the range imaging device as taught by Watanabe, as modified, because, as Kawahito teaches, this improves the sensitivity by improving the opening ratio ([0144]). Claim 8: Watanabe, as modified, teaches the range imaging device according to Claim 2. Watanabe, as modified, does not teach, but Kawahito does teach, a microlens facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light, the microlens has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (Fig. 30, microlens 17 and [0144]). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the microlens as taught by Kawahito in the range imaging device as taught by Watanabe, as modified, because, as Kawahito teaches, this improves the sensitivity by improving the opening ratio ([0144]). Claim 10: Watanabe, as modified, teaches the range imaging device according to Claim 3. Watanabe, as modified, does not teach, but Kawahito does teach, a microlens facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light, the microlens has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (Fig. 30, microlens 17 and [0144]). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the microlens as taught by Kawahito in the range imaging device as taught by Watanabe, as modified, because, as Kawahito teaches, this improves the sensitivity by improving the opening ratio ([0144]). Claim 12: Watanabe, as modified, teaches the range imaging device according to Claim 4. Watanabe, as modified, does not teach, but Kawahito does teach, a microlens facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light, the microlens has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (Fig. 30, microlens 17 and [0144]). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the microlens as taught by Kawahito in the range imaging device as taught by Watanabe, as modified, because, as Kawahito teaches, this improves the sensitivity by improving the opening ratio ([0144]). Claim 14: Watanabe, as modified, as modified, teaches a range imaging apparatus, comprising: a light receiving unit including the range imaging device of claim 5; and distance image processing circuitry configured to obtain a distance from the range imaging device to a subject based on a distance image captured by the range imaging device (Watanabe pg 4, TOF device). Claim 15: Watanabe, as modified, teaches the range imaging device according to Claim 7. Watanabe, as modified, does not teach, but Kawahito does teach, a microlens facing a surface of the pixel circuit such that the surface of the pixel circuit is positioned to receive the light, the microlens has an optical axis that is perpendicular to an entrance surface of the photoelectric conversion device and passes through a center of the entrance surface, and the entrance surface is positioned to receive the light (Fig. 30, microlens 17 and [0144]). It would have been prima facie obvious to someone having ordinary skill in the art before the effective filing date of the claimed invention to use the microlens as taught by Kawahito in the range imaging device as taught by Watanabe, as modified, because, as Kawahito teaches, this improves the sensitivity by improving the opening ratio ([0144]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CLARA CHILTON whose telephone number is (703)756-1080. The examiner can normally be reached Monday-Friday 6-2 MT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at 571-270-5227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CLARA G CHILTON/Examiner, Art Unit 3645 /HELAL A ALGAHAIM/SPE , Art Unit 3645
Read full office action

Prosecution Timeline

Apr 25, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection mailed — §103
Jun 18, 2026
Response Filed
Aug 06, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
54%
Grant Probability
66%
With Interview (+12.2%)
4y 1m (~9m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 72 resolved cases by this examiner. Grant probability derived from career allowance rate.

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