DETAILED ACTION
1. This action is in response to the RCE filed on 12/29/25.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
3. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
4. Claims 1 and 21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no disclosure in the specification as originally filed to indicate possession of the following:
Claim 1 the limitations recite “the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”; “the control terminal of the seventh transistor electrically shorted to the control terminal of the eight transistor”.
Claim 21 the limitation recites “the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”.
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 1 and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 the limitations recite “the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”; “the control terminal of the seventh transistor electrically shorted to the control terminal of the eight transistor”. It is unclear to what it meant by the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”; “the control terminal of the seventh transistor electrically shorted to the control terminal of the eight transistor”.
Claim 21 the limitation recites “the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”. It is unclear to what it meant by the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor”.
Claims 3 and 5-7 are rejected due to their dependency of claim 1.
Claim Rejections - 35 USC § 102
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1, 6-9, 11-18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fu et al. (US 20160268924).
Regarding claim 1: Fu et al. disclose an apparatus (i.e. figures 1-9), comprising:
a first transistor (i.e. Q1) having first and second terminals, the first terminal coupled to an input voltage terminal (i.e. voltage input to Q1);
a second transistor (i.e. Q2) having a and second terminals, wherein the first terminal of the second transistor (i.e. Q2) is coupled to the first second terminal of the first transistor (i.e. Q2);
a third transistor (i.e. Q3) having and second terminals, the first terminal of the third transistor (i.e. Q3) coupled to the second terminal of the second transistor (i.e. Q2);
a fourth transistor (i.e. Q4) having and second terminals, the first terminal of the fourth transistor (i.e. Q4) coupled to the terminal of the third transistor (i.e. Q3), the terminal of terminal of the third transistor (i.e. Q3), and the fourth current second terminal of the fourth transistor (i.e. Q4) coupled (i.e. electrically coupled) to a ground terminal (i.e. ground);
a first controllable resistive element (i.e. 106) including:
a fifth transistor (i.e. Q8) having first and second terminals and a control terminal, the first terminal of the fifth transistor (i.e. Q8) coupled to the second terminal of the first transistor (i.e. Q1) and to the first terminal of the second transistor (i.e. Q2); and
a sixth transistor (i.e. Q7) having first and second terminals and a control terminal, the first terminal of the sixth transistor (i.e. Q7) coupled to the second terminal of the fifth transistor (i.e. Q8), the second terminal of the sixth transistor (i.e. Q7) coupled to a second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2), the control terminal of the sixth transistor (i.e. Q7) electrically short (i.e. electrically coupled via the input/output of transistor Q7 and Q8) to the control terminal of the fifth transistor (i.e. Q8); and
a second resistive element (i.e. 104) including:
a seventh transistor (i.e. Q5) having first and second terminals and a control terminal, the first terminal of the seventh transistor (i.e. Q5) coupled to the second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2); and
an eighth transistor (i.e. Q6) having first and second terminals and a control terminal, the first terminal of the eighth transistor coupled to the second terminal of the seventh transistor (i.e. Q5), the second terminal of the eighth transistor (i.e. Q5) coupled to the second terminal of the third transistor (i.e. Q3) and to the first terminal of the fourth transistor (i.e. Q4), the control terminal of the seventh transistor (i.e. Q5) electrically (i.e. electrically coupled/shorted via the input/output of transistor Q7 and Q8) to the control terminal of the eighth transistor (i.e. Q6).
Regarding claim 6: a first capacitor (i.e. C3) having first and second terminals, the first terminal of the first capacitor (i.e. C3) coupled the second terminal of the first transistor (i.e. Q1) and to the first terminal of the second transistor (i.e. Q2), the second terminal of the first capacitor (i.e. C3) coupled to the second terminal of the third transistor (i.e. Q3) and to the first terminal of the fourth transistor (i.e. Q4); and
a second capacitor (i.e. C2) coupled (i.e. electrically coupled) between the second voltage terminal (i.e. terminal between Q1, Q2) and the ground terminal (i.e. ground).
Regarding claim 7: a third capacitor (i.e. Co) coupled between an output voltage terminal (i.e. terminal Vo) and the ground terminal (i.e. ground): and
an inductor (i.e. Lo) having first and second terminals, the first terminal of the inductor coupled (i.e. electrically coupled) to the second terminal of the second transistor (i.e. Q2) and to the first terminal of the third transistor (i.e. Q3), the second terminal of the inductor (i.e. Lo) coupled to the output voltage terminal (i.e. terminal Vo).
Regarding claim 8: Fu et al. disclose an apparatus (i.e. figures 1-9), comprising:
a first transistor (i.e. Q1) having first and second terminals, the first terminal coupled to an input voltage terminal (i.e. voltage input to Q1);
a second transistor (i.e. Q2) having a and second terminals, wherein the first terminal of the second transistor (i.e. Q2) is coupled to the first second terminal of the first transistor (i.e. Q2);
a third transistor (i.e. Q3) having and second terminals, the first terminal of the third transistor (i.e. Q3) coupled to the second terminal of the second transistor (i.e. Q2);
a fourth transistor (i.e. Q4) having and second terminals, the first terminal of the fourth transistor (i.e. Q4) coupled to the terminal of the third transistor (i.e. Q3), the terminal of terminal of the third transistor (i.e. Q3), and the fourth current second terminal of the fourth transistor (i.e. Q4) coupled (i.e. electrically coupled) to a ground terminal (i.e. ground);
a first resistive element (i.e. Q8) having first and second terminals and a control terminal, the first terminal of the first resistive element (i.e. Q8) coupled (i.e. electrically coupled) to the second terminal of the first transistor (i.e. Q1) and to the first terminal of the second transistor (i.e. Q2), the second terminal of the first resistive element (i.e. Q8) coupled to a second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2);
a second resistive element (i.e. Q6) having first and second terminals and a control terminal, the first terminal of the second resistive element (i.e. Q6) coupled (i.e. electrically coupled) to the second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2), the second terminal of the second resistive element (i.e. Q8) coupled to the second terminal of the third transistor (i.e. Q3) and to the first terminal of the fourth transistor (i.e. Q4);
a controller (i.e. controller for figure 1) coupled to the first, second, third, and fourth control terminals of the first, second, third, and fourth transistors (i.e. Q1) (i.e. Q2) (i.e. Q3) (i.e. Q4) and to the control terminals of the first and second resistive elements (i.e. Q8) (i.e. Q6), wherein during a time period in which the controller (i.e. controller for figure 1) provides a first control signal having a de-asserted value to the control terminal of the first resistive element (i.e. Q8) and a second control signal having the de-asserted value to the control terminal of the fourth transistor (i.e. Q4), the controller is capable of providing a third control signal having an asserted value to the control terminal of the second resistive element (i.e. Q6) followed by providing a fourth control signal having the asserted value to the control terminal of the first transistor (i.e. Q1) (i.e. see switch status tables).
Regarding claim 9: (i.e. figures 1-9) wherein the time period is a first time
period, and during a second a time period in which the controller provides the third control signal having the de-asserted value to the control terminal of the second resistive element (i.e. Q6) and the fourth control signal having the de-asserted value to the control terminal of the first transistor (i.e. Q1) (i.e. see switch status tables),
the controller is capable of providing the first control signal having the asserted value to the control terminal of the first resistive element (i.e. Q1) followed by providing the second control signal having the asserted value to the control terminal of the fourth transistor (i.e. Q4) (i.e. see switch status tables).
Regarding claim 11: (i.e. figures 1-9) a capacitor (i.e. C3) having first and second terminals, the first terminal of the capacitor coupled to the second terminal of the first transistor (i.e. Q1) and to the first terminal of the second transistor (i.e. Q2), the second terminal of the capacitor (i.e. C3) coupled to the second terminal of the third transistor (i.e. Q3) and to the first terminal of the fourth transistor (i.e. Q4).
Regarding claim 12: wherein the capacitor is a first capacitor (i.e. C3), and the apparatus further comprising a second capacitor (i.e. C2) coupled (i.e. electrically coupled) between the second voltage terminal (i.e. terminal between Q1, Q2) and the ground terminal (i.e. ground).
Regarding claim 13: (i.e. figures 1-9) wherein the controller (i.e. controller for figure 1) controls the first resistive element (i.e. Q8) to snub a commutation of the second transistor (i.e. Q2), and controls the second resistive element (i.e. Q6) to snub a commutation of the first transistor (i.e. Q1) (i.e. operation of the controller).
Regarding claim 14: (i.e. figures 1-9) wherein the first resistive element includes: a fifth transistor (i.e. Q8) having first and second terminals and a control terminal, the first terminal of the fifth transistor (i.e. Q7) coupled (i.e. electrically coupled) to the second terminal of the first transistor (i.e. Q1) and to the first terminal of the second transistor (i.e. Q2); and
a sixth transistor (i.e. Q7) having first and second terminals and a control terminal, the first terminal of the sixth transistor (i.e. Q7) coupled (i.e. electrically coupled) to the second terminal of the fifth transistor (i.e. Q8), the second terminal of the sixth transistor (i.e. Q7) coupled to the second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2), the control terminal of the sixth transistor (i.e. Q7) coupled (i.e. electrically coupled) to the control terminal of the fifth transistor (i.e. Q8), the controller coupled to the control terminals of the fifth and sixth transistors (i.e. Q8) (i.e. Q7).
Regarding claim 21: (i.e. figures 1-9) the control terminal of the sixth transistor (i.e. Q7) electrically short (i.e. electrically coupled/shorted via the input/output of transistor Q7 and Q8) to the control terminal of the fifth transistor (i.e. Q8).
Regarding claim 15: wherein the second resistive element includes:
a seventh transistor (i.e. Q5) having transistor having first and second terminals and a control terminal, the first terminal of the seventh transistor (i.e. Q5) coupled (i.e. electrically coupled) to the second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2); and
an eighth transistor (i.e. Q6) having first and second terminals and a control terminal, the first terminal of the eighth transistor (i.e. Q6) coupled to the second terminal of the seventh transistor (i.e. Q5), the second terminal of the eighth transistor (i.e. Q6) coupled (i.e. electrically coupled) to the second terminal of the third transistor (i.e. Q3) and to the first terminal of the fourth transistor (i.e. Q4), the control terminal of the seventh transistor (i.e. Q5) coupled (i.e. electrically coupled) to the control terminal of the eighth transistor (i.e. Q6), the controller coupled (i.e. electrically coupled) to the control terminals of the seventh and eighth transistor (i.e. Q5) (i.e. Q6).
Regarding claim 16: (i.e. figures 1-9) a third capacitor (i.e. Co) coupled between an output voltage terminal and the ground terminal; and an inductor (i.e. Lo) having first and second terminals, the first terminal of the inductor (i.e. Lo) coupled to the second terminal of the second transistor (i.e. Q2) and to the first terminal of the third transistor (i.e. Q3), the second terminal of the inductor (i.e. Lo) coupled to the output voltage terminal (i.e. terminal Vo).
Regarding claim 17: Fu et al. disclose (i.e. figures 1-9) A method for controlling transistors of a power converter comprising a first, second, third and fourth transistors (i.e. Q1) (i.e. Q2) (i.e. Q3) (i.e. Q4) coupled in series between an input voltage terminal (i.e. input terminal of Q1) and a ground terminal (i.e. ground) and further comprising a first resistive element (i.e. Q7) (i.e. Q8) coupled (i.e. electrically coupled) between a terminal of the first transistor (i.e. Q1) and a second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2) and a second resistive element (i.e. Q5) and/or (i.e. Q6) coupled (i.e. electrically coupled) between the second voltage terminal (i.e. terminal between C1, C2 or terminal between Q1, Q2) and a terminal of the fourth transistor (i.e. Q4), the method comprising, during a time period starting with a first time, followed by a second time, followed by a third time, and ending with a fourth time (i.e. see switch status tables for first to fourth time):
providing a first control signal to a control terminal of the fourth transistor (i.e. Q4) starting at the first time, the first control signal having a de-asserted value (i.e. Q4 off); and
providing a second control signal to a control terminal of the first resistive element (i.e. Q8) and/or (i.e. Q7) starting at the second time, the second control signal having the de-asserted value (i.e. Q7 or Q8 off);
providing a third control signal to a control terminal of the second resistive element (i.e. Q5) and/or (i.e. Q6) starting at the third time, the third control signal having an asserted value (i.e. Q5 or Q6 on); and
providing a fourth control signal to a control terminal of the first transistor (i.e. Q1) starting at the fourth time, the fourth control signal having the asserted value (i.e. Q1 on) (i.e. see switch status tables).
Regarding claim 18: wherein the time period is a first time period, the method further comprising, during a second time period starting with a fifth time, followed by a sixth time, followed by a seventh time, and ending with an eighth time (i.e. see switch status tables for fifth to eight time):
providing the fourth control signal to the control terminal of the first transistor (i.e. Q1) starting at the fifth time, the fourth control signal having the de-asserted value (i.e. Q1 on);
providing the third control signal to the control terminal of the second resistive element (i.e. Q5) and/or (i.e. Q6) starting at the sixth time, the third control signal having the de-asserted value (i.e. Q5 or Q6 off);
providing the second control signal to the control terminal of the first resistive element (i.e. Q8) and/or (i.e. Q7) starting at the seventh time, the second control signal having the asserted value (i.e. Q8 or Q7 on); and
providing the first control signal to the control terminal of the fourth transistor (i.e. Q4) starting at the eighth time, the first control signal having the asserted value (i.e. Q4 on) (i.e. see switch status tables).
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 3, 5, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (US 20160268924).
Regarding claims 3 and 5: Scoones et al. discloses the claimed invention except for a resistance of the first resistive element is determined according to ½*√LC, in which L is a parasitic inductance of the apparatus and C is a parasitic capacitance of the apparatus. It would have been an obvious to one having ordinary skill in the art at the time the invention was made to modify Fu et al.’s invention to have a resistance of the first resistive element is determined according to ½*√LC in order to increase the efficiency of the power supply. Since, the examiner takes Office Notice of the equivalence of a parasitic inductance of the apparatus and C is a parasitic capacitance of the apparatus for their use in the art and the selection of any of these known equivalents to the resistance of the first resistive element would be within the level of ordinary skill in the art.
Regarding claim 10: Fu et al. discloses the claimed invention except for a resistance of each of the first resistive element and the second resistive element is determined according to ½*√LC, in which L is a parasitic inductance of the apparatus and C is a parasitic capacitance of the apparatus.
It would have been an obvious to one having ordinary skill in the art at the time the invention was made to modify Fu et al.’s invention to have a resistance of the first and second resistive element is determined according to ½*√LC in order to increase the efficiency of the power supply. Since, the examiner takes Office Notice of the equivalence of a parasitic inductance of the apparatus and C is a parasitic capacitance of the apparatus (i.e. Scoones et al., figure 8) for their use in the art and the selection of any of these known equivalents to the resistance of the first and second resistive element would be within the level of ordinary skill in the art.
11. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fu et al. (US 20160268924) in view of Scoones et al. (US 10075080).
Regarding claim 19: Fu et al. disclose the limitation of the claim(s) as discussed above, but does not specifically disclose the first resistive element and the second resistive element are field-effect transistors (FETs) each having a drain-to-source resistance equal to a critical damping factor of the apparatus.
Scoones et al. disclose a power supply (i.e. figure 8) comprising the resistive element and the second resistive element are field-effect transistors (FETs) (i.e. 825, 827) each having a drain-to-source resistance (i.e. any value of the transistors of 825,827) equal to a critical damping factor of the apparatus.
Therefore, it would have been obvious to one with ordinary skill in the art before the earliest effective filing date to modify the circuit of Fu et al.’s invention with the power supply as disclose by Scoones et al., because the use of the three-level switching converter significantly reduces current ripple and also enables the employment of physically smaller inductors, thus increasing the power density.
Allowable Subject Matter
12. Claims 2 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
13. Applicant's arguments filed 12/29/25 have been fully considered but they are not persuasive.
Claim 1, Applicant argues that “as amended, claim 1 recites, in part, "the control terminal of the sixth transistor electrically shorted to the control terminal of the fifth transistor" and "the control terminal of the seventh transistor electrically shorted to the control terminal of the eighth transistor." The references cited in the Office Action, including Fu and Scoones, are not alleged to, and indeed do not, render these features of claim 1 unpatentable.”
The Examiner disagrees, because Fu et al. disclose (i.e. equivalent shows in parentheses) the control terminal of the sixth transistor (i.e. Q7) electrically short (i.e. electrically coupled/shorted via the input/output of transistor Q7 and Q8) to the control terminal of the fifth transistor (i.e. Q8).
Claim 3, Applicant argues that “nowhere does Fu even mention a resistor (or a resistive device/element) or a resistance (or impedance), much less teaching or suggesting the specific resistance recited in claim 3. In addition, Fu teaches "a five- level inverter apparatus," rather than "a three-level switching power supply." It is thus unclear why and how it would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Fu's invention to have a resistance as recited in claim 3 of this Application. For at least these reasons, claim 3 is not obvious in view of Fu.”
The Examiner disagrees, because Fu et al.’s figure 1 shows the bidirectional switches 106, 104 having the function as “a resistive element” when they are turn on. In addition, the transitional term “comprising”, which is synonymous with “including,” “containing,” or “characterized by,” is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. Furthermore, “comprising” is a term of art used in claim language which means that the named elements are essential, but other elements may be added and still form a construct within the scope of the claim (see Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501, 42 USPQ2d 1608, 1613 (Fed. Cir. 1997). Therefore, it would have been an obvious to one having ordinary skill in the art at the time the invention was made to modify Fu et al.’s invention to have a resistance of the first resistive element is determined according to ½*√LC in order to increase the efficiency of the power supply. Since, the examiner takes Office Notice of the equivalence of a parasitic inductance of the apparatus and C is a parasitic capacitance of the apparatus for their use in the art and the selection of any of these known equivalents to the resistance of the first resistive element would be within the level of ordinary skill in the art.
Claim 6, Applicant’s arguments with respect to claim(s) 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument (see the above rejection).
Claim 8, Applicant argues that “Id. at p. 6. However, in the switch status tables of Fu (see, e.g., FIG. 2, reproduced above), there is no mode in which the control terminals of both Q4 and Q8 have a de-asserted value (e.g., "0"), while the control terminals of both Q1 and Q6 have an asserted value (e.g., "1"). In fact, in all modes shown in the switch status tables of Fu, the control terminals of Q4 and Q8 have opposite values (rather than the same de-asserted value), and the control terminals of Q1 and Q6 have opposite values (rather than the same asserted value). For at least these reasons, Fu fails to teach or suggest all features of claim 8.”
The Examiner disagrees, because the limitation of claim 8 does not require to have a de-asserted value (i.e. “0”) for the control terminals of the first resistive element and the fourth transistor (Q8 and Q4 as in the rejection, respectively) and to have an asserted value (i.e. “1”) for the control terminals of the second resistive element and the first transistor (Q6 and Q1 as in the rejection, respectively) simultaneously. In addition, “a time period” recited in claim 8 is broadly considered as anytime period of which the controller is operate (for example, start time to end time) (similar response applied for claim 17).
Conclusion
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGUYEN TRAN whose telephone number is (571)270-1269. The examiner can normally be reached Flex: M-F 8-7.
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/Nguyen Tran/Primary Examiner, Art Unit 2838