Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 21-40 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 28, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Shoaib et al., US Patent Application Publication 2016/0267111 (hereinafter Shoaib) in view of Steinfadt, US Patent Application Publication 2012/0239706 (hereinafter Steinfadt).
Regarding claim 21, Shoaib teaches:
A graphics processing unit comprising: an interconnect to a host device (see e.g. image processing accelerator 210 is connected to host device 219); and a matrix accelerator (see e.g. fig. 5, systolic array architecture 500 is a matrix processing accelerator), the matrix accelerator configured to perform a set of parallel dot product operations on the elements of input matrices (see e.g. fig. 5, para. [0055-60], [0070-1], the systolic array including 2D-PEs performs parallel dot product operations), the matrix accelerator including multiple parallel processor lanes associated with multiple pipeline stages (see e.g. fig. 5, 7, para. [0055-60], processing is done through parallel lanes of 2D-PEs in pipelined stages with the output of one 2D-PE passed to the next 2D-PE in a row/column), each of the multiple pipeline stages including a set of interconnected multipliers and adders (see e.g. para. [0055], multiply-accumulate units), the multiple pipeline stages configured to perform multiple concurrent matrix operations (see e.g. fig. 5, para. [0057], matrix processing is performed concurrently across the array of processing elements).
Shoaib fails to explicitly teach a compute cluster including a plurality of streaming multiprocessors, a streaming multiprocessor of the plurality of streaming multiprocessors including: a register file configured to store elements of input matrices, and performing operations in response to a single instruction.
Steinfadt teaches a compute cluster including a plurality of streaming multiprocessors (see e.g. para. [0232], [0235], [0331]), a streaming multiprocessor of the plurality of streaming multiprocessors including: a register file configured to store elements of input matrices (para. [0331], [0344], the memories can be registers and store elements of matrix data), as well as using a single instruction (SIMD) to cause a set of parallel matrix operations to be performed (see e.g. para. [0074]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Shoaib and Steinfadt to include a compute cluster including a plurality of streaming multiprocessors, a streaming multiprocessor of the plurality of streaming multiprocessors including: a register file configured to store elements of input matrices, and performing operations in response to a single instruction. Applying the matrix processing to include GPU and SIMD components such as discussed by Steinfadt would have provided an advantage such as described by Steinfadt that “GPUs are very affordable and massively parallel. The hardware has a low cost with many current computers and laptops containing CUDA-enabled graphics cards already, and the software tools are free.” (see para. [0242]).
Regarding claim 28, Shoaib in view of Steinfadt teaches or suggests:
The graphics processing unit as in claim 21, further comprising a scheduler microcontroller configured to schedule the single instruction to a processing resource selected from one of the matrix accelerator and a functional unit that is external to the matrix accelerator (see e.g. Steinfadt para. [0337], a controller can schedule and control operations for external or remote processing units).
Regarding claim 31, Shoaib teaches:
A method comprising: performing a set of matrix operations on elements of input matrices (see e.g. fig. 5, para. [0055-60], [0070-1], the systolic array including 2D-PEs performs parallel dot product operations); determining a set of pipeline commands to perform to execute operations on a matrix accelerator including multiple pipeline stages (see e.g. para. [0057-9], a set of operations are performed on the systolic array); scheduling the set of pipeline commands to the multiple pipeline stages of the matrix accelerator to execute operations (see e.g. para. [0057], operations are managed/scheduled); and executing operations across one or more parallel processor lanes associated with the multiple pipeline stages (see e.g. fig. 5, 7, para. [0055-60], processing is done through parallel lanes of 2D-PEs in pipelined stages with the output of one 2D-PE passed to the next 2D-PE in a row/column), wherein the multiple pipeline stages include one or more sets of interconnected multipliers and adders (see e.g. para. [0055], multiply-accumulate units) to compute multiple concurrent matrix operations (see e.g. fig. 5, para. [0057], matrix processing is performed concurrently across the array of processing elements).
Shoaib fails to explicitly teach fetching and decoding a single instruction to be executed within a general-purpose graphics processing unit (GPGPU), the single instruction decoded into a decoded instruction to cause the GPGPU to perform the operations.
Steinfadt teaches a GPGPU (see e.g. para. [0232-5]) and decoding a single instruction (SIMD) to cause the GPGPU to perform matrix operations (see e.g. para. [0074]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Shoaib and Steinfadt to include fetching and decoding a single instruction to be executed within a general-purpose graphics processing unit (GPGPU), the single instruction decoded into a decoded instruction to cause the GPGPU to perform the operations. Applying the matrix processing to include GPU and SIMD components such as discussed by Steinfadt would have provided an advantage such as described by Steinfadt that “GPUs are very affordable and massively parallel. The hardware has a low cost with many current computers and laptops containing CUDA-enabled graphics cards already, and the software tools are free.” (see para. [0242]).
Claims 29-30, 34-36 are rejected under 35 U.S.C. 103 as being unpatentable over Shoaib in view of Steinfadt, further in view of Karthikeyan et al., US Patent Application Publication 2014/0195783 (hereinafter Karthikeyan).
Regarding claim 29, Shoaib in view of Steinfadt teaches or suggests:
The graphics processing unit as in claim 28.
Shoaib in view of Steinfadt fails to explicitly teach wherein the single instruction is associated with a predication mask, the predication mask to enable or disable one or more channels of one or more parallel processor lanes of the multiple parallel processor lanes.
Karthikeyan teaches using a mask for a dot product operation to enable or disable an operation (see e.g. para. [0084-8]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Shoaib, Steinfadt, and Karthikeyan such that the single instruction is associated with a predication mask, the predication mask to enable or disable one or more channels of one or more parallel processor lanes of the multiple parallel processor lanes. This would have been desirable to provide additional programmer control and flexibility to only operate on certain elements or reduce unnecessary processing.
Regarding claim 30, Shoaib in view of Steinfadt and Karthikeyan teaches or suggests:
The graphics processing unit as in claim 29, wherein the one or more parallel processor lanes are single instruction multiple data (SIMD) lanes (see e.g. Steinfadt para. [0061], [0074], [0135-6]) and each channel of the one or more parallel processor lanes is associated with one or more multi-element vectors (see e.g. Shoaib para. [0018], [0050-1], Steinfadt para. [0135-6]).
Regarding claim 34, Shoaib in view of Steinfadt teaches or suggests:
The method as in claim 31, to generate a set of products based on an elementwise multiply of source input elements (see e.g. Shoaib para. [0051]).
Shoaib in view of Steinfadt fails to explicitly teach wherein the set of pipeline commands to perform to execute the decoded instruction on the matrix accelerator causes the matrix accelerator to evaluate a write enable mask to determine a set of enabled parallel processing channels and, for each enabled parallel processing channel, to generate a set of products based on an elementwise multiply of source input elements.
Karthikeyan teaches using a mask for a dot product operation to enable or disable an operation (see e.g. para. [0084-8]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Shoaib, Steinfadt, and Karthikeyan such that the set of pipeline commands to perform to execute the decoded instruction on the matrix accelerator causes the matrix accelerator to evaluate a write enable mask to determine a set of enabled parallel processing channels and, for each enabled parallel processing channel, to generate a set of products based on an elementwise multiply of source input elements. This would have been desirable to provide additional programmer control and flexibility to only operate on certain elements or reduce unnecessary processing.
Regarding claim 35, Shoaib in view of Steinfadt and Karthikeyan teaches or suggests:
The method as in claim 34, the set of pipeline commands to additionally cause the matrix accelerator to calculate a sum of the set of products and add the sum to a value in an accumulator within a pipeline stage of the multiple pipeline stages (see e.g. Shoaib para. [0052], Karthikeyan para. [0063]).
Regarding claim 36, Shoaib in view of Steinfadt and Karthikeyan teaches or suggests:
The method as in claim 35, additionally comprising outputting the sum to the accumulator of a subsequent pipeline stage or to a destination register based on a calculation depth configured for the decoded instruction (see e.g. Shoaib para. [0067], accumulated based on being at the depth of the last row/column).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,042,370 in view of Steinfadt, which teaches a compute cluster including a plurality of streaming multiprocessors (see e.g. para. [0232], [0235], [0331]). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application are substantially similar to the claims in the ‘370 patent. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of the reference application and Steinfadt to include a compute cluster including a plurality of streaming multiprocessors such as GPU and SIMD components as in Steinfadt that would have provided an advantage such as described by Steinfadt that “GPUs are very affordable and massively parallel. The hardware has a low cost with many current computers and laptops containing CUDA-enabled graphics cards already, and the software tools are free.” (see para. [0242]).
Claims 21-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11,640,297 in view of Steinfadt, which teaches a compute cluster including a plurality of streaming multiprocessors (see e.g. para. [0232], [0235], [0331]). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in the instant application are substantially similar to the claims in the ‘370 patent. Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of the reference application and Steinfadt to include a compute cluster including a plurality of streaming multiprocessors such as GPU and SIMD components as in Steinfadt that would have provided an advantage such as described by Steinfadt that “GPUs are very affordable and massively parallel. The hardware has a low cost with many current computers and laptops containing CUDA-enabled graphics cards already, and the software tools are free.” (see para. [0242]).
Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Woolley, JR. et al., US Patent Application Publication 2016/0162402, teaches a streaming multiprocessor system for performing matrix operations.
Allowable Subject Matter
Claims 22-27, 32-33, 37-40, while rejected on the ground of nonstatutory double patenting, are allowable over the prior art. The following is a statement of reasons for the indication of allowable subject matter over the prior art:
In particular, the prior art, independently or in combination, does not anticipate and reasonably teach the specific aspects of wherein the instruction is to specify a number of pipeline stages of the multiple pipeline stages to use to execute the instruction (in combination with all other features of each respective claim).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at 5712703995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN M LINDLOF/ Primary Examiner, Art Unit 2183