Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application claims foreign priority based on Korean Patent Application No. KR10-2022-0063287, filed 05/24/2022.
A certified copy of Korean Patent Application No. KR10-2022-0063287 in Korean has been received (on 06/07/2023), as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Akopyan (US 9269044 B2) in view of Yajima (US 20220014179 A1) Regarding claim 1, Akopyan teaches a synaptic circuit including synapses arranged in a plurality of rows and a plurality of columns; (See e.g. [C7:L52 – 54], The cross-point array 3 communicates its state to the pre-synaptic circuits and to post-synaptic circuits and is driven by them.) (See e.g. [C12:L34 – 37], There are N row_request signals for a neuron array with N rows [a plurality of rows]. Neurons handshake with the AER system using a col_request wire to indicate their column addresses. There are N col_request signals for a neuron array with N columns [a plurality of columns].)
an axon circuit configured to generate a first input spike signal to be provided to a first row among the plurality of rows, and a second input spike signal to be provided to a second row among the plurality of rows; (See e.g. [C1:L60 - 63], a synapse interconnecting an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, wherein a neuron integrates input spikes [generate a input spike signal] and generates a spike event in response to the integrated input spikes exceeding a threshold.) (See e.g. [C4:29 – 31], Axonal neurons 18 [first input] and 20 [second input] are shown with outputs 30 and 32 connected to axons (e.g., wordlines or access lines) 34 [first row] and 36 [second row], respectively.) (See e.g. [C5:L24 – 26], Each synapse stores a bit that can be read, set, or reset from a row (axon) or column (dendrite) in the crossbar 12.)
[an input spike detecting circuit configured to generate an enable signal] when detecting a pulse from at least one of the first input spike signal and the second input spike signal; (See e.g. [C4:L39 – 45], Neurons 18 and 20 will “fire” (transmit a pulse) in response to the inputs they receive from external input connections (not shown), typically from other neurons, exceeding a threshold.)
first accumulated signal, which is output from a first column among the plurality of columns (See e.g. [C4:L22 – 45], Neurons 11 are also connected to the crossbar 12 via axon paths/wires (axons) 15 such as axons 34 and 36. Neurons 14 and 16 are dendritic neurons and neurons 18 and 20 are axonal neurons connected with axons 13. …In general, in accordance with an embodiment of the invention, neurons 14 [which is output from a first column among the plurality of columns] and 16 will “fire” (transmit a pulse) in response to the inputs they receive from axonal input connections [first accumulated signal] (not shown) exceeding a threshold.) (See e.g. [C5:L24 – 26], Each synapse stores a bit that can be read, set, or reset from a row (axon) or column (dendrite) in the crossbar 12.)
Akopyan does not teach an input spike detecting circuit configured to generate an enable signal a first neuron circuit configured to: compare a voltage level of a first accumulated signal, which is output from a first column among the plurality of columns, with a threshold voltage level in response to the enable signal; and output a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level.
Yajima teaches an input spike detecting circuit configured to generate an enable signal (See e.g. [0329], the inhibitory circuit 34 and the activation circuit 34a (an input circuit) increase or decrease the voltage of the node N1 when the input spike signal 50 is input as the input signal …a frequency detection circuit that generates the spike signal 52 based on the frequency of the spike signal 50 can be achieved.)
a first neuron circuit configured to: compare a voltage level of a [first accumulated] signal, [which is output from a first column among the plurality of columns], with a threshold voltage level in response to the enable signal; (See e.g. [0293], FIG. 32B, when the voltage Vin is 1 V [with a threshold voltage level in response to the enable signal], the voltage of the node N1 reaches 0.5 V [compare a voltage level of a signal]. Thus, the spike signal 52 is generated. The intervals at which the spike signal 52 is generated are 30.3 ms, and the frequency is 33 Hz.)
and output a first output spike signal when the voltage level of the [first accumulated] signal exceeds the threshold voltage level. (See e.g. [0293], FIG. 32B, when the voltage Vin is 1 V, the voltage of the node N1 reaches 0.5 V. Thus, the spike signal 52 is generated [output a first output spike signal]. The intervals at which the spike signal 52 is generated are 30.3 ms, and the frequency is 33 Hz.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Akopyan and Yajima before them, to include Yajima’s threshold voltage level which would allow Akopyan’s model to update voltage associated with a spike when a threshold is met. One would have been motivated to make a such a combination in order to reduce power consumption, as suggested by Yajima (US 20220014179 A1) (0121)
Regarding claim 6, Akopyan teaches the method of claim 1. Akopyan further teaches [wherein the input spike detecting circuit is further configured to generate the enable signal by performing an OR operation on] the first input spike signal and the second input spike signal. (See e.g. [C1:L60 - 63], a synapse interconnecting an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, wherein a neuron integrates input spikes [input spike signal] and generates a spike event in response to the integrated input spikes exceeding a threshold.) (See e.g. [C4:29 – 31], Axonal neurons 18 [first input] and 20 [second input] are shown with outputs 30 and 32 connected to axons (e.g., wordlines or access lines) 34 and 36, respectively.)
Akopyan does not teach wherein the input spike detecting circuit is further configured to generate the enable signal by performing an OR operation
Yajima teaches wherein the input spike detecting circuit is further configured to generate the enable signal by performing an OR operation (See e.g. [0549], As seen above, the spike signals from a plurality of paths may be input to the input terminal 71a of one FF circuit 70d using the combinational circuit such as the OR circuit 78c. The FF circuit 70d outputs the high level, as a bit signal [generate the enable signal] L/H2, to the output terminal 72b when the spike signal is input to the input terminal 71a.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Akopyan and Yajima before them, to include Yajima’s generation of an enable signal by an OR operation which would allow Akopyan’s model to perform logic operations on input signals. One would have been motivated to make a such a combination in order to implement logic detection to ensure a neuron is received by Yajima (US 20220014179 A1) (0340)
Regarding claim 7, Akopyan teaches the method of claim 1. Akopyan further teaches wherein a first synapse located in the first column is further configured to generate a first operation signal by performing an operation of the first input spike signal and a first weight signal, wherein a second synapse located in the first column is further configured to generate a second operation signal by performing an operation of the second input spike signal and a second weight signal (See e.g. [C3:L46 – 50], each synapse interconnects an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron. Each neuron integrates input spikes and generates a spike event in response to the integrated input spikes exceeding a threshold) (See e.g. [C6:L50 – 53], a vertical update (dendritic synapse update in crossbar 12) is for updating (setting/resetting) weights of synapses in a column of the crossbar 12.)
Akopyan does not teach wherein the first neuron circuit is further configured to generate the first accumulated signal by accumulating a charge amount of the first operation signal and a charge amount of the second operation signal.
Yajima teaches wherein the first neuron circuit is further configured to generate the [first accumulated] signal by [accumulating] a charge amount of the [first] operation signal [and a charge amount of the second operation signal.] (See e.g. [0031], an input circuit that increases a voltage of an intermediate node by an amount corresponding to an input spike signal when the input spike signal is input to an input terminal, and/or decreases the voltage of the intermediate node by the amount corresponding to the input spike signal when the input spike signal is input to the input terminal) (See e.g. [0525], For example, in FIG. 8 of the third embodiment, the voltage of the node N1 (corresponding to the intermediate node Ni) is proportional to the value of integral of the current Iin input to the input terminal 75 (Tin). At time t58, when the internal state S reaches a threshold state Sth, the spike generation circuit 74 outputs the spike signal 52 as the voltage Vout.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Akopyan and Yajima before them, to include Yajima’s charged signal generation which would allow Akopyan’s model to accumulate voltage/potential to be equivalent to accumulating a charge amount. One would have been motivated to make a such a combination in order to increase or decrease voltage in response to input spike which would allow for the accumulating a charge amount by Yajima (US 20220014179 A1) (0383)
Regarding claim 9, Akopyan teaches generating a first input spike signal; (See e.g. [C1:L60 - 63], a synapse interconnecting an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, wherein a neuron integrates input spikes [generate a input spike signal] and generates a spike event in response to the integrated input spikes exceeding a threshold.) (See e.g. [C4:29 – 31], Axonal neurons 18 [first input] and 20 are shown with outputs 30 and 32 connected to axons (e.g., wordlines or access lines) 34 and 36, respectively.)
generating a second input spike signal; (See e.g. [C1:L60 - 63], a synapse interconnecting an axon of a pre-synaptic neuron with a dendrite of a post-synaptic neuron, wherein a neuron integrates input spikes [generate a input spike signal] and generates a spike event in response to the integrated input spikes exceeding a threshold.) (See e.g. [C4:29 – 31], Axonal neurons 18 and 20 [second input] are shown with outputs 30 and 32 connected to axons (e.g., wordlines or access lines) 34 and 36, respectively.)
determining whether at least one of the first input spike signal and the second input spike signal has a pulse; (See e.g. [C4:L39 – 45], Neurons 18 and 20 will “fire” (transmit a pulse) in response to the inputs they receive from external input connections (not shown), typically from other neurons, exceeding a threshold.)
[generating an enable signal] when it is determined that at least one of the first input spike signal and the second input spike signal has a pulse; (See e.g. [C4:L39 – 45], Neurons 18 and 20 will “fire” (transmit a pulse) in response to the inputs they receive from external input connections (not shown), typically from other neurons, exceeding a threshold.)
Akopyan does not teach generating an enable signal, comparing a voltage level of an accumulated signal with a threshold voltage level in response to the enable signal; and generating an output spike signal when the voltage level of the accumulated signal exceeds the threshold voltage level.
Yajima teaches generating an enable signal (See e.g. [0170], As described previously, the inverting circuit 16 outputs an inversion signal [enable signal] of the signal of the node N1 to the gate of the FET 14 and the node N2 (a second node).)
comparing a voltage level of an [accumulated] signal with a threshold voltage level in response to the enable signal; and (See e.g. [0293], FIG. 32B, when the voltage Vin is 1 V [with a threshold voltage level], the voltage of the node N1 reaches 0.5 V. (See e.g. [0499], The comparator X50 compares the voltage V11 of the node N11, which is closer to the end T11 of the path L11, with the voltage V12 of the node N12, which is closer to the end T12 of the path L12, and outputs the output voltage Vout [comparing a voltage level of a signal])
generating an output spike signal when the voltage level of the [accumulated] signal exceeds the threshold voltage level. (See e.g. [0293], FIG. 32B, when the voltage Vin is 1 V, the voltage of the node N1 reaches 0.5 V. Thus, the spike signal 52 is generated [output spike signal]. The intervals at which the spike signal 52 is generated are 30.3 ms, and the frequency is 33 Hz.)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Akopyan and Yajima before them, to include Yajima’s threshold voltage level which would allow Akopyan’s model to update voltage associated with a spike when a threshold is met. One would have been motivated to make a such a combination in order to reduce power consumption, as suggested by Yajima (US 20220014179 A1) (0121)
Allowable Subject Matter
Claims 2objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ALLMAN THOMPSON whose telephone number is (571)272-3671. The examiner can normally be reached Monday - Thursday, 6 a.m. - 3 p.m. ET..
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/K.A.T./ Examiner, Art Unit 2125
/KAMRAN AFSHAR/ Supervisory Patent Examiner, Art Unit 2125
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