Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to amendment filed on February 19, 2026
Claims 1 – 10 are presented for examination.
Claims 1 and 9 have been amended.
Examiner’s Note:
Support for the limitations added to independent claims 1 and 9, using respective similar language, e.g. “generate the enable signal having a second logic level when not detecting a pulse from the first input spike signal and the second input spike signal”, can be found in [0046], “When not detecting a pulse from at least one of the first to N-th input spike signals SP1 to SPN, the input spike detecting circuit 140 may generate the enable signal EN having a second logic level.” of the instant application’s specification as filed on 04/26/2023.
Support for the limitations added to independent claims 1 and 9, using respective similar language, “refrain from comparing the voltage level of the first accumulated signal with the threshold voltage level in response to the enable signal having the second logic level.”, can be found in [0042], “When receiving the enable signal EN having a second logic level, the first neuron 131 may not compare the voltage level of the first accumulated signal with the threshold voltage level.” of the original specification.
Response to Arguments
With respect to 103:
Applicant’s arguments with respect to claims 1, 6, 7 and 9 have been considered but are moot because the arguments do not apply to the combinations of references used in the current rejections. In particular, as discussed in detail below, a new combination of references (i.e., the newly-cited Merolla reference in view of the newly-cited BEIDAS reference) is applied to reject amended independent claim 1 as well as dependent claims 6 and 7, and BEIDAS is applied to reject independent claim 9.
These rejections were necessitated by applicant’s amendments.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 9 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by BEIDAS (US 20230100670 A1)
Regarding claim 9, BEIDAS discloses An operating method of a spike neural network circuit, the method comprising: (See e.g. [0029], ““spiking neuron” is understood as an artificial neuron suitable for a spiking neural network.”)
generating a first input spike signal; (See e.g. [0113], “The pulse capturing elements 611, … may be configured to generate and send a signal (e.g. a high signal, 1, or a pulse) to the respective weight releasing elements 621, … after the respective pulse capturing element 611,… has detected an input spike signal.” [i.e., pulse capturing elements 611 may be configured to generate and send a signal corresponding to generating a first input spike signal.])
generating a second input spike signal; (See e.g. [0113], “The pulse capturing elements …, 612, …may be configured to generate and send a signal (e.g. a high signal, 1, or a pulse) to the respective weight releasing elements …, 622, … after the respective pulse capturing element …, 612, … has detected an input spike signal.” [i.e., pulse capturing elements 612 may be configured to generate and send a signal corresponding to generating a second input spike signal.])
determining whether at least one of the first input spike signal and the second input spike signal has a pulse; (See e.g. [0119], “Accordingly, with each trigger signal indicating a received input spike signal from one of the inputs 601, 602,…,” [i.e., received input spike signal from one of the inputs 601, 602 corresponding to determining whether at least one of the first input spike signal and the second input spike signal has a pulse.] “the membrane potential accumulator 640 may perform accumulation to obtain the integration value based on the determined weights for the instance of time.”)
generating an enable signal having a first logic level when it is determined that at least one of the first input spike signal and the second input spike signal has a pulse; (See e.g. [0118], “the weight releasing elements 621, 622,… may be configured to provide weights to the adder 630 with a positive transition of the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal.” [i.e., the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal corresponding to generate an enable signal having a first logic level.])
generating the enable signal having a second logic level when it is determined that the first input spike signal and the second spike signal don't have a pulse; (See e.g. [0150], “there are no pulses that the trigger signal generates as seen in 940, 1040.” [i.e., there are no pulses that the trigger signal generates corresponding to when not detecting a pulse.] “The oscillator operates in the first operating mode (e.g. a low power mode/turned off) as seen in 950, and the oscillator activator does not activate the oscillator with a signal 960.” See e.g. [0152], “The oscillator activator may be configured so, such that the first trigger signal 941, 1041 may trigger the oscillator activator to activate the oscillator 961 with a negative transition of the first trigger signal 941, 1041 (from a signal of a high level to a low level)” [i.e., the first trigger signal 941 corresponding to generate the enable signal having a second logic.] “substantially at a second instance of time (t2).”)
comparing a voltage level of an accumulated signal with a threshold voltage level in response to the enable signal having the first logic level; (See e.g. [0145], “There may be one or more spike inputs that the neuron circuit received, and the neuron circuit may sum 808 the released weights of the plurality of inputs that received an input spike. The neuron circuit may perform the accumulation 809 (i.e. accumulate the membrane potential “ACMP”) 809 with the sum of weights. After the neuron circuit performs the accumulation, the neuron circuit may compare the accumulated membrane potential (ACMP) and a membrane potential threshold (T) 810.” [i.e., neuron circuit may compare the accumulated membrane potential (ACMP) and a membrane potential threshold (T) 810 corresponding to compare a voltage level of a first accumulated signal with a threshold.], for further clarification on voltage level, see [0053], “As exemplarily shown in FIG. 4, the metric may be the voltage of an electrical signal, which may be referred as membrane potential similar to biological neurons.”)
refraining from comparing the voltage level of the accumulated signal with the threshold voltage level in response to the enable signal having the second logic level; and (See e.g. [0150], “At the first operation mode, there are no pulses that the trigger signal generates as seen in 940, 1040.” [i.e., there are no pulses that the trigger signal generates corresponding to the enable signal having the second logic level.] “The oscillator operates in the first operating mode (e.g. a low power mode/turned off) as seen in 950.”)
generating an output spike signal when the voltage level of the accumulated signal exceeds the threshold voltage level. (See e.g. [0146], “If the accumulated membrane potential is above 810 the membrane potential threshold (T), the neuron circuit may output 813 a spike to be transmitted to a plurality of post-synaptic neuron circuits.”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Merolla (NPL: A Digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm) in view of BEIDAS (US 20230100670 A1) Regarding claim 1, Merolla teaches a synaptic circuit including synapses arranged in a plurality of rows and a plurality of columns; (See e.g. [Abstract:P1:C1], “we fabricated a key building block of a modular neuromorphic architecture, a neurosynaptic core,” [i.e., a neurosynaptic core corresponding to a synaptic circuit including synapses.] “with 256 digital integrate-and-fire neurons and a 1024×256 bit SRAM crossbar memory for synapses using IBM’s 45nm SOI process.” See e.g. [S2:P2:Fig. 1], “The core consists of axons, represented as rows” [i.e., axons represented as rows corresponding to a plurality of rows.]; “dendrites, represented as columns” [i.e., dendrites represented as columns corresponding to a plurality of columns.]; “synapses”, “represented as row–column junctions; and neurons that receive inputs from dendrites. The parameters that describe the core have integer ranges as indicated.”)
an axon circuit configured to generate a first input spike signal to be provided to a first row among the plurality of rows, and a second input spike signal to be provided to a second row among the plurality of rows; (See e.g. [S3:P2:C2], “Based on these considerations, we arrived at a block-level implementation of our neurosynaptic core that consists of an input decoder with 1024 axon circuits…In the first phase, address-events are sent to the core one at a time, and these events are sequentially decoded to the appropriate axon block” [i.e. axon block corresponding to first and second row among the plurality of rows.] “(e.g., axon 3 from Fig. 2). On receiving an event, the axon activates the SRAM’S row” [i.e., axon activates corresponding to input spike signal.], “which reads out all of the axon’s connections as well as its type.”)
Merolla does not teach an input spike detecting circuit configured to: generate an enable signal having a first logic level when detecting a pulse from at least one of the first input spike signal and the second input spike signal;
However, in the same field, analogous art BEIDAS teaches an input spike detecting circuit configured to: generate an enable signal having a first logic level when detecting a pulse from at least one of the first input spike signal and the second input spike signal; (See e.g. [0117], “the integration value at an initial mode of operation in which the neuron circuit has not received any input spike” [i.e., neuron circuit has not received any input spike corresponding to input spike detecting circuit.] “signals may be equal to the resting membrane potential.” See e.g. [0118], “the weight releasing elements 621, 622,… may be configured to provide weights to the adder 630 with a positive transition of the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal.” [i.e., the trigger signal (e.g. when the pulse signal changes from a low signal to a high (0 to 1) signal corresponding to generate an enable signal having a first logic level.] See e.g. [0119], “Accordingly, with each trigger signal indicating a received input spike signal from one of the inputs 601, 602, …,” [i.e., received input spike signal from one of the inputs 601, 602 corresponding to detecting a pulse from at least one of the first input spike signal and the second input spike signal.] “the membrane potential accumulator 640 may perform accumulation to obtain the integration value based on the determined weights for the instance of time.”)
generate the enable signal having a second logic level when not detecting a pulse from the first input spike signal and the second input spike signal; and (See e.g. [0150], “there are no pulses that the trigger signal generates as seen in 940, 1040.” [i.e., there are no pulses that the trigger signal generates corresponding to when not detecting a pulse.] “The oscillator operates in the first operating mode (e.g. a low power mode/turned off) as seen in 950, and the oscillator activator does not activate the oscillator with a signal 960” See e.g. [0152], “The oscillator activator may be configured so, such that the first trigger signal 941, 1041 may trigger the oscillator activator to activate the oscillator 961 with a negative transition of the first trigger signal 941, 1041 (from a signal of a high level to a low level)” [i.e., the first trigger signal 941 corresponding to generate the enable signal having a second logic.] “substantially at a second instance of time (t2).”)
a first neuron circuit configured to: compare a voltage level of a first accumulated signal, which is output from a first column among the plurality of columns, with a threshold voltage level in response to the enable signal having the first logic level; (See e.g. [0032], “The terminology used as “input”, “intermediate” and “output” are used only in order to refer to the corresponding neurons and/or layers that provide input and output to the neurons (or layer) 112, 114, 116, 118 illustrated in the middle layer.” [i.e., input and output to the neurons (or layer) 112, 114, 116, 118 illustrated in the middle layer corresponding to which is output from a first column among the plurality of columns.] See e.g. [0145], “There may be one or more spike inputs that the neuron circuit received, and the neuron circuit may sum 808 the released weights of the plurality of inputs that received an input spike. The neuron circuit may perform the accumulation 809 (i.e. accumulate the membrane potential “ACMP”) 809 with the sum of weights. After the neuron circuit performs the accumulation, the neuron circuit may compare the accumulated membrane potential (ACMP) and a membrane potential threshold (T) 810.” [i.e., neuron circuit may compare the accumulated membrane potential (ACMP) and a membrane potential threshold (T) 810 corresponding to compare a voltage level of a first accumulated signal, which is output from a first column among the plurality of columns.], for further clarification on voltage level, see [0053], “As exemplarily shown in FIG. 4, the metric may be the voltage of an electrical signal, which may be referred as membrane potential similar to biological neurons.”))
output a first output spike signal when the voltage level of the first accumulated signal exceeds the threshold voltage level. (See e.g. [0146], “If the accumulated membrane potential is above 810 the membrane potential threshold (T), the neuron circuit may output 813 a spike to be transmitted to a plurality of post-synaptic neuron circuits.”)
refrain from comparing the voltage level of the first accumulated signal with the threshold voltage level in response to the enable signal having the second logic level. (See e.g. [0150], “At the first operation mode, there are no pulses that the trigger signal generates as seen in 940, 1040.” [i.e., there are no pulses that the trigger signal generates corresponding to the enable signal having the second logic level.] “The oscillator operates in the first operating mode (e.g. a low power mode/turned off) as seen in 950.”)
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Merolla and BEIDAS before them, to include BEIDAS’s threshold voltage level which would allow Merolla’s model to update voltage associated with a spike when a threshold is met. One would have been motivated to make a such a combination in order to reduce wasted power consumption in a circuit, as suggested by BEIDAS (0150)
Regarding claim 6, Merolla in view of BEIDAS teaches he method of claim 1.
Merolla does not teach wherein the input spike detecting circuit is further configured to generate the enable signal by performing an OR operation on the first input spike signal and the second input spike signal.
However, in the same field, analogous art BEIDAS teaches wherein the input spike detecting circuit is further configured to generate the enable signal by performing an OR operation on the first input spike signal and the second input spike signal. (See e.g. [0106], “Each of the pulse capturing elements 611, 612,… may provide an indication of a received input spike signal from the respective input 601, 602, … to the corresponding weight releasing element 621, 622,…. Furthermore, the signal detector may include a trigger circuit including a pulse trigger 680 and an OR gate 681.” [i.e., an OR gate 681 corresponding to generate the enable signal by performing an OR operation.])
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teaching of Merolla and BEIDAS before them, to include BEIDAS’s threshold voltage level which would allow Merolla’s model to update voltage associated with a spike when a threshold is met. One would have been motivated to make a such a combination in order to reduce wasted power consumption in a circuit, as suggested by BEIDAS (0150)
Regarding claim 7, Merolla in view of BEIDAS teaches the method of claim 1. Merolla further teaches wherein a first synapse located in the first column is further configured to generate a first operation signal by performing an operation of the first input spike signal and a first weight signal, (See e.g. [S2:P2:C1], “At each time step t, each axon j is presented with an activity bit Aj(t) that represents whether its corresponding neuron fired in the previous time step… Correspondingly, neuron i weighs synaptic input from axon j of type Gj ∈ {0,1,2} as SGj i . Thus, neuron i receives the following input from axon j: Aj(t) × Wji ×SGj i .” See e.g. [S3:P2:C2], “For each time step, the detailed operation of the core commences in two phases: the first phase implements the axon-driven component, and the second phase implements a time step synchronization.”)
wherein a second synapse located in the first column is further configured to generate a second operation signal by performing an operation of the second input spike signal and a second weight signal, and (See e.g. [S2:P2:C1], “At each time step t, each axon j is presented with an activity bit Aj(t) that represents whether its corresponding neuron fired in the previous time step… Correspondingly, neuron i weighs synaptic input from axon j of type Gj ∈ {0,1,2} as SGj i . Thus, neuron i receives the following input from axon j: Aj(t) × Wji ×SGj i .” See e.g. [S3:P2:C2], “For each time step, the detailed operation of the core commences in two phases: the first phase implements the axon-driven component, and the second phase implements a time step synchronization.”)
wherein the first neuron circuit is further configured to generate the first accumulated signal by accumulating a charge amount of the first operation signal and a charge amount of the second operation signal. (See e.g. [S3:P2:C2], “All the connections that exist (all the 1’s) are then sent to their respective neurons,” [i.e., All the connections that exist (all the 1’s) are then sent to their respective neurons corresponding to accumulated signal by accumulating a charge amount of the first operation signal and a charge amount of the second operation signal.] “which perform the appropriate membrane potential updates;”)
Allowable Subject Matter
Claims 2 - 5, 8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYLE ALLMAN THOMPSON whose telephone number is (571)272-3671. The examiner can normally be reached Monday - Thursday, 6 a.m. - 3 p.m. ET..
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/K.A.T./Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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