CTNF 18/307,838 CTNF 96556 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 04/27/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 6, 13, 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Claim 6, 13, 19 recite “the selected encoding format” and “the resulting difference.” The limitations lack of antecedent basis. Looks like claim 6, 13, 19 should be a dependent claim of claim 5, claim 12, claim 18, respectively. Appropriate correction is required. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-3, 8-10, 14-16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Li (US 20180189000) . Regarding Claim 1, Li teaches A computer-implemented method for handling a logical-to-physical address translation table, the method comprising: (Li [0001] an apparatus, method, and system for logical block address to physical block address (L2P) table compression.) implementing a class of metadata including a logical-to-physical table (LPT) and LPT entries corresponding to the class of metadata ; (Li [0002] a solid state drive (SSD) comprising NAND memory cells has an indirection table, a logical block address to physical block address (L2P) table to convert logical addresses, such as logical block addresses (LBAs), to NAND physical block addresses (PBAs). [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries) (i.e. L2P table entries is a class of metadata) caching, from the logical-to-physical translation layer, selected metadata blocks in a non-durable cache, the selected metadata blocks being selected from the class of metadata; (Li [0050] to service an L2P lookup request…the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC)). reducing a size of the selected metadata blocks by encoding the LPT entries from the non-durable cache during write operations to a flash memory; (Li [0034] IU data items includes the IU data for IUs with table entries [0057] the compression engine 120 load the IU data from memory or from the storage die (e.g., NAND Flash memory) (i.e., compressing/encoding reducing the size of IU/LPT data) and recording a location in flash memory of the encoded LPT entries in the logical-to-physical translation layer. (Li [0044] these pages (e.g., NAND Flash pages) are read to check whether they still have the valid L2P information by comparing the storage die address (e.g., NAND address) and the pointer in the corresponding compression unit.) Regarding Claim 2, Li teaches Li teaches decoding the encoded LPT entries from the flash memory during read operations of the set of metadata blocks to the non-durable cache. (Li [0034] IU data items includes the IU data for IUs with table entries [0037] the decompression technique is the reverse process of the compression technique. [0050] the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC))) Regarding Claim 3, Li teaches Li teaches responsive to user input/output (I/O) write requests to write data, performing I/O operations on metadata blocks of the selected metadata blocks including page-in and page-out operations between the non-durable cache and a flash memory. (Li [0019] an approach that effectively compresses the L2P table in memory for a non-volatile memory (e.g., on an SSD) and couples that with paging to handle the worst case of an incompressible L2P table. [0074] an apparatus for compressing a logical block address to physical block address (L2P) table, comprising: a non-volatile memory to store user data [0050] the compression engine 120 decompresses the IU data to a local buffer) Regarding Claim 8, Li teaches A computer program product comprising a computer-readable storage medium having a set of instructions stored therein which, when executed by a processor, causes the processor to perform a method comprising: (Li [0001] an apparatus, method, and system for logical block address to physical block address (L2P) table compression.) implementing a class of metadata including a logical-to-physical table (LPT) and LPT entries corresponding to the class of metadata ; (Li [0002] a solid state drive (SSD) comprising NAND memory cells has an indirection table, a logical block address to physical block address (L2P) table to convert logical addresses, such as logical block addresses (LBAs), to NAND physical block addresses (PBAs). [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries) (i.e. L2P table entries is a class of metadata) caching, from the logical-to-physical translation layer, selected metadata blocks in a non-durable cache, the selected metadata blocks being selected from the class of metadata; (Li [0050] to service an L2P lookup request…the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC)). reducing a size of the selected metadata blocks by encoding the LPT entries from the non-durable cache during write operations to a flash memory; (Li [0034] IU data items includes the IU data for IUs with table entries [0057] the compression engine 120 load the IU data from memory or from the storage die (e.g., NAND Flash memory) (i.e., compressing/encoding reducing the size of IU/LPT data) and recording a location in flash memory of the encoded LPT entries in the logical-to-physical translation layer. (Li [0044] these pages (e.g., NAND Flash pages) are read to check whether they still have the valid L2P information by comparing the storage die address (e.g., NAND address) and the pointer in the corresponding compression unit.) Regarding Claim 9, Li teaches Li teaches decoding the encoded LPT entries from the flash memory during read operations of the set of metadata blocks to the non-durable cache. (Li [0034] IU data items includes the IU data for IUs with table entries [0037] the decompression technique is the reverse process of the compression technique. [0050] the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC))) Regarding Claim 10, Li teaches Li teaches responsive to user input/output (I/O) write requests to write data, performing I/O operations on metadata blocks of the selected metadata blocks including page-in and page-out operations between the non-durable cache and a flash memory. (Li [0019] an approach that effectively compresses the L2P table in memory for a non-volatile memory (e.g., on an SSD) and couples that with paging to handle the worst case of an incompressible L2P table. [0074] an apparatus for compressing a logical block address to physical block address (L2P) table, comprising: a non-volatile memory to store user data [0050] the compression engine 120 decompresses the IU data to a local buffer) Regarding Claim 14, Li teaches A computer system for handling logical-to-physical table (LPT) entries, the computer system comprising: a processor set; and a computer readable storage medium; wherein: the processor set is structured, located, connected, and/or programmed to run program instructions stored on the computer readable storage medium; and the program instructions which, when executed by the processor set, cause the processor set to perform a method comprising: (Li [0001] an apparatus, method, and system for logical block address to physical block address (L2P) table compression.) implementing a class of metadata including a logical-to-physical table (LPT) and LPT entries corresponding to the class of metadata ; (Li [0002] a solid state drive (SSD) comprising NAND memory cells has an indirection table, a logical block address to physical block address (L2P) table to convert logical addresses, such as logical block addresses (LBAs), to NAND physical block addresses (PBAs). [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries) (i.e. L2P table entries is a class of metadata) caching, from the logical-to-physical translation layer, selected metadata blocks in a non-durable cache, the selected metadata blocks being selected from the class of metadata; (Li [0050] to service an L2P lookup request…the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC)). reducing a size of the selected metadata blocks by encoding the LPT entries from the non-durable cache during write operations to a flash memory; (Li [0034] IU data items includes the IU data for IUs with table entries [0057] the compression engine 120 load the IU data from memory or from the storage die (e.g., NAND Flash memory) (i.e., compressing/encoding reducing the size of IU/LPT data) and recording a location in flash memory of the encoded LPT entries in the logical-to-physical translation layer. (Li [0044] these pages (e.g., NAND Flash pages) are read to check whether they still have the valid L2P information by comparing the storage die address (e.g., NAND address) and the pointer in the corresponding compression unit.) Regarding Claim 15, Li teaches Li teaches decoding the encoded LPT entries from the flash memory during read operations of the set of metadata blocks to the non-durable cache. (Li [0034] IU data items includes the IU data for IUs with table entries [0037] the decompression technique is the reverse process of the compression technique. [0050] the compression engine 120 decompresses the IU data to a local buffer (e.g., a static random access memory (SRAM) buffer implemented inside an SSD silicon-on-chip (SOC))) Regarding Claim 16, Li teaches Li teaches responsive to user input/output (I/O) write requests to write data, performing I/O operations on metadata blocks of the selected metadata blocks including page-in and page-out operations between the non-durable cache and a flash memory. (Li [0019] an approach that effectively compresses the L2P table in memory for a non-volatile memory (e.g., on an SSD) and couples that with paging to handle the worst case of an incompressible L2P table. [0074] an apparatus for compressing a logical block address to physical block address (L2P) table, comprising: a non-volatile memory to store user data [0050] the compression engine 120 decompresses the IU data to a local buffer) Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 4, 11, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20180189000), in view of Cariello (US 20210349829) . Regarding Claim 4, Li teaches Li does not teach increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. However, Cariello teaches increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. (Cariello [0017] a memory device may calculate the physical address of any page of the pages of sequentially stored data based on the first physical address, or may read multiple sequential pages of data starting from the first physical address. Such sequentially stored data may be an example of or be referred to as a stream of data. [0088] a memory device may receive two or more interleaved streams of write commands…the memory device may identify different blocks of memory at which to write the data for each stream to enable the multiple streams to be associated with corresponding entries in a second-level L2P table) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Regarding Claim 11, Li teaches Li does not teach increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. However, Cariello teaches increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. (Cariello [0017] a memory device may calculate the physical address of any page of the pages of sequentially stored data based on the first physical address, or may read multiple sequential pages of data starting from the first physical address. Such sequentially stored data may be an example of or be referred to as a stream of data. [0088] a memory device may receive two or more interleaved streams of write commands…the memory device may identify different blocks of memory at which to write the data for each stream to enable the multiple streams to be associated with corresponding entries in a second-level L2P table) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Regarding Claim 17, Li teaches Li does not teach increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. However, Cariello teaches increasing a spatial locality of the written data by re-ordering the user I/O write requests according to related sequential data streams where there are multiple sequential data streams being written concurrently to the flash memory. (Cariello [0017] a memory device may calculate the physical address of any page of the pages of sequentially stored data based on the first physical address, or may read multiple sequential pages of data starting from the first physical address. Such sequentially stored data may be an example of or be referred to as a stream of data. [0088] a memory device may receive two or more interleaved streams of write commands…the memory device may identify different blocks of memory at which to write the data for each stream to enable the multiple streams to be associated with corresponding entries in a second-level L2P table) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data . 07-21-aia AIA Claim (s) 5-7, 12, 18, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20180189000), in view of Cariello (US 20210349829), further in view of Shaharabany ( US 20220114088) . Regarding Claim 5, Li teaches Li teaches encoding the LPT entries (Li [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries.) Li does not teach two consecutive LPT entries; storing the LPT entry However, Cariello teaches two consecutive LPT entries; storing the LPT entry (Cariello [0053] entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on.) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Li-Cariello does not teach subtracting fields of two consecutive LPT entries; and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. However, Shaharabany teaches subtracting fields of two consecutive LPT entries ; (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA.) and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. (Shaharabany [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 6, Li and Cariello teach Li-Cariello does not teach electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. However, Shaharabany teaches electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA. [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 7, Li teaches Li teaches wherein the encoding the LPT entries includes: reorganizing the LPT entries of the selected blocks according to field type such that fields of a first type are grouped together sequentially ; (Li [0021] the L2P table is compressed in groups of N consecutive indirection unit entries.) Li does not teach sequentially However, Cariello teaches sequentially (Cariello [0053] entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on.) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of entries for the L2P table. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Li-Cariello does not teach [encoding] according to field type such that fields of a first type; and applying encoding methods based on field types of the LPT entries, including the first type. However, Shaharabany teaches [encoding] according to field type such that fields of a first type; and applying encoding methods based on field types of the LPT entries, including the first type. (Shaharabany [0060] if the current entry is the last entry at block 7 14, then at block 716, the controller encodes the current L2P entry as the current entry in the delta buffer.) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 12, Li teaches Li teaches encoding the LPT entries (Li [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries.) Li does not teach two consecutive LPT entries; storing the LPT entry However, Cariello teaches two consecutive LPT entries; storing the LPT entry (Cariello [0053] entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on.) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Li-Cariello does not teach subtracting fields of two consecutive LPT entries; and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. However, Shaharabany teaches subtracting fields of two consecutive LPT entries ; (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA.) and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. (Shaharabany [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 18, Li teaches Li teaches encoding the LPT entries (Li [0022] compressing the L2P table by contiguous groups, and matching the size M to a cache-line size of an SSD controller of the SSD, allows efficient read and write of L2P table memory entries.) Li does not teach two consecutive LPT entries; storing the LPT entry However, Cariello teaches two consecutive LPT entries; storing the LPT entry (Cariello [0053] entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on.) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of sequentially store data. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Li-Cariello does not teach subtracting fields of two consecutive LPT entries; and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. However, Shaharabany teaches subtracting fields of two consecutive LPT entries ; (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA.) and responsive to a resulting difference between the two consecutive LPT entries being less than a pre-defined threshold, storing the LPT entry as a difference in a selected encoding format. (Shaharabany [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 20, Li teaches Li teaches wherein the encoding the LPT entries includes: reorganizing the LPT entries of the selected blocks according to field type such that fields of a first type are grouped together sequentially ; (Li [0021] the L2P table is compressed in groups of N consecutive indirection unit entries.) Li does not teach sequentially However, Cariello teaches sequentially (Cariello [0053] entries of a terminal L2P table may be ordered sequentially by an LBA index. For example, a first entry in a terminal L2P table (e.g.,) may include a first physical address that corresponds to LBA N (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries that includes a second physical address corresponding to LBA N+1, a third entry that includes a third physical address corresponding to LBA N+2, and so on.) Li and Cariello are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Cariello to modify the Li ‘s system for L2P table compression with Cariello’s teaching of entries for the L2P table. The motivation for doing so would be (Cariello [0023, 0074]) generating and using entries in L2P tables for sequentially stored data and building or updating a built L2P table that supports compressed logical-to-physical mapping for sequentially stored data. Li-Cariello does not teach [encoding] according to field type such that fields of a first type; and applying encoding methods based on field types of the LPT entries, including the first type. However, Shaharabany teaches [encoding] according to field type such that fields of a first type; and applying encoding methods based on field types of the LPT entries, including the first type. (Shaharabany [0060] if the current entry is the last entry at block 7 14, then at block 716, the controller encodes the current L2P entry as the current entry in the delta buffer.) Li, Cariello and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li, Cariello and Shaharabany to modify the Li-Cariello‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries . 07-21-aia AIA Claim (s) 13, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20180189000), in view of Shaharabany ( US 20220114088) Regarding Claim 13, Li teaches Li does not teach electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. However, Shaharabany teaches electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA. [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Shaharabany to modify the Li‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Regarding Claim 19, Li teaches Li does not teach electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. However, Shaharabany teaches electing the selected encoding format from a plurality of candidate encoding formats based on the resulting difference. (Shaharabany [0053] the controller calculates a PBA offset (G) from the previous absolute delta L2P entry, where the PBA offset is equal to an offset from the PBA of the data block. The PBA offset is calculated by subtracting the PBA of the last absolute entry from the current PBA. [0051] A new absolute delta L2P entry may be written after a threshold value of the PBA offset is exceeded. [0052] receives an encode command to encode a LBA to a delta L2P entry of a first data block, where the encode command includes a L2P_pair (A) and a last_absolute_entry field (B)) Li and Shaharabany are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Li and Shaharabany to modify the Li‘s system for L2P table compression with Shaharabany’s teaching of delta compression. The motivation for doing so would be to have (Shaharabany [0052]) a method of encoding LBA to delta L2P entries. Relevant Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Pham (US 20170364446) teaches compression and caching for logical-to-physical storage address mapping tables Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI MA whose telephone number is (571)272-2468. The examiner can normally be reached Monday through Friday from 8am to 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WEI MA/Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135 Application/Control Number: 18/307,838 Page 2 Art Unit: 2135 Application/Control Number: 18/307,838 Page 3 Art Unit: 2135 Application/Control Number: 18/307,838 Page 4 Art Unit: 2135 Application/Control Number: 18/307,838 Page 5 Art Unit: 2135 Application/Control Number: 18/307,838 Page 6 Art Unit: 2135 Application/Control Number: 18/307,838 Page 7 Art Unit: 2135 Application/Control Number: 18/307,838 Page 8 Art Unit: 2135 Application/Control Number: 18/307,838 Page 9 Art Unit: 2135 Application/Control Number: 18/307,838 Page 10 Art Unit: 2135 Application/Control Number: 18/307,838 Page 11 Art Unit: 2135 Application/Control Number: 18/307,838 Page 12 Art Unit: 2135 Application/Control Number: 18/307,838 Page 14 Art Unit: 2135 Application/Control Number: 18/307,838 Page 15 Art Unit: 2135 Application/Control Number: 18/307,838 Page 16 Art Unit: 2135 Application/Control Number: 18/307,838 Page 17 Art Unit: 2135 Application/Control Number: 18/307,838 Page 18 Art Unit: 2135 Application/Control Number: 18/307,838 Page 19 Art Unit: 2135 Application/Control Number: 18/307,838 Page 20 Art Unit: 2135 Application/Control Number: 18/307,838 Page 21 Art Unit: 2135 Application/Control Number: 18/307,838 Page 22 Art Unit: 2135 Application/Control Number: 18/307,838 Page 23 Art Unit: 2135
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