DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed December 3, 2025 has been entered. Claims 1-15 remain pending in the application.
Examiner notes that applicant has not amended the specification to overcome the objection provided in the Non-Final Office Action mailed October 27, 2025, and therefore, the objection remains.
Response to Arguments
Applicant’s arguments, see page 6, filed December 3, 2025, with respect to the rejections of claims 1-8 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of previously presented prior art reference Lacher (Patent Number US 3,916,216 A), hereafter referred to as Lacher.
Applicant's arguments, see pages 7-8, filed December 3, 2025, with respect to the rejections of claims 9-15 under 35 U.S.C. § 103 have been fully considered but they are not persuasive. Applicant argues that the previously presented prior art references fail to disclose continuously supplying the bias current by reducing its value stepwise according to the power voltage level, rendering the rejections invalid. Examiner respectfully disagrees.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., continuously supplying the bias current by reducing its value stepwise according to the power voltage level) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
As recited in independent claims 9 and 15, the overpower protection circuit provides two distinct bias current levels based on the power voltage being above certain voltage levels. This does not require continuously supplying the bias current by reducing its value stepwise according to the power voltage level. Therefore, applicant’s arguments are unconvincing and the rejections of claims 9-15 are maintained.
Specification
The use of the terms Wi-Fi®, WiMax®, LTE®, and BLUETOOTH® which are trade names or marks used in commerce, has been noted in this application (see Paragraph 47, lines 1-3). The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever they appear or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the term.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ishihara (Patent Publication Number US 2022/0239261 A1), as cited by applicant, hereafter referred to as Ishihara, in view of Lacher.
Regarding claim 1, Ishihara discloses:
A power amplifier (Ishihara, Figs. 3A, 4A, and 5) comprising: a power transistor (Fig. 3A, Tr12) configured to receive a power voltage (Fig. 3A, see connection between Vcc and Tr12); a first transistor (Fig. 3A, Tr22) including a first terminal (Fig. 3A, see emitter of Tr22) configured to provide a bias current to the power transistor (Fig. 3A, see bias current ib2 provided to Tr12 from Tr22); and an overpower protection circuit (Fig. 3A, 330) configured to generate a first current (Fig. 3A, see IOUT_OCP) corresponding to the power voltage (Fig. 3A, see that IOUT_OCP is derived from Vcc) and to provide the first current to a second terminal of the first transistor (Fig. 3A, see connection between IOUT_OCP and collector of Tr22), wherein the overpower protection circuit includes: a limiting current source (Fig. 4A, 2351) configured to provide a limiting current (Fig. 4A, see current IREF provided by 2351) to the second terminal of the first transistor (Fig. 4A, see that IREF has a sink current subtracted to be current IOUT_OCP provided to collector of transistor Tr22 in Fig. 3A); and a sink current generating circuit (Figs. 3A, 4A, and 5, see elements 335 and 338) including a second transistor (Fig. 5, 525b) that includes a control terminal (Fig. 5, see gate of 525b) to which a voltage corresponding to the power voltage is applied (Fig. 5, consider output voltage of 515 and relationship to power voltage Vcc) and a first terminal connected to the second terminal of the first transistor (Fig. 5, consider drain of 525b, and connection to current IVCC_PROP, coupled to current IREF via current mirror 3353 in Fig. 4A, and consider that IREF is coupled to current IOUT_OCP provided to collector of transistor Tr22 in Fig. 3A), and configured to sink a second current from the limiting current (Fig. 4A, consider that current IVCC_PROP determines current ISINK, which is subtracted from IREF to form IOUT_OCP), but fails to disclose [the first terminal of the second transistor] directly [connected to the second terminal of the first transistor].
However, Lacher teaches [the first terminal of the second transistor] directly [connected to the second terminal of the first transistor] (Lacher, Fig. 1, see direct connection between sink transistor 49 and bias transistor 51).
Ishihara and Lacher are both considered to be analogous to the claimed invention because they are in the same field of improving amplifier circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Ishihara to incorporate the teachings of Lacher to provide a direct connection between the sink transistor and bias transistor of Ishihara, which would have the effect of preventing deterioration of the output signal of Ishihara (Lacher, Col. 5, lines 17-20).
Regarding claim 2, Ishihara further discloses:
wherein when the power voltage increases, the second current increases, and the first current decreases (Ishihara, Fig. 4B, consider that when Vcc is above Vcc_lm, as Vcc increases, ISINK [the second current] increases, and IOUT_OCP [the first current] decreases).
Regarding claim 3, Ishihara further discloses:
wherein when the power voltage is higher than a first voltage, the first current decreases as the power voltage increases (Ishihara, Fig. 4B, consider that when Vcc is above Vcc_lm, as Vcc increases, IOUT_OCP [the first current] decreases).
Regarding claim 4, Ishihara further discloses:
wherein the first current has a value obtained by subtracting the second current from the limiting current (Ishihara, Fig. 4A, consider that IOUT_OCP [the first current] is obtained by subtracting ISINK [the second current] from IREF [the limiting current]).
Regarding claim 5, Ishihara further discloses:
wherein the sink current generating circuit further includes a first resistor (Ishihara, Fig. 5, R51) including a first end connected to the power voltage (Fig. 5, see connection between RF1 and Vcc) and a second resistor (Fig. 5, R52) connected between a second end of the first resistor and a ground (Fig. 5, see R52 between R51 and Vgnd), and the second end of the first resistor is connected to the control terminal of the second transistor (Fig. 5, see connection between R51 and gate of transistor 525b via element 515).
Regarding claim 6, Ishihara further discloses:
wherein the sink current generating circuit further includes a third resistor (Ishihara, Fig. 5, R55) connected to a second terminal of the second transistor (Fig. 5, see connection between source of 525b and R55 via transistor 525a) and the ground (Fig. 5, see connection between R55 and ground).
Regarding claim 7, Ishihara further discloses:
wherein the second current flows from the second terminal of the first transistor to the first terminal of the second transistor (Ishihara, Fig. 4A, consider that current ISINK coupled to current IOUT_OCP that is coupled to collector of Tr22 in Fig. 3A is coupled to current IVCC_PROP via current mirror 3353, and that IVCC_PROP is coupled to drain of 525b in Fig. 5).
Regarding claim 8, Ishihara further discloses:
wherein the first terminal of the first transistor is an emitter (Fig. 3A, see emitter of Tr22), and the second terminal of the first transistor is a collector (Fig. 3A, see collector of Tr22).
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Morisawa et al. (Patent Publication Number US 2021/0234523 A1), as cited by applicant, hereafter referred to as Morisawa, in view of Hisashi (Patent Number JP 4,066,303 B2), hereafter referred to as Hisashi.
Regarding claim 9, Morisawa discloses:
A power amplifier (Morisawa, Figs. 1 and 8) comprising: a power transistor (Fig. 1, Amp1, see also Paragraph 23, lines 1-2) configured to receive a power voltage (Fig. 1, see connection between Amp1 and Vcc); a first transistor (Fig. 1, Q2) including a first terminal (Fig. 1, see emitter of Q2) configured to provide a bias current to the power transistor (Fig. 1, see bias current Ib2 provided from emitter of Q2 to Amp1); and an overpower protection circuit (Fig. 1, Element 3) configured to generate a first current (Fig. 1, see current Ib2) corresponding to the power voltage (Fig. 1, consider that current Ib2 is derived from power voltage Vcc in protection circuit 3) and to provide the first current to a second terminal of the first transistor (Fig. 1, see connection between Ib2 and collector of Q2 via emitter of Q2), wherein the overpower protection circuit is configured to generate the first current having a first value when the power voltage is higher than a first reference voltage (Figs. 3B and 3E, consider that when Vdet is at high value (power voltage above first reference voltage, Ib2 has low value), but fails to disclose and the overpower protection circuit is configured to generate the first current having a second value when the power voltage is higher than a second reference voltage, and the second reference voltage is higher than the first reference voltage, and the second value is smaller than the first value.
However, Hisashi teaches and the overpower protection circuit is configured to generate the first current having a second value when the power voltage is higher than a second reference voltage (Hisashi, Fig. 1, consider current generated by control circuit 600 when voltage signal Lx is above reference signal LMTREF1), and the second reference voltage is higher than the first reference voltage (Fig. 2, consider that reference voltage LMTREF1 is higher than reference voltage LMTREF2), and the second value is smaller than the first value (Figs 2-3, consider that LMTREF1 restricts signal Lx entirely to the minimum value when comparator 100 is activated, while LMTREF2 restricts signal Lx to a value above the minimum value when comparator 300 is activated).
Morisawa and Hisashi are both considered to be analogous to the claimed invention because they are in the same field of improving protection circuits for amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Morisawa to incorporate the teachings of Hisashi to include an additional comparator system in the amplifier of Morisawa, which would have the effect of enabling both instantaneous and long-term protection for the amplifier of Morisawa (Hisashi, Paragraph 13, lines 1-6).
Regarding claim 10, Morisawa further discloses:
wherein the overpower protection circuit is configured to generate the first current having a third value when the power voltage is lower than the first reference voltage (Morisawa, Figs. 3B and 3E, consider value of Ib2 when Vdet is at low value), and the third value is larger than the first value (Figs. 3B and 3E, consider that when Vdet is at low value, Ib2 is at a high value).
Regarding claim 11, Morisawa further discloses:
wherein the overpower protection circuit includes: a first comparator (Morisawa, Fig. 8, see comparator 301 as part of overcurrent detection circuit 30) configured to compare the power voltage to the first reference voltage (Fig. 8, see comparison of V1 with Vref); but fails to disclose and a second comparator configured to compare the power voltage to the second reference voltage.
However, Hisashi further teaches and a second comparator (Hisashi, Fig. 1, 100) configured to compare the power voltage to the second reference voltage (Fig. 1, see comparison of signal Lx with reference voltage LMTREF1).
Morisawa and Hisashi are both considered to be analogous to the claimed invention because they are in the same field of improving protection circuits for amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Morisawa to incorporate the teachings of Hisashi to include an additional comparator system in the amplifier of Morisawa, which would have the effect of enabling both instantaneous and long-term protection for the amplifier of Morisawa (Hisashi, Paragraph 13, lines 1-6).
Regarding claim 12, Morisawa further discloses:
wherein the overpower protection circuit includes: a logic circuit (Morisawa, Fig. 1, 31) configured to receive an output of the first comparator (Fig. 1, see connection between comparator based detection circuit 30 and logic circuit 31) and a current source (Fig. 1, 34) configured to generate the first current in response to the logic signal (Fig. 1, see dependence of Ib2 [the first current] on activation of transistor Q1 controlled by signal from current source 34), but fails to disclose [the logic circuit configured to receive] and an output of the second comparator and to generate a logic signal.
However, Hisashi further teaches [the logic circuit configured to receive] and an output of the second comparator and to generate a logic signal (Hisashi, Fig. 1, see output of comparator 100 received by logic circuit 600, which generates logic signal to transistor 700).
Morisawa and Hisashi are both considered to be analogous to the claimed invention because they are in the same field of improving protection circuits for amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Morisawa to incorporate the teachings of Hisashi to include an additional comparator system in the amplifier of Morisawa, which would have the effect of enabling both instantaneous and long-term protection for the amplifier of Morisawa (Hisashi, Paragraph 13, lines 1-6).
Regarding claim 13, Morisawa further discloses:
wherein the first terminal of the first transistor is an emitter (Morisawa, Fig. 1, see emitter of Q2), and the second terminal of the first transistor is a collector (Fig. 1, see collector of Q2).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Morisawa in view of Hisashi, Ishihara, and Lacher.
Regarding claim 14, Morisawa discloses:
A power amplifier (Morisawa, Fig. 1) comprising: a power transistor (Fig. 1, Amp1, see also Paragraph 23, lines 1-2) configured to receive a power voltage (Fig. 1, see connection between Amp1 and Vcc); a transistor (Fig. 1, Q2) configured to provide a bias current to the power transistor (Fig. 1, see bias current Ib2 provided from emitter of Q2 to Amp1); and an overpower protection circuit (Fig. 1, Element 3) configured to: generate a first current (Fig. 1, see current Ib2) having a first value based on a comparison between the power voltage and a first reference voltage (Figs. 3B and 3E, consider levels of Ib2 based on level of Vdet); and provide the first current to the transistor (Fig. 1, see connection between Ib2 and Q2), but fails to disclose generate a second current having a second value based on a comparison between the power voltage and a second reference voltage; [and provide] or the second current [to the transistor], wherein the overpower protection circuit includes: a limiting current source configured to provide a limiting current to the transistor; and a sink current generating circuit including a second transistor that includes a control terminal to which a voltage corresponding to the power voltage is applied and a first terminal directly connected to the transistor, and configured to sink a second current from the limiting current.
However, Hisashi teaches generate a second current having a second value based on a comparison between the power voltage and a second reference voltage (Hisashi, Fig. 1, consider current generated by control circuit 600 when voltage signal Lx is above reference signal LMTREF1); [and provide] or the second current [to the transistor] (Fig. 1, see connection between control circuit 600 and transistor 700), but fails to teach wherein the overpower protection circuit includes: a limiting current source configured to provide a limiting current to the transistor; and a sink current generating circuit including a second transistor that includes a control terminal to which a voltage corresponding to the power voltage is applied and a first terminal directly connected to the transistor, and configured to sink a second current from the limiting current.
However, Ishihara teaches wherein the overpower protection circuit includes: a limiting current source (Ishihara, Fig. 4A, 2351) configured to provide a limiting current (Fig. 4A, see current IREF provided by 2351) to the transistor (Fig. 4A, see that IREF has a sink current subtracted to be current IOUT_OCP provided to collector of transistor Tr22 in Fig. 3A); and a sink current generating circuit (Figs. 3A, 4A, and 5, see elements 335 and 338) including a second transistor (Fig. 5, 525b) that includes a control terminal (Fig. 5, see gate of 525b) to which a voltage corresponding to the power voltage is applied (Fig. 5, consider output voltage of 515 and relationship to power voltage Vcc) and a first terminal connected to the transistor (Fig. 5, consider drain of 525b, and connection to current IVCC_PROP, coupled to current IREF via current mirror 3353 in Fig. 4A, and consider that IREF is coupled to current IOUT_OCP provided to collector of transistor Tr22 in Fig. 3A), and configured to sink a second current from the limiting current (Fig. 4A, consider that current IVCC_PROP determines current ISINK, which is subtracted from IREF to form IOUT_OCP), but fails to teach [the first terminal of the second transistor] directly [connected to the second terminal of the transistor].
However, Lacher teaches [the first terminal of the second transistor] directly [connected to the second terminal of the transistor] (Lacher, Fig. 1, see direct connection between sink transistor 49 and bias transistor 51).
Morisawa, Hisashi, Ishihara, and Lacher are all considered to be analogous to the claimed invention because they are in the same field of improving protection circuits for amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Morisawa to incorporate the teachings of Hisashi, Ishihara, and Lacher to include an additional comparator system in the amplifier of Morisawa, which would have the effect of enabling both instantaneous and long-term protection for the amplifier of Morisawa (Hisashi, Paragraph 13, lines 1-6), to include the protection circuit of Ishihara in the circuit of Morisawa, which would have the effect of enabling a continuous adjustment of the protection current based on increasing power levels (Ishihara, Fig. 4B, see relationship between IOUT_OCP and Vcc), and to provide a direct connection between the sink transistor and bias transistor of Ishihara, which would have the effect of preventing deterioration of the output signal of Morisawa (Lacher, Col. 5, lines 17-20).
Regarding claim 15, Morisawa fails to disclose:
wherein the second reference voltage is higher than the first reference voltage, and the second value is smaller than the first value.
However, Hisashi further teaches wherein the second reference voltage is higher than the first reference voltage (Hisashi, Fig. 2, consider that reference voltage LMTREF1 is higher than reference voltage LMTREF2), and the second value is smaller than the first value (Figs 2-3, consider that LMTREF1 restricts signal Lx entirely to the minimum value when comparator 100 is activated, while LMTREF2 restricts signal Lx to a value above the minimum value when comparator 300 is activated).
Morisawa, Hisashi, Ishihara, and Lacher are all considered to be analogous to the claimed invention because they are in the same field of improving protection circuits for amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Morisawa to incorporate the teachings of Hisashi to include an additional comparator system in the amplifier of Morisawa, which would have the effect of enabling both instantaneous and long-term protection for the amplifier of Morisawa (Hisashi, Paragraph 13, lines 1-6).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843