DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-9 11-17 and 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanno (US 2021/0064520).
Consider claim 1, Kanno discloses a memory system comprising: a storage device; an external interface circuit configured to receive a write logical address associated with a write command and a storage location for mapping information and store the write logical address in the storage location, and to set a first flag indicating whether storage of the write logical address has been completed; and a processor configured to determine the storage location at which the write logical address is to be stored within a map table and control the storage device to program write data associated with the write command, the map table storing map data between external logical addresses and physical addresses of the storage device, wherein the first flag is not transmitted to an external device at a time of setting the first flag (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses receiving write and read commands, determining where to write data and updating an L2P table to reflect where data is stored. The storage disclosed in Kanno can store a multitude of data (is shared). Kanno discloses a completion response that is stored in a completion queue. As for the new limitation, Kanno teaches that the completion response is generated by the write control unit and then sends the response to a completion queue of the host. “At a time of setting the first flag” is considered the time the response is generated and the sending occurs after that.).
Consider claim 2, Kanno discloses the memory system according to claim 1, wherein the external interface circuit is configured to start receiving the write data after the write logical address is stored in the storage location (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses L2P updates can happen before transfer of data or in parallel.).
Consider claim 3, Kanno discloses the memory system according to claim 1, wherein an interval in which the write logical address is stored in the storage location and an interval in which the write data is input are configured to partially overlap (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses L2P updates can happen before transfer of data or in parallel.).
Consider claim 5, Kanno discloses the memory system according to claim 1, wherein the processor is configured to set a second flag indicating whether the programming has been completed (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses a completion response that is stored in a completion queue.).
Consider claim 6, Kanno discloses the memory system according to claim 1, wherein: the processor is configured to set a second flag indicating whether the programming has been completed, and the processor is configured to process a read command based on the first flag and the second flag set for a read logical address associated with the read command (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses a completion response that is stored in a completion queue. The completion response is considered to meet the claim requirements of the first and second flags. A read for data can only be processed if that data is been previously successfully written.).
Claims 7-9, 11 and 12 are the memory controller claims to memory system claims 1-3, 5 and 6 above and are rejected in the same manner.
Claims 13-15 and 19-20 are the memory claims to memory system claims 1-3, 5 and 6 above and are rejected in the same manner.
Consider claim 16, Kanno discloses the operating method according to claim 13, wherein the receiving of the write logical address comprises: receiving, by the external interface circuit, the write command including the write logical address and an address length, from an external device; and storing, by the external interface circuit, the write logical address and the address length in the shared memory region (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses logical addresses and lengths are received/stored related to write commands.).
Consider claim 17, Kanno discloses the operating method according to claim 13, wherein the receiving of the storage location comprises: determining, by the processor, the storage location at which the write logical address is to be stored within a map table storing map data between external logical addresses and physical addresses of the storage device; storing, by the processor, the write logical address in the shared memory region; and reading, by the processor, the storage location from the shared memory region (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses a completion response that is stored in a completion queue. The completion response is considered to meet the claim requirements of the first and second flags. A read for data can only be processed if that data is been previously successfully written.).
Consider claim 21, Kanno discloses an operating method of a memory system, the operating method comprising: receiving, by an external interface circuit, a write command including a write logical address and an address length; receiving, by the external interface circuit, write data associated with the write command; and programming, by a processor, the write data associated with the write command in a storage device, wherein a map table storing map data between external logical addresses and physical addresses of the storage device is updated, by the external interface circuit, before the programming of the write data has been completed by the processor; and a first flag is set, by the external interface circuit, after completing update of the map table, wherein the first flag is not transmitted to an external device at a time of setting the first flag (abstract, [0028], [0055]-[0057], [0081], [0096]-[0097], [0170], [0178], [0187], Kanno discloses receiving write and read commands, determining where to write data and updating an L2P table to reflect where data is stored. The storage disclosed in Kanno can store a multitude of data (is shared). Kanno discloses L2P updates can happen before transfer of data or in parallel. Kanno discloses a completion response that is stored in a completion queue. As for the new limitation, Kanno teaches that the completion response is generated by the write control unit and then sends the response to a completion queue of the host. “At a time of setting the first flag” is considered the time the response is generated and the sending occurs after that.).
Response to Arguments
Applicant's arguments filed 4/3/2026 have been fully considered but they are not persuasive. The applicant’s arguments pertain to the new claim limitations which have been addressed in the appropriate claim rejections above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ALSIP whose telephone number is (571)270-1182. The examiner can normally be reached M-F 9-5.
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/MICHAEL ALSIP/Primary Examiner, Art Unit 2136
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