DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Foreign priority is not claimed for this application.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: #541 and #542, which are mentioned in paragraph 51 with regards to fig. 5a, are not shown in the figure. The drawings are also objected to because in par. 53 and 56 of the specification, it states that the first end of a first resistor (right end of #563) is coupled to a first input terminal #561 Vin+, but #561 is shown to be on the left of #563. The same issue is there for #573 and #571 Vin-. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
Par. 49, second and third to last lines: (S2, S2) should be (S1, S2)
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation "a first output terminal of a line driver" in line 2 and “a second output terminal” of the liner driver in line 3. However, a first output terminal and second output terminal of a line driver was already defined in claim 7, which this claim is dependent on. For examination purposes, examiner interprets the first and second output terminals and the line drivers from both claims to be the same one. Claim 14 inherits this rejection due to its dependence on claim 13. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-5, 7-9, 11-13, 15-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20190173429 by Seth et al.
Regarding claim 1, Seth teaches a system comprising (Fig. 1-3):
a first amplifier (Fig. 2 #210, Fig. 3 MP1a, MN1a, MN2a, MP2a) and a second amplifier (Fig. 2 #210, Fig. 3 MP1b, MN1b, MN2b, MP2b), wherein
the first amplifier (Fig. 2 #210 (which is shown in depth in fig.3)) and a first end of a first resistor (Fig. 2 #208a) are coupled to a first output terminal of a line driver (Fig. 2 #202) to receive a first signal (Fig. 2 #206a),
the second amplifier (Fig. 2 #210 (which is shown in depth in fig.3)) and a first end of a second resistor (Fig. 2 #208b) are coupled to a second output terminal of the line driver to receive a second signal (Fig. 2 #206b),
a second end of the second resistor (Fig. 2 #208b) and an output terminal of the first amplifier (Fig. 2 #222a connected to #208b) are coupled to an interface to a physical medium (Fig. 2 #110; Abstract),
a second end of the first resistor (Fig. 2 #208a) and an output terminal of the second amplifier (Fig. 2 #222b connected to #208a) are coupled to the interface (Fig. 2 #110),
the first amplifier is configured to generate a current at the second end of the second resistor, based at least on a voltage sensed from the first signal, to supply an additional current to the second signal traversing the second resistor towards the interface (Fig. 2 IOUT2, Par. 18-19, 25), and
the second amplifier is configured to generate a current at the second end of the first resistor, based at least on a voltage sensed from the second signal, to supply an additional current to the first signal traversing the first resistor towards the interface (Fig. 2 IOUT2, Par. 18-19, 25).
Regarding claim 2, Seth teaches the system of claim 1, wherein each of the first amplifier and the second amplifier is a transconductance amplifier (Par. 16).
Regarding claim 4, Seth teaches the system of claim 1, wherein each of the first amplifier and the second amplifier comprises a current mirror circuit configured to output a respective current in an output stage (Fig. 3 #222a and #222b).
Regarding claim 5, Seth teaches the system of claim 1, wherein at least one of the first amplifier or the second amplifier is a class AB amplifier (Fig. 3).
Regarding claim 7, Seth teaches a system (Fig. 1-3) comprising:
a first amplifier (Fig. 2 #210, Fig. 3 MP1a, MN1a, MN2a, MP2a) and a first resistor (Fig. 2 #214a) coupled to an input terminal of the first amplifier; and
a second amplifier (Fig. 2 #210, Fig. 3 MP1b, MN1b, MN2b, MP2b) and a second resistor (Fig. 2 #214b) coupled to an input terminal of the second amplifier, wherein
a first end of the first resistor (#214a) is coupled to a first output terminal of a line driver (Fig. 2 #202) to receive a first signal (Fig. 2 #206a),
a first end of the second resistor (#214b) is coupled to a second output terminal of the line driver to receive a second signal (Fig. 2 #206b),
an output terminal of the second amplifier (Fig. 2 #222b) is coupled to a first terminal of an interface to a physical medium (Fig. 2 + input of #110),
an output terminal of the first amplifier (Fig. 2 #222a) is coupled to a second terminal of the interface (Fig. 2 – input of #110),
the first amplifier is configured to generate a current at the second end of the second resistor, based at least on a voltage sensed from the first signal, to supply an additional current to the second signal traversing the second resistor towards the interface (Fig. 2 IOUT2, Par. 18-19, 25), and
the second amplifier is configured to generate a current at the second end of the first resistor, based at least on a voltage sensed from the second signal, to supply an additional current to the first signal traversing the first resistor towards the interface (Fig. 2 IOUT2, Par. 18-19, 25).
Regarding claim 8, Seth teaches the system of claim 7, wherein at least one of the first resistor (Fig. 2 #212a) or the second resistor (Fig. 2 #212b) is set to cause the first amplifier (Fig. 2 #210, Fig. 3 MP1a, MN1a, MN2a, MP2a) and the second amplifier (Fig. 2 #210, Fig. 3 MP1b, MN1b, MN2b, MP2b) to output a particular range of output voltages, based at least on a voltage sensed from at least one of the first signal or the second signal (Fig. 2 whatever output signal #206a and #206b is sent to the first and second resistors will cause the resistors to influence the voltages that are output from the first and second amplifiers; Par. 26).
Regarding claim 9, Seth teaches the system of claim 7, wherein each of the first amplifier and the second amplifier is a transconductance amplifier (Par. 16).
Regarding claim 11, Seth teaches the system of claim 7, wherein each of the first amplifier and the second amplifier comprises a current mirror circuit configured to output a respective current in an output stage (Fig. 3 #222a, and #222b).
Regarding claim 12, Seth teaches the system of claim 7, wherein at least one of the first amplifier or the second amplifier is a class AB amplifier (Fig. 3).
Regarding claim 13, Seth teaches the system of claim 7, wherein
a first end of a third resistor (Fig. 2 #208a) is coupled to a first output terminal (Fig. 2 #206a) of a line driver (Fig. 2 #202),
a first end of a fourth resistor (Fig. 2 #208b) is coupled to a second output terminal (Fig. 2 #206b) of the line driver (Fig. 2 #202),
a second end of the fourth resistor (Fig. 2 #206b) and the output terminal of the first amplifier (Fig. 2 #22a is connected to #208b) are coupled to the interface (fig. 2 #110), and
a second end of the third resistor (Fig. 2 #208a) and the output terminal of the second amplifier (Fig. 2 #22b connected to 208a) are coupled to the interface (Fig. #110).
Regarding claim 15, Seth teaches a system (Fig. 1-3) comprising:
circuitry configured to couple a first end of a first resistor (Fig. 2 #214a) to a first input terminal (Fig. 2 negative inverted - terminal) of a line driver (Fig. 2 #210), and couple a first end of a second resistor (Fig. 2 3214b) to a second input terminal (Fig. 2 positive non-inverted + terminal) of the line driver,
wherein the circuitry is configured to
receive, at a second end of the first resistor, a first signal (Fig. #206a),
receive, at a second end of the second resistor, a second signal (Fig. 2 #206b), and
set at least one of the first resistor or the second resistor to cause the line driver to output a predetermined range of output voltages, based at least on a voltage sensed from at least one of the first signal or the second signal (Fig. 2 whatever output signal #206a and #206b is sent to the first and second resistors will cause the resistors to influence the voltages that are output from the first and second amplifiers; Par. 26).
Regarding claim 16, Seth teaches the system of claim 15, wherein the line driver includes at least one of a class AB line driver or a class B line driver (Fig. 3).
Regarding claim 17, Seth teaches the system of claim 15, wherein
the second end of the first resistor (Fig. 2 #214a) is coupled to a first output terminal (Fig. 2 #206a) of another line driver (Fig. 2 #202), and
the second end of the second resistor (Fig. 2 #214b) is coupled to a second output terminal (Fig. 2 #206b) of the another line driver.
Regarding claim 18, Seth teaches the system of claim 15, wherein
a first end of a third resistor (Fig. 2 #208b) and a first output terminal of the line driver (Fig. 2 #22a coupled to #208b) are coupled to an interface to a physical medium (Fig. 2 #110),
a first end of a fourth resistor (Fig. 2 #208a) and a second output terminal of the line driver (Fig. 2 #22b coupled to #208a) are coupled to the interface (Fig. 2 #110),
a second end of the fourth resistor (Fig. 2 left hand side of #208a) is coupled to the second end of the first resistor (Fig. 2 #214a), and
a second end of the third resistor(Fig. 2 left hand side of #208b) is coupled to the second end of the second resistor (Fig. 2 #214b).
Regarding claim 20, Seth teaches the system of claim 15, wherein the line driver (Fig. 2 #210) is configured to generate a current, based at least on (1) a voltage sensed from at least the first signal or the second signal (Fig. 2 voltage output from #202 is input to #210) and (2) at least one of a resistance of the first resistor or a resistance of the second resistor (Fig. 2 #214a and #214b), to supply an additional current to at least one of the first signal or the second signal (Fig. 2 IOUT2 that is output from #210 and #222a and #222b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20190173429 by Seth et al.
Regarding claim 3, Seth teaches the system of claim 1 as shown above, but does not teach that the first and second amplifiers consist of one or more common-gate transistors in the input and output stages. However, common-gate configurations are known in the art, and implementing them in a circuit has many advantages such as excellent frequency response characteristics and superior high frequency performance (“Common Gate MOSFET Amplifier: A Comprehensive Analysis of High-Performance RF Applications”).
Regarding claim 10, Seth teaches the system of claim 7 as shown above, but does not teach that the first and second amplifiers consist of one or more common-gate transistors in the input and output stages. However, common-gate configurations are known in the art, and implementing them in a circuit has many advantages such as excellent frequency response characteristics and superior high frequency performance (“Common Gate MOSFET Amplifier: A Comprehensive Analysis of High-Performance RF Applications”).
Claim(s) 6, 14, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seth as applied to claims 1, 13, and 18 above, and further in view of US 20240030900 by Rastogi et al.
Regarding claim 6, Seth teaches the system of claim 1, but does not explicitly teach that each of the first resistor and the second resistor is coupled at an end of a respective transmission line coupled to the interface.
However, Rastogi teaches a line driver circuit (Fig. 1a) wherein each of the first resistor (Fig. 1a R3) and the second resistor (Fig. 1a R4) is coupled at an end of a respective transmission line (Fig. 1a #108) coupled to the interface (Fig. 1a #104).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Rastogi with Seth because this coupling of resistors to a transmission line maximizes power transfer to the receiving device (Par. 26 of Rastogi).
Regarding claim 14, Seth teaches the system of claim 13, but does not explicitly teach that each of the third resistor and the fourth resistor are coupled at an end of a respective transmission line coupled to the interface.
However, Rastogi teaches a line driver circuit (Fig. 1a) wherein each of the first resistor (Fig. 1a R3) and the second resistor (Fig. 1a R4) is coupled at an end of a respective transmission line (Fig. 1a #108) coupled to the interface (Fig. 1a #104).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Rastogi with Seth because this coupling of resistors to a transmission line maximizes power transfer to the receiving device (Par. 26 of Rastogi).
Regarding claim 19, Seth teaches the system of claim 18, but does not explicitly teach that each of the third resistor and the fourth resistor are coupled at an end of a respective transmission line coupled to the interface.
However, Rastogi teaches a line driver circuit (Fig. 1a) wherein each of the first resistor (Fig. 1a R3) and the second resistor (Fig. 1a R4) is coupled at an end of a respective transmission line (Fig. 1a #108) coupled to the interface (Fig. 1a #104).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to combine Rastogi with Seth because this coupling of resistors to a transmission line maximizes power transfer to the receiving device (Par. 26 of Rastogi).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NAREH SHAMIRYAN whose telephone number is (703)756-4616. The examiner can normally be reached M-F: 7:00AM-4:00PM PT.
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/NAREH SHAMIRYAN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843