DETAILED ACTION
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) las is/are rejected under 35 U.S.C. 103 as being unpatentable over Hansen et al. (U.S. Pub. No 2016/0032486) in view of Axus (Wafer Edge Grinding Process October 2013).
Hansen et al. teaches crystals were grown and sliced to produce 4H-SiC substrates such that the resulting surface is at an angle of 4 degrees away from the c-axis toward the <11-20> direction which meets the limitation of a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface (paragraph 75). Hansen et al. teaches one application where the epitaxial film deposited is thick (10-100+ µm) using CVD process which meets the limitation of a SiC epitaxial film having a film thickness of 20 µm or more, which is formed on the 4H-SiC single crystal substrate (paragraphs 68 and 69). Hansen et al. teaches wafer diameter was within a specification of 150+/−0.4 mm following the edge chamfer process which meets the limitation of and a bevel part on a peripheral part (paragraph 75). Hansen et al. does not teach wherein the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more.
Axus teaches after the boule is grown to diameter and length, it is rounded and then sliced into substrates that will become wafers (page 2). Axus teaches “The edge grinding step is critical to the safety of the wafer edge. Silicon in this crystalline state is very brittle and if the edge is not profiled or rounded off, it will flake during handling and certainly during follow-on processing steps both mechanical in nature and thermally dynamic in nature. Edge flaking is not only catastrophic for the individual wafer, it can be a disaster for other wafers that are being processed if the edge flake contaminates the processing equipment or nearby wafers.” (page 2). Axus teaches “While other shapes may be used to protect the wafer edge from chipping, what has become generally known as the "bullet nose" shape and variations of this shape are the most common for monocrystalline silicon wafers of all sizes in the semiconductor industry. This shape is common also for polycrystalline applications such as those made in PV (solar) related device manufacturing. The shape of the "nose" may be blunter if the wafers are to be processed farther down the line using the CMP or they may be aerodynamic is the wafers are not going to go through a CMP process.” (page 2). Axus teaches “The SEMI specification for the length of the bevel edge is 200 µm + 50 µm which overlaps with the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more (page 3). It would have been obvious to one of ordinary skill in the art to shape the bevel edge of the SiC wafer substrate taught by Hansen et al. so that the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more because it prevents chipping and flaking.
Regarding claim 3, Hansen et al. teaches one application where the epitaxial film deposited is thick (10-100+ µm) using CVD process which meets the limitation of a SiC epitaxial film having a film thickness of 20 µm or more, which is formed on the 4H-SiC single crystal substrate (paragraphs 68 and 69). Axus teaches “The SEMI specification for the length of the bevel edge is 200 µm + 50 µm which overlaps with the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more (page 3). Hansen et al. in view of Axus overlaps with when Y represents a width ( m) of the slope part and X represents a thickness ( m) of the epitaxial film, Formula shown below is satisfied, Y> 20X-400.
Regarding claims 4-9, Hansen et al. teaches a beveled circumferential edge (e.g., with maximum angle of 22.5+/−0.2 degrees with respect to fabrication surface of the substrate) (paragraph 38).
Regarding claim 10, Hansen et al. teaches edges of the wafer is then chamfered to an angle of 22.5+/−0.1 degrees (paragraph 45).
Regarding claims 11-14, Hansen et al. teaches one application where the epitaxial film deposited is thick (10-100+ µm) using CVD process which meets the limitation of a SiC epitaxial film having a film thickness of 20 µm or more, which is formed on the 4H-SiC single crystal substrate (paragraphs 68 and 69).
Regarding claim 15, Axus teaches “The SEMI specification for the length of the bevel edge is 200 µm + 50 µm which overlaps with the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more (page 3).
Regarding claim 16, Paragraph 16 of Applicant’s specification states “the generation of the threading edge dislocation row and the interface dislocation are closely related”. Hansen et al. teaches a median areal density of threading screw dislocations is in the range from 0/cm2 to 400/cm2 (paragraph 38). Therefore it is the position of the Office Hansen et al. would overlap with to wherein a density of an interface dislocation extending from the outer peripheral edge of the SiC epitaxial layer is 10 lines/cm or less because the threading location is as low as 0.
Regarding claims 17 and 18, the SiC epitaxial wafer is generally obtained by growing 4H SiC epitaxial layer on a SiC single crystal substrate, in which a surface having an off angle from a (0001) plane to <11-20> direction is used as a growth surface, by step flow growth (paragraph 38).
Regarding claim 19, Hansen et al. teaches a step of preparing a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface, and a bevel part in a peripheral part of the substrate, wherein the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part (paragraph 38). Hansen et al. teaches one application where the epitaxial film deposited is thick (10-100+ µm) using CVD process which meets the limitation of a SiC epitaxial film having a film thickness of 20 µm or more, which is formed on the 4H-SiC single crystal substrate (paragraphs 68 and 69). Axus teaches “The SEMI specification for the length of the bevel edge is 200 µm + 50 µm which overlaps with the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more (page 3). Hansen et al. in view of Axus overlaps with when Y represents a width ( m) of the slope part and X represents a thickness ( m) of the epitaxial film, Formula shown below is satisfied, Y> 20X-400.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hansen et al. in view of Axus as applied to claim 1 above, and further in view of Momose et al. (U.S. Pub. No. 2013/0009170).
Regarding claim 2, Hansen et al. teaches crystals were grown and sliced to produce 4H-SiC substrates such that the resulting surface is at an angle of 4 degrees away from the c-axis toward the <11-20> direction which meets the limitation of a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface (paragraph 75). Hansen et al. teaches one application where the epitaxial film deposited is thick (10-100+ µm) using CVD process which meets the limitation of a SiC epitaxial film having a film thickness of 20 µm or more, which is formed on the 4H-SiC single crystal substrate (paragraphs 68 and 69). Hansen et al. teaches wafer diameter was within a specification of 150+/−0.4 mm following the edge chamfer process which meets the limitation of and a bevel part on a peripheral part (paragraph 75). Hansen et al. does not teach wherein the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more.
Axus teaches after the boule is grown to diameter and length, it is rounded and then sliced into substrates that will become wafers (page 2). Axus teaches “The edge grinding step is critical to the safety of the wafer edge. Silicon in this crystalline state is very brittle and if the edge is not profiled or rounded off, it will flake during handling and certainly during follow-on processing steps both mechanical in nature and thermally dynamic in nature. Edge flaking is not only catastrophic for the individual wafer, it can be a disaster for other wafers that are being processed if the edge flake contaminates the processing equipment or nearby wafers.” (page 2). Axus teaches “While other shapes may be used to protect the wafer edge from chipping, what has become generally known as the "bullet nose" shape and variations of this shape are the most common for monocrystalline silicon wafers of all sizes in the semiconductor industry. This shape is common also for polycrystalline applications such as those made in PV (solar) related device manufacturing. The shape of the "nose" may be blunter if the wafers are to be processed farther down the line using the CMP or they may be aerodynamic is the wafers are not going to go through a CMP process.” (page 2). Axus teaches “The SEMI specification for the length of the bevel edge is 200 µm + 50 µm which overlaps with the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more (page 3). It would have been obvious to one of ordinary skill in the art to shape the bevel edge of the SiC wafer substrate taught by Hansen et al. so that the bevel part includes a slope part continuous from the main surface and an outer peripheral edge part, and a width of the slope part is 150 µm or more because it prevents chipping and flaking.
Hansen et al. in view of Axus does not teach the SiC epitaxial wafer according to wherein the SiC epitaxial film is formed on the main surface and the bevel part of the substrate.
Momose et al. teaches SiC epitaxial film composed of 4H-SiC is formed on top of the main surface of a SiC single crystal wafer composed of 4H-SiC which meets the limitation of a 4H-SiC single crystal substrate (paragraph 117). Momose et al. teaches epitaxial SiC single crystal substrate which includes a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees which meets the limitation of a 4H-SiC single crystal substrate which has a surface with an off angle with respect to a c-plane as a main surface (paragraph 14). Momose et al. teaches method of manufacture of epitaxial SiC single crystal substrate, which includes a SiC single crystal wafer and a SiC epitaxial film formed on the main surface of a SiC single crystal wafer by epitaxial growth (paragraph 27). Momose et al. teaches the SiC epitaxial wafer according to wherein the SiC epitaxial film is formed on the main surface and the bevel part of the substrate (Figure 3). Momose et al. teaches explains the generating mechanism of threading edge dislocation arrays (Figures 6-10). Momose et al. teaches “If dislocation array density is 10 arrays/cm2 or less, it is possible to mitigate device degradation in the case where a device is formed on the epitaxial SiC single crystal substrate” (paragraph 71). It would have been obvious to one of ordinary skill in the art at the time of filing to form the epitaxial fil film such that the SiC epitaxial film is formed on the main surface and the bevel part of the substrate because it minimizes the dislocation array density and therefore mitigate device degradation in the case where a device is formed on the epitaxial SiC single crystal substrate.
Conclusion
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/GUINEVER S GREGORIO/Primary Examiner, Art Unit 1732 03/23/2026