DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/8/2026 has been entered.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Specification/Drawings
The amendment filed 9/8/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the manner in which the well layer WL and barrier layer BL are now depicted in new figures 3 and 4 was not previously described with a specificity commensurate with the new visual disclosure.
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
In view of Applicant’s amendments, some of the prior drawing objections are withdrawn.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the second area does not overlap the cover layer in a thickness direction of the base layer” as found in claims 1 and 21; an entirety of an upper surface of the P-type semiconductor layer not covered by the cover layer as found in claim 22; and the cover layer directly covering only the sides surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer as found in claim 23, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
In view of Applicant’s amendments, the prior claim objections are withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4-8, and 21-23 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
For claims 1 and 21, as the thickness direction as found in the limitation “the second area does not overlap the cover layer in a thickness direction of the base layer” is not well defined, there are many ways in which the second area is shown to overlap the cover layer in the thickness direction, and so this limitation introduces new matter. For example, if the thickness direction of the base layer is taken to be perpendicular to D3 as shown in Fig. 5, the second area is entirely covered by the cover layer in the thickness direction of the base layer. Furthermore, any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
Claims 2 and 4-8 inherit this rejection for new matter.
For claim 22, as the cover layer is shown to cover an entirety of an upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “the cover layer does not cover an entirety of an upper surface of the P-type semiconductor layer” introduces new matter; an observer on either side of the device shown in Fig. 5, looking in a direction that is perpendicular to DR3, would find that the cover layer entirely covers all portions of the P-type semiconductor layer, contrary to what is claimed. Or, alternatively, with an “upper” direction perpendicular to DR3 as shown in Fig. 3, an upper surface could be the right side surface of the P-type semiconductor layer, which results in Fig. 5 showing the cover layer covering the entirety of the upper surface of the P-type semiconductor layer.
Furthermore, as a thickness direction of “does not overlap with the P-type semiconductor layer in a thickness direction of the base layer” is not well defined, there are many ways in which the cover layer is shown to overlap the P-type semiconductor in a thickness direction, and so this limitation introduces new matter. For example, if the thickness direction of the base layer is taken to be perpendicular to D3 as shown in Fig. 5, the P-type semiconductor layer is entirely covered by the cover layer in the thickness direction of the base layer.
Also any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
Claim 23 inherits this rejection for new matter.
For claim 23, as the cover layer is shown to cover an entirety of the upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer” introduces new matter; an observer on either side of the device shown in Fig. 5, looking in a direction that is perpendicular to DR3, would find that the cover layer entirely covers all portions of the P-type semiconductor layer, contrary to what is claimed. Or, alternatively, with an “upper” direction perpendicular to DR3 as shown in Fig. 3, an upper surface could be the right side surface of the P-type semiconductor layer, which results in Fig. 5 showing the cover layer covering the entirety of the upper surface of the P-type semiconductor layer.
Also, any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
In view of Applicant’s arguments, some of the prior 112(b) rejections are withdrawn, with the others maintained.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 4-8, and 21-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 1) As “the second area does not overlap the cover layer in a thickness direction of the base layer” was neither originally shown nor described, the relationship between parts required by the claim is unclear. Furthermore, as discussed above, this limitation has multiple interpretations making the metes and bounds unclear.
During examination, this was read as requiring only that the cover layer may have an opening overlapping with the second area.
Claims 2 and 4-8 inherit these rejections for indefiniteness.
(Re Claim 21) As “the second area does not overlap the cover layer in a thickness direction of the base layer” was neither originally shown nor described, the relationship between parts required by the claim is unclear. Furthermore, as discussed above, this limitation has multiple interpretations making the metes and bounds unclear.
During examination, this was read as requiring only that the cover layer may have an opening overlapping with the second area.
(Re Claim 22) As “the cover layer does not cover an entirety of an upper surface of the P-type semiconductor layer, does not overlap with the P-type semiconductor layer in a thickness direction of the base layer,” was neither originally shown nor described, the relationship between parts required by the claim is unclear.
During examination, this was read as requiring only that the cover layer may have an opening exposing the upper surface of the P-type semiconductor layer.
Furthermore, reciting “an entirety of an upper surface” renders the extent of the entirety referred to unclear. The recited “an entirety” allows for the possibility of other entireties of an upper surface, e.g. “an entirety” may still apply to an entire portion of the surface, less than the entire area. The intended portion of the “an entirety” of the upper surface is not clear. Also, since the claim establishes no directions or frame of reference “an upper surface” is not well defined and may be arbitrarily ascribed to any surface.
During examination, “an entirety of an upper surface of the P-type semiconductor layer” was understood to refer to a portion of an upper surface of the P-type semiconductor layer.
Claim 23 inherits these rejections for indefiniteness.
(Re Claim 23) As “the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer” was neither originally shown nor described, the relationship between parts required by the claim is unclear.
During examination, this was read as requiring only that the cover layer may have an opening exposing the upper surface of the P-type semiconductor layer.
Rejection 1/3
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (US 2020/0328327) of record.
(Re Claim 1) He teaches a display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer (Fig. 6C); and
a cover layer (620; Fig. 6C) disposed between the light emitting elements adjacent to each other;
wherein the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D);
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element emitting light (520b; Fig. 6C) of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C),
the N-type semiconductor layer includes a first area (between the thicker dashed lines in the U-shaped opening in 620; Fig. 6C markup) and a second area (Fig. 6C markup),
the first area overlaps the cover layer in a thickness direction (top to bottom; Fig. 6C) of the base layer,
the second area does not overlap the cover layer in the thickness direction of the base layer (Fig. 6C),
the active layer and the p-type semiconductor layer are disposed in the second area (Fig. 6C), and
the cover layer has a uniform thickness along the thickness direction in the first area (Fig. 6C).
PNG
media_image1.png
681
1037
media_image1.png
Greyscale
PNG
media_image2.png
692
1039
media_image2.png
Greyscale
(Re Claim 2) He teaches the display device of claim 1, wherein the first light emitting element and the second light emitting element include a same N-type semiconductor layer (both include 505; ¶57).
(Re Claim 4) He teaches the display device of claim 3, wherein a portion (under the middle active layer 530) of the N-type semiconductor layer disposed in the second area does not overlap the cover layer in a thickness direction (Fig. 6D and the Fig. 6C markup).
(Re Claim 21) He teaches the electronic device comprising a display device, the display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer; and
a cover layer disposed between the light emitting elements adjacent to each other,
wherein the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D),
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer (boxed area on the left beneath the corresponding active area; Fig. 6C markup) of the first light emitting element and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C),
the N-type semiconductor layer includes a first area (between the thicker dashed lines in the U-shaped opening in 620; Fig. 6C markup) and a second area (Fig. 6C markup),
the first area overlaps the cover layer in a thickness direction (top to bottom; Fig. 6C) of the base layer,
the second area does not overlap the cover layer in the thickness direction of the base layer (Fig. 6C),
the active layer and the p-type semiconductor layer are disposed in the second area (Fig. 6C), and
the cover layer has a uniform thickness along the thickness direction in the first area (Fig. 6C).
PNG
media_image2.png
692
1039
media_image2.png
Greyscale
PNG
media_image1.png
681
1037
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5 and 7 rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Su et al. (US 2012/0235116) of record.
(Re Claim 5) He teaches the display device of claim 1, wherein the first active layer and the second active layer are formed on the plane surface formed by the first N-type semiconductor layer and the second N-type semiconductor layer.
He has not been shown to explicitly teach the display device wherein the active layer includes a barrier layer and a well layer and the N-type semiconductor layer is in contact with the active layer to be adjacent to the barrier layer.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Modified He then teaches the active layer includes a barrier layer (Su: 272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), and the N-type semiconductor layer (He: 505) is in contact with the active layer to be adjacent to the barrier layer (compare the location of Su’s 206 with He’s 505).
(Re Claim 7) He teaches the display device of claim 1, wherein the N-type semiconductor layer includes GaN (¶77) doped with a first conductivity type dopant (n-type dopant; ¶57), and the P-type semiconductor layer includes GaN (¶77) doped with a second conductivity type dopant (p-type dopant; ¶60).
He has not been shown to explicitly teach the display device wherein the active layer includes a well layer including InGaN and a barrier layer including GaN.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Furthermore, Su teaches forming quantum wells using InGaN and barrier layers using GaN (¶¶46, 51).
A PHOSITA would find it obvious to utilize InGaN to form the quantum wells, and GaN to form the barrier layers, of modified He, as Su teaches these are suitable materials to respectively form the quantum wells and barrier layers from. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Hasegawa et al. (US 2016/0372631) of record.
(Re Claim 6) He teaches the display device of claim 1, wherein the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially disposed in a stacked direction (stacked direction is from bottom to top; Fig. 6C), the N-type semiconductor layer includes a dopant (n-type; ¶57).
He has not been shown to explicitly teach that the dopant is a silicon dopant.
Hasegawa teaches that GaN is n-type doped using silicon dopant (¶42).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize silicon dopant to dope the GaN of the N-type semiconductor layer, as this is a known n-type dopant for GaN.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) and Su et al. (US 2012/0235116) both of record as applied to claim 7 above, and further in view of Hu (US 2013/0214247) of record.
(Re Claim 8) Modified He teaches the display device of claim 7, but has not been shown to explicitly teach the display device wherein the light emitting elements further include: a superlattice layer disposed between the active layer and the N-type semiconductor layer, and an electron blocking layer disposed between the active layer and the P-type semiconductor layer.
Su teaches forming an electron blocking layer (EBL; Fig. 2F) between the active layer (208; Fig. 2F) and a P-type semiconductor layer (212; Fig. 2F, ¶49).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to incorporate the electron blocking layer of Su between the active layer and the P-type semiconductor layer of modified He, as electron blocking layers help confine radiative recombination within the active layer (Su: ¶48).
Hu teaches forming a superlattice layer between an active layer (145; Fig. 3) and an N-type semiconductor layer (140; Fig. 3).
A PHOSITA would find it obvious to form a superlattice layer between the active layer and the N-type semiconductor layer of modified He, in order to release stresses within the layers and improve internal quantum efficiency of the light emitting elements (Hu: ¶11).
Modified He then teaches that the light emitting elements further include:
a superlattice layer (Hu: 145; Fig. 3) disposed between the active layer (Su: 208; Fig. 2F) and the N-type semiconductor layer (He: 505; Fig. 6C), and
an electron blocking layer (Su: EBL; Fig. 2F) disposed between the active layer (Su: 208; Fig. 2F) and the P-type semiconductor layer (He: 540; Fig. 6C).
Rejection 2/3, using a wider first area region encompassing all of the cover layer disposed between the light emitting elements.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by He et al. (US 2020/0328327) of record.
(Re Claim 1) He teaches a display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer (Fig. 6C); and
a cover layer (the part of 620 that is between the light emitting elements as shown in the Fig. 6C markup within the first area) disposed between the light emitting elements adjacent to each other;
wherein the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D);
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element emitting light (520b; Fig. 6C) of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C),
the N-type semiconductor layer includes a first area (between the thicker dashed lines; Fig. 6C markup) and a second area (Fig. 6C markup),
the first area overlaps the cover layer in a thickness direction (top to bottom; Fig. 6C) of the base layer,
the second area does not overlap the cover layer in the thickness direction of the base layer (Fig. 6C),
the active layer and the p-type semiconductor layer are disposed in the second area (Fig. 6C), and
the cover layer has a uniform thickness along the thickness direction in the first area (in the U-shaped part of 620 within each first area; Fig. 6C).
PNG
media_image1.png
681
1037
media_image1.png
Greyscale
PNG
media_image3.png
692
1039
media_image3.png
Greyscale
(Re Claim 2) He teaches the display device of claim 1, wherein the first light emitting element and the second light emitting element include a same N-type semiconductor layer (both include 505; ¶57).
(Re Claim 4) He teaches the display device of claim 3, wherein a portion (under the middle active layer 530) of the N-type semiconductor layer disposed in the second area does not overlap the cover layer in a thickness direction (Fig. 6D and the Fig. 6C markup).
(Re Claim 21) He teaches the electronic device comprising a display device, the display device comprising: a base layer (310; Fig. 6D); and light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer; and
a cover layer disposed between the light emitting elements adjacent to each other,
wherein the active layer is between the base layer and the N-type semiconductor layer (Fig. 6D),
the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer (boxed area on the left beneath the corresponding active area; Fig. 6C markup) of the first light emitting element and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer (left 530; Fig. 6C) of the first light emitting element and a second active layer (middle 530; Fig. 6C) of the second light emitting element, and
the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C),
the N-type semiconductor layer includes a first area (between the thicker dashed lines in the U-shaped opening in 620; Fig. 6C markup) and a second area (Fig. 6C markup),
the first area overlaps the cover layer in a thickness direction (top to bottom; Fig. 6C) of the base layer,
the second area does not overlap the cover layer in the thickness direction of the base layer (Fig. 6C),
the active layer and the p-type semiconductor layer are disposed in the second area (Fig. 6C), and
the cover layer has a uniform thickness along the thickness direction in the first area (in the U-shaped part of 620 within each first area; Fig. 6C).
PNG
media_image3.png
692
1039
media_image3.png
Greyscale
PNG
media_image1.png
681
1037
media_image1.png
Greyscale
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 5 and 7 rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Su et al. (US 2012/0235116) of record.
(Re Claim 5) He teaches the display device of claim 1, wherein the first active layer and the second active layer are formed on the plane surface formed by the first N-type semiconductor layer and the second N-type semiconductor layer.
He has not been shown to explicitly teach the display device wherein the active layer includes a barrier layer and a well layer and the N-type semiconductor layer is in contact with the active layer to be adjacent to the barrier layer.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Modified He then teaches the active layer includes a barrier layer (Su: 272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), and the N-type semiconductor layer (He: 505) is in contact with the active layer to be adjacent to the barrier layer (compare the location of Su’s 206 with He’s 505).
(Re Claim 7) He teaches the display device of claim 1, wherein the N-type semiconductor layer includes GaN (¶77) doped with a first conductivity type dopant (n-type dopant; ¶57), and the P-type semiconductor layer includes GaN (¶77) doped with a second conductivity type dopant (p-type dopant; ¶60).
He has not been shown to explicitly teach the display device wherein the active layer includes a well layer including InGaN and a barrier layer including GaN.
He teaches that the active layer may include at least one quantum well (He: ¶65).
Su teaches forming an active layer (208; Fig. 2F) including a barrier layer (272; Fig. 2F) and a well layer (quantum well contacting 272; Fig. 2F), such that an N-type semiconductor layer (206; Fig. 2F) is in contact with the active layer to be adjacent to the barrier layer.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form each light emitting element stack of He, such that the active layer of He contacts the N-type semiconductor layer utilized for contact – He’s N-type semiconductor 505 (note contact metal location in Fig. 6C) – as taught by Su, as the active layer configuration taught by Su provides improved quantum efficiency (Su: ¶43).
Furthermore, Su teaches forming quantum wells using InGaN and barrier layers using GaN (¶¶46, 51).
A PHOSITA would find it obvious to utilize InGaN to form the quantum wells, and GaN to form the barrier layers, of modified He, as Su teaches these are suitable materials to respectively form the quantum wells and barrier layers from. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See also In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) of record as applied to claim 1 above, and further in view of Hasegawa et al. (US 2016/0372631) of record.
(Re Claim 6) He teaches the display device of claim 1, wherein the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially disposed in a stacked direction (stacked direction is from bottom to top; Fig. 6C), the N-type semiconductor layer includes a dopant (n-type; ¶57).
He has not been shown to explicitly teach that the dopant is a silicon dopant.
Hasegawa teaches that GaN is n-type doped using silicon dopant (¶42).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize silicon dopant to dope the GaN of the N-type semiconductor layer, as this is a known n-type dopant for GaN.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) and Su et al. (US 2012/0235116) both of record as applied to claim 7 above, and further in view of Hu (US 2013/0214247) of record.
(Re Claim 8) Modified He teaches the display device of claim 7, but has not been shown to explicitly teach the display device wherein the light emitting elements further include: a superlattice layer disposed between the active layer and the N-type semiconductor layer, and an electron blocking layer disposed between the active layer and the P-type semiconductor layer.
Su teaches forming an electron blocking layer (EBL; Fig. 2F) between the active layer (208; Fig. 2F) and a P-type semiconductor layer (212; Fig. 2F, ¶49).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to incorporate the electron blocking layer of Su between the active layer and the P-type semiconductor layer of modified He, as electron blocking layers help confine radiative recombination within the active layer (Su: ¶48).
Hu teaches forming a superlattice layer between an active layer (145; Fig. 3) and an N-type semiconductor layer (140; Fig. 3).
A PHOSITA would find it obvious to form a superlattice layer between the active layer and the N-type semiconductor layer of modified He, in order to release stresses within the layers and improve internal quantum efficiency of the light emitting elements (Hu: ¶11).
Modified He then teaches that the light emitting elements further include:
a superlattice layer (Hu: 145; Fig. 3) disposed between the active layer (Su: 208; Fig. 2F) and the N-type semiconductor layer (He: 505; Fig. 6C), and
an electron blocking layer (Su: EBL; Fig. 2F) disposed between the active layer (Su: 208; Fig. 2F) and the P-type semiconductor layer (He: 540; Fig. 6C).
Rejection 3/3
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over He et al. (US 2020/0328327) and Wang (US 2021/0335884), both of record.
(Re Claim 22) He teaches an electronic device (110; Fig. 9B) comprising a display device (910; Fig. 9B), the display device comprising: a base layer (310; Fig. 6D); light emitting elements (520d+520e+520f; Fig. 6C) disposed on the base layer, the light emitting elements including an N-type semiconductor layer (505; Fig. 6C, ¶57), a P-type semiconductor layer (540; Fig. 6C, ¶60), and an active layer (530; Fig. 6C, ¶65) disposed between the N-type semiconductor layer and the P-type semiconductor layer (Fig. 6C); and wherein the light emitting elements include a first light emitting element (520a; Fig. 6C) emitting light of a first color (¶59) and a second light emitting element (520b; Fig. 6C) emitting light of a second color (¶59),
the N-type semiconductor layer includes a first N-type semiconductor layer of the first light emitting element (boxed area on the left beneath the corresponding active area; Fig. 6C markup) and a second N-type semiconductor layer of the second light emitting element (boxed area in the middle beneath the corresponding active area; Fig. 6C markup),
the active layer includes a first active layer of the first light emitting element (left 530; Fig. 6C) and a second active layer (middle 530; Fig. 6C) of the second light emitting element, the first N-type semiconductor layer and the second N-type semiconductor layer are integral with each other, and form a plane surface in an area where the active layer is disposed (Fig. 6C).
He has not been explicitly shown to teach the electronic device comprising a display device, the display device comprising:
a cover layer disposed between the light emitting elements adjacent to each other, and the cover layer does not cover an entirety of upper surface of the P-type semiconductor layer, and covers side surfaces of the P-type semiconductor layer.
He teaches utilizing a cover layer (the dielectric layer of ¶58) to define the placement of the light emitting elements during their growth.
Wang teaches forming separated light emitting elements (108+100; Fig. 1c) within openings in a cover layer (104; Fig. 1c).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the light emitting elements of He using a cover layer as taught by Wang, for the cover layer taught by He (the dielectric layer of ¶58), as such a cover layer provides an increased growth rate (Wang: ¶44).
Wang’s cover layer is placed on a top surface of a common n-type layer 100 (Wang: ¶37), which corresponds to a top surface of the substrate 510 of He, which is the top surface of the layer 505 (He: “The substrate 510 may be part of a device and may be the same or similar to the one shown in the diagram 500a in FIG. 5A, and may include the bottom layer 503 and the one or more buffer or initiation layers 505”; ¶63), and so Wang’s cover layer 104 would be similarly positioned. This means He’s layers that form the light emitting elements located above He’s layer 505 are grown within Wang’s cover layer 104.
A PHOSITA would then find it obvious to omit forming the passivation layer 620 of He, as Wang’s cover layer 104 provides a barrier between atmosphere and the active layer. This omission also reduces the overall process steps when forming the light emitting elements using a cover layer like Wang’s.
This results in modified He teaching a cover layer (Wang: 104) disposed between the light emitting elements adjacent to each other (Wang: Fig. 1c), and the cover layer does not cover an entirety of an upper surface (topmost as seen in Wang’s Fig. 1c) of the P-type semiconductor material (the P-type semiconductor material 114 of Wang is uncovered), does not overlap with the P-type semiconductor layer in a thickness direction (top to bottom direction, due to how Wang’s cover layer surrounds each light emitting element; see Wang’s Fig. 1c) of the base layer, and directly covers side surfaces (left and right) of the P-type semiconductor layer (due to Wang’s cover layer surrounding each light emitting element; see Wang’s Fig. 1c).
PNG
media_image1.png
681
1037
media_image1.png
Greyscale
(Re Claim 23) Modified He teaches the electronic device of claim 22, wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer (Wang: Fig. 1c).
Response to Arguments
Applicant's arguments filed 9/8/2026 have been fully considered but they are not persuasive.
With respect to the drawing objections concerning claims 22-23, Applicant’s figures do not show the negative claim limitations.
For claim 22, as the cover layer is shown to cover an entirety of an upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “the cover layer does not cover an entirety of an upper surface of the P-type semiconductor layer” introduces new matter; an observer on either side of the device shown in Fig. 5, looking in a direction that is perpendicular to DR3, would find that the cover layer entirely covers all portions of the P-type semiconductor layer, contrary to what is claimed. Or, alternatively, with an “upper” direction perpendicular to DR3 as shown in Fig. 3, an upper surface could be the right side surface of the P-type semiconductor layer, which results in Fig. 5 showing the cover layer covering the entirety of the upper surface of the P-type semiconductor layer. Nothing in the claim requires a particular direction along which the cover layer is perceived not to cover an entirety of an upper surface of the P-type semiconductor layer and myriad ways in which to see the cover layer covering an entirety of an upper surface of the P-type semiconductor layer exist.
Furthermore, as a thickness direction of “does not overlap with the P-type semiconductor layer in a thickness direction of the base layer” is not well defined, there are many ways in which the cover layer is shown to overlap the P-type semiconductor in a thickness direction, and so this limitation introduces new matter. For example, if the thickness direction of the base layer is taken to be perpendicular to D3 as shown in Fig. 5, the P-type semiconductor layer is entirely covered by the cover layer in the thickness direction of the base layer. Nothing in the claim requires the thickness direction to be any particular direction, defined according to e.g., the stacked direction of elements, a direction perpendicular to some surface, a direction defined by the gap between two separated elements, etc.
For claim 23, as the cover layer is shown to cover an entirety of the upper surface of the P-type semiconductor layer in the drawings, at least in a left-to-right direction as seen in e.g., Fig. 5, reciting “wherein the cover layer directly covers only the side surfaces of the P-type semiconductor layer without covering the upper surface of the P-type semiconductor layer” introduces new matter; an observer on either side of the device shown in Fig. 5, looking in a direction that is perpendicular to DR3, would find that the cover layer entirely covers all portions of the P-type semiconductor layer, contrary to what is claimed. Or, alternatively, with an “upper” direction perpendicular to DR3 as shown in Fig. 3, an upper surface could be the right side surface of the P-type semiconductor layer, which results in Fig. 5 showing the cover layer covering the entirety of the upper surface of the P-type semiconductor layer.
Also, any claim containing a negative limitation which does not have basis in the original disclosure should be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, as failing to comply with the written description requirement.
With respect to whether He’s Fig. 6C discloses that “the cover layer has a uniform thickness along the thickness direction in the first area”, though Applicant argues that He’s thickness varies, the claim language cited does not preclude variation somewhere in the cover layer. All that the language requires is that, across some finite interval, the cover layer has a uniform thickness along the thickness direction in the first area. Nothing in the claim defines the particular extent of the uniformity, only that it must occur within the first area. Furthermore, claim 1 and 21 recite “a cover layer disposed between the light emitting elements adjacent to each other”, allowing for just the portion of He’s 620 that is between the light emitting elements adjacent to each other to be the cover layer as claimed. See the second rejection.
For the rejection of claim 22, He in view of Wang demonstrates a cover layer that does not overlap the P-type semiconductor and that directly covers the side surfaces of the P-type semiconductor layer. See Wang’s Fig. 1c and accompanying argument made in the rejection.
The remainder of Applicant’s arguments are moot.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
