Prosecution Insights
Last updated: April 19, 2026
Application No. 18/310,073

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102§103§112
Filed
May 01, 2023
Examiner
VLCEK, JACOB ALEXANDER
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
0%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
1 granted / 1 resolved
+32.0% vs TC avg
Minimal -100% lift
Without
With
+-100.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
11 currently pending
Career history
12
Total Applications
across all art units

Statute-Specific Performance

§103
56.5%
+16.5% vs TC avg
§102
30.4%
-9.6% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 4 is objected to because of the following informalities: "the at least" in the second paragraph is a grammatical error. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 1, the phrase “key pattern” renders the claim indefinite because the claim includes elements not actually disclosed (those encompassed by “key pattern”), thereby rendering the scope of the claim unascertainable. It should be noted that “key pattern” is the generic term for an interlocking geometric motif formed by straight lines or bars that intersect to form rectilinear spiral shapes. It simply is a resemblance of the L-shaped or T-shaped slots in an ordinary key. The scope of the claim is unclear, and therefore the term is indefinite. For examination purposes, the phrase “key pattern” has been construed to cover any kind of geometric pattern. Regarding claims 2-13, they are dependent on claim 1 and thus rejected because they inherit the issue with the phrase “key pattern” and are indefinite. Regarding claim 14, the phrase “key pattern” renders the claim indefinite because the claim includes elements not actually disclosed (those encompassed by “key pattern”), thereby rendering the scope of the claim unascertainable. It should be noted that “key pattern” is the generic term for an interlocking geometric motif formed by straight lines or bars that intersect to form rectilinear spiral shapes. It simply is a resemblance of the L-shaped or T-shaped slots in an ordinary key. The scope of the claim is unclear, and therefore the term is indefinite. For examination purposes, the phrase “key pattern” has been construed to cover any kind of geometric pattern. Regarding claims 15-18, they are dependent on claim 14 and thus rejected because they inherit the issue with the phrase “key pattern” and are indefinite. Regarding claim 19, the phrase “key pattern” renders the claim indefinite because the claim includes elements not actually disclosed (those encompassed by “key pattern”), thereby rendering the scope of the claim unascertainable. It should be noted that “key pattern” is the generic term for an interlocking geometric motif formed by straight lines or bars that intersect to form rectilinear spiral shapes. It simply is a resemblance of the L-shaped or T-shaped slots in an ordinary key. The scope of the claim is unclear, and therefore the term is indefinite. For examination purposes, the phrase “key pattern” has been construed to cover any kind of geometric pattern. Regarding claim 20, it is dependent on claim 19 and thus rejected because they inherit the issue with the phrase “key pattern” and are indefinite. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 7-9, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 20170345679 A1). Regarding claim 1, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 1, FIG. 2A, and FIG. 3A OF Kwon et al. teach a semiconductor device (FIG. 1, paragraph 0021), comprising: a substrate (1; FIG. 3A; paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region; and at least one coarse key pattern (KP; FIG. 2A; paragraph 0023) at least partly divided into fine key patterns (DP; FIG. 3A; paragraph 0034) on the edge region (SL; FIG. 1; paragraph 0022), extending in a first direction (FIG. 3A) and spaced apart from each other in a second direction (FIG. 3A) that crosses the first direction, wherein each of the fine key patterns comprise: a first key pattern (MP3; FIG. 3A; paragraph 0034) extending in the first direction; and a second key pattern (NP3; FIG. 3A; paragraph 0034) comprising a first portion (NP3; FIG. 3A; paragraph 0034) extending along a side surface of the first key pattern, and a second portion (NP3; FIG. 3A; paragraph 0034) extending along an opposite side surface of the first key pattern, wherein each of the first and second portions have widths (NP3, W3; FIG. 3A; paragraph 0035) that are less than a width of the first key pattern (MP3, W2; FIG. 3A; paragraph 0035), when measured in the second direction. Regarding claim 2, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 1, wherein the first portion (NP3; FIG. 3A; paragraph 0034), the first key pattern (MP3; FIG. 3A; paragraph 0034), and the second portion (NP3; FIG. 3A; paragraph 0034) are sequentially arranged in the second direction. Regarding claim 3, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 1, wherein the width of the first portion (NP3, W3; FIG. 3A; paragraph 0035) is substantially equal to the width of the second portion (NP3, W3; FIG. 3A; paragraph 0035). Regarding claim 4, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 2A of Kwon teaches the semiconductor device of claim 1, wherein the at least one coarse key pattern (KP; FIG. 2A; paragraph 0023) comprises a first coarse key pattern (KP; FIG. 2A; paragraph 0023) extending in the first direction, and a second coarse key pattern (KP; FIG. 2A; paragraph 0023) extending in the second direction, and each of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the first coarse key pattern (KP; FIG. 2A; paragraph 0023) is elongated in the first direction to have a length that is larger than each of the fine key patterns of the second coarse key pattern (KP; FIG. 2A; paragraph 0023). Regarding claim 5, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 2A of Kwon et al. teaches the semiconductor device of claim 4, wherein a number of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the first coarse key pattern (KP; FIG. 2A; paragraph 0023) is less than a number of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the second coarse key pattern (KP; FIG. 2A; paragraph 0023). Regarding claim 7, as best understood based on the 35 U.S.C. 112(b) issue identified above, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 2A and FIG. 3A of Kwon et al. teach the semiconductor device of claim 1, wherein the at least one coarse key patterns (KP; FIG. 2A; paragraph 0023) further comprises inner patterns (ST; FIG. 3A; paragraph 0028) between the fine key patterns (DP; FIG. 3A; paragraph 0034) which are adjacent to each other in the second direction. Regarding claim 8, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 7, wherein the fine key patterns (BP; FIG. 3A; paragraph 0034) and the inner patterns (ST; FIG. 3A; paragraph 0028) are alternately arranged in the second direction. Regarding claim 9, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 7, wherein the first portions (NP3; FIG. 3A; paragraph 0034), the first key patterns, the second portions (NP3; FIG. 3A; paragraph 0034), and the inner patterns (ST; FIG. 3A; paragraph 0028) are alternately arranged in the second direction. Regarding claim 14, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 1, FIG. 2A, FIG. 3A, and FIG. 3B of Kwon et al. teach a semiconductor device, comprising: a substrate (1; FIG. 3A; Paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region; word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030) on the chip region (CH; FIG. 1; paragraph 0022), extending in a first direction, and spaced apart from each other in a second direction crossing the first direction; and fine key patterns (DP; FIG. 3A; paragraph 0034) extending in the first direction on the edge region (SL; FIG. 1; paragraph 0022) and spaced apart from each other in the second direction (as shown in FIG. 2A, the patterns can occur in both perpendicular directions), wherein the fine key patterns (DP; FIG. 3A; paragraph 0034) comprise the same material (1; FIG. 3A; paragraph 0026) as at least a portion of the word lines (CI, CP; FIG. 3B; paragraph 0023; paragraph 0030), and a first pitch of each of the fine key patterns (DP; FIG. 3A; paragraph 0034) (counting the fine key pattern as the whole set) is larger than a second pitch of four adjacent ones of the word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030), when measured in the second direction. Regarding claim 19, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 1, FIG. 3A, and FIG. 3B of Kwon et al. teach a semiconductor device, comprising: a substrate (1; FIG. 3A; paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030) extended in a first direction on the chip region (CH; FIG. 1; paragraph 0022) and spaced apart from each other in a second direction crossing the first direction; and fine key patterns (DP; FIG. 3A; paragraph 0034) extended in the first direction on the edge region and spaced apart from each other in the second direction, wherein each of the fine key patterns comprises a first key pattern (MP3; FIG. 3A; paragraph 0034) extending in the first direction, and a second key pattern (NP3; FIG. 3A; paragraph 0034) extending along opposite side surfaces of the first key pattern, and a width of the first key pattern (MP3; W2; FIG. 3A; paragraph 0035) is larger than a distance between adjacent ones of the word lines (GE; FIG. 3A; paragraph 0030), when measured in the second direction. Regarding claim 20, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 19, wherein the second key pattern (NP3; FIG. 3A; paragraph 0034) comprises a first portion (NP3; FIG. 3A; paragraph 0034) covering a side surface of the first key pattern (MP3; FIG. 3A; paragraph 0034) and a second portion (NP3; FIG. 3A; paragraph 0034) covering an opposite surface of the first key pattern (MP3; FIG. 3A; paragraph 0034), and the width of the first key pattern (MP3, W2; FIG. 3A; paragraph 0035) is larger than widths of the first and second portions (NP3, W3; FIG. 3A; paragraph 0035), when measured in the second direction. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon in view of Nigam et al. (US 20200176255 A1). Regarding claim 6, Kwon et al. teaches the semiconductor device of claim 1. Kwon et al. does not teach a first pitch of each of the fine key patterns in the second direction ranges from 80 nm to 150 nm. FIG. 4 of Nigam et al. teaches the pitch (P1; FIG. 4; paragraph 0033) between two sets of patterns of lines (110; FIG. 4; paragraph 0033) may range from about 40 nm to about 400 nm (paragraph 0033). Kwon et al. and Nigam et al. are both considered analogous to the claimed invention because they are within the same field of semiconductors with patterns. Therefore, it would have been obvious to someone with ordinary skill in the art before the effective filing date to make the first pitch of each of the fine key patterns in the second direction ranges from 80 nm to 150 nm. Creating such a small pitch would be through pitch multiplication, which would extend the capabilities of the photolithography technique beyond its minimum pitch to form sublithographic features having a pitch of less than about 100 nm (paragraph 0009). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 20190101835 A1) concerns an error measurement structure with pattern structures similar to those in the claimed invention. Ha et al. (US 20140054793 A1) concerns a COF substrate that includes geometric conductive patterns. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.A.V./ Examiner, Art Unit 2817 /RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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Prosecution Timeline

May 01, 2023
Application Filed
Dec 12, 2025
Non-Final Rejection — §102, §103, §112
Feb 10, 2026
Applicant Interview (Telephonic)
Feb 11, 2026
Examiner Interview Summary

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Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
0%
With Interview (-100.0%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 1 resolved cases by this examiner. Grant probability derived from career allow rate.

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