Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The examiner acknowledges receipt on April 9th, 2026 of the following amendments in response to the previous office action (the non-final rejection dated January 11th, 2026):
The line “the at least one coarse key pattern being a process-monitoring pattern” has been added to claim 1, as well as clarification that the first and second portions are adjacent to the first fine key pattern. This was done with the purpose of overcoming the 102 and 112(b) rejection of claim 1.
The line “the at least one coarse key pattern being a process-monitoring pattern” has been added to claim 14. This was done with the purpose of overcoming the 112(b) rejection of claim 14.
The line “the at least one coarse key pattern being a process-monitoring pattern” has been added to claim 19. This was done with the purpose of overcoming the 112(b) rejection of claim 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14, 19, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 20170345679 A1).
Regarding claim 14, FIG. 1, FIG. 2A, FIG. 3A, and FIG. 3B of Kwon et al. teach a semiconductor device, comprising:
a substrate (1; FIG. 3A; Paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region;
word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030) on the chip region (CH; FIG. 1; paragraph 0022), extending in a first direction, and spaced apart from each other in a second direction crossing the first direction; and
fine key patterns (DP; FIG. 3A; paragraph 0034) extending in the first direction on the edge region (SL; FIG. 1; paragraph 0022) and spaced apart from each other in the second direction (as shown in FIG. 2A, the patterns can occur in both a first and second direction, so a set of patterns can line up in the same direction as the word line equivalents), the fine key patterns being process- monitoring patterns (paragraph 0036),
wherein the fine key patterns (DP; FIG. 3A; paragraph 0034) comprise the same material (1; FIG. 3A; paragraph 0026) as at least a portion of the word lines (CI, CP; FIG. 3B; paragraph 0023; paragraph 0030), and
a first pitch of each of the fine key patterns (DP; FIG. 3A; paragraph 0034) (counting the fine key pattern as the whole set) is larger than a second pitch of four adjacent ones of the word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030), when measured in the second direction.
Regarding claim 19, FIG. 1, FIG. 2A, FIG. 3A, and FIG. 3B of Kwon et al. teach a semiconductor device, comprising:
a substrate (1; FIG. 3A; paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region
word lines (GE, GP, GI; FIG. 3A; FIG. 3B; paragraph 0023; paragraph 0030) extended in a first direction on the chip region (CH; FIG. 1; paragraph 0022) and spaced apart from each other in a second direction crossing the first direction (as shown in FIG. 2A, the patterns can occur in both a first and second direction, so a set of patterns can line up in the same direction as the word line equivalents); and
fine key patterns (DP; FIG. 3A; paragraph 0034) extended in the first direction on the edge region and spaced apart from each other in the second direction, the fine key patterns being process- monitoring patterns (paragraph 0036),
wherein each of the fine key patterns comprises a first key pattern (MP3; FIG. 3A; paragraph 0034) extending in the first direction, and a second key pattern (NP3; FIG. 3A; paragraph 0034) extending along opposite side surfaces of the first key pattern, and
a width of the first key pattern (MP3; W2; FIG. 3B; paragraph 0035) is larger than a distance between adjacent ones of the word lines (GE; FIG. 3A; paragraph 0030), when measured in the second direction.
Regarding claim 20, as best understood based on the 35 U.S.C. 112(b) issue identified above, FIG. 3A of Kwon et al. teaches the semiconductor device of claim 19, wherein
the second key pattern (NP3; FIG. 3A; paragraph 0034) comprises a first portion (NP3; FIG. 3A; paragraph 0034) covering a side surface of the first key pattern (MP3; FIG. 3A; paragraph 0034) and a second portion (NP3; FIG. 3A; paragraph 0034) covering an opposite surface of the first key pattern (MP3; FIG. 3A; paragraph 0034), and
the width of the first key pattern (MP3, W2; FIG. 3B; paragraph 0035) is larger than widths of the first portion (NP3, W3; FIG. 3B; paragraph 0035) and second portion (NP3, W3; FIG. 3B; paragraph 0035), when measured in the second direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. in view of Lee et al. (US 20210103079 A1).
Regarding claim 1, FIG. 1, FIG. 2A, FIG. 3A, and FIG. 3B of Kwon et al. a semiconductor device, comprising:
a substrate (1; FIG. 3A; paragraph 0026) including a chip region (CH; FIG. 1; paragraph 0022) and an edge region (SL; FIG. 1; paragraph 0022) enclosing the chip region; and
at least one coarse key pattern (KP; FIG. 2A; paragraph 0023) at least partly divided into fine key patterns (DP; FIG. 3A; paragraph 0034) on the edge region, extending in a first direction (FIG. 3A) and spaced apart from each other in a second direction (FIG. 3A) that crosses the first direction, the at least one coarse key pattern being a process-monitoring pattern (paragraph 0036),
wherein each of the fine key patterns comprise:
a first key pattern (MP3; FIG. 3A; paragraph 0034) extending in the first direction; and
a second key pattern (NP3; FIG. 3A; paragraph 0034) comprising a first portion (NP3; FIG. 3A; paragraph 0034) and a second portion (NP3; FIG. 3A; paragraph 0034),
wherein each of the first portion and the second portion have widths (NP3, W3; FIG. 3B; paragraph 0035) that are less than a width of the first key pattern (MP3, W2; FIG. 3B; paragraph 0035), when measured in the second direction.
Kwon et al. does not teach the first portion extending along and adjacent to a side surface of the first key pattern, and the second portion extending along and adjacent to an opposite side surface of the first key pattern.
FIG. 3 of Lee et al. teaches within an alignment key (paragraph 0078) a thin light blocking pattern (110; FIG. 3; paragraph 0078) directly surrounding a layer pattern (130; FIG. 3; paragraph 0078) in a way that corresponds with the first and second portions of the claimed invention.
Kwon et al. and Lee et al. are both analogous to the claimed invention in that they involve semiconductor devices with patterns. Therefor, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Kwon et al. so that the first and second portions are adjacent to the first fine key pattern. These are known arrangements of key patterns in these structures (paragraph 0025).
Regarding claim 2, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. FIG. 3A of Kwon et al. further teaches the device wherein the first portion (NP3; FIG. 3A; paragraph 0034), the first key pattern (MP3; FIG. 3A; paragraph 0034), and the second portion (NP3; FIG. 3A; paragraph 0034) are sequentially arranged in the second direction.
Regarding claim 3, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. FIG. 3B of Kwon et al. further teaches the device wherein the width of the first portion (NP3, W3; FIG. 3B; paragraph 0035) is substantially equal to the width of the second portion (NP3, W3; FIG. 3B; paragraph 0035).
Regarding claim 4, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. FIG. 2A of Kwon further teaches the device wherein
the at least one coarse key pattern (KP; FIG. 2A; paragraph 0023) comprises a first coarse key pattern (KP; FIG. 2A; paragraph 0023) extending in the first direction, and a second coarse key pattern (KP; FIG. 2A; paragraph 0023) extending in the second direction, and
each of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the first coarse key pattern (KP; FIG. 2A; paragraph 0023) is elongated in the first direction to have a length that is larger than each of the fine key patterns of the second coarse key pattern (KP; FIG. 2A; paragraph 0023).
Regarding claim 5, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. FIG. 2A of Kwon et al. further teaches device wherein a number of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the first coarse key pattern (KP; FIG. 2A; paragraph 0023) is less than a number of the fine key patterns (KP; FIG. 2A; paragraph 0023) of the second coarse key pattern (KP; FIG. 2A; paragraph 0023).
Regarding claim 7, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. FIG. 2A and FIG. 3A of Kwon et al. further teach the device, wherein the at least one coarse key pattern (KP; FIG. 2A; paragraph 0023) further comprises inner patterns (ST; FIG. 3A; paragraph 0028) between the fine key patterns (DP; FIG. 3A; paragraph 0034) which are adjacent to each other in the second direction.
Regarding claim 8, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 7. FIG. 3A of Kwon et al. further teaches the device wherein the fine key patterns (BP; FIG. 3A; paragraph 0034) and the inner patterns (ST; FIG. 3A; paragraph 0028) are alternately arranged in the second direction.
Regarding claim 9, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 7. FIG. 3A of Kwon et al. further teaches the device wherein the first portions (NP3; FIG. 3A; paragraph 0034), the first key patterns (MP3; FIG. 3A; paragraph 0034), the second portions (NP3; FIG. 3A; paragraph 0034), and the inner patterns (ST; FIG. 3A; paragraph 0028) are alternately arranged in the second direction.
Regarding claim 13, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 7. FIG. 3A and FIG. 3B of Kwon et al. further teach the device wherein a width of each of the inner patterns (ST; FIG. 3B; paragraph 0028) is greater than a width (NP3, W3; FIG. 3B; paragraph 0035) of each of the first portion (NP3; FIG. 3A; paragraph 0034) and the second portion (NP3, W3; FIG. 3A; paragraph 0035), when measured in the second direction.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. as applied to claim 1 above, and further in view of Nigam et al. (US 20200176255 A1).
Regarding claim 6, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 1. Neither Kwon et al. not Lee et al. teach a first pitch of each of the fine key patterns in the second direction ranges from 80 nm to 150 nm.
FIG. 4 of Nigam et al. teaches the pitch (P1; FIG. 4; paragraph 0033) between two sets of patterns of lines (110; FIG. 4; paragraph 0033) may range from about 40 nm to about 400 nm (paragraph 0033).
Kwon et al., Lee et al., and Nigam et al. are all considered analogous to the claimed invention because they are within the same field of semiconductor devices with patterns. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date to make the first pitch of each of the fine key patterns in the second direction ranges from 80 nm to 150 nm. Creating such a small pitch would be through pitch multiplication, which would extend the capabilities of the photolithography technique beyond its minimum pitch to form sublithographic features having a pitch of less than about 100 nm (paragraph 0009).
Allowable Subject Matter
Claims objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 7. Kwon et al. further teaches the device wherein each of the fine key patterns (BP; FIG. 3A; paragraph 0034) further comprises third key patterns (ST; FIG. 3A; paragraph 0028) interposed between the first key pattern (MP3; FIG. 3A; paragraph 0034) and the second key pattern (NP3; FIG. 3A; paragraph 0034). Neither Kwon et al. nor Lee et al. teach the device wherein the third key patterns are between the second key pattern and the inner pattern adjacent thereto. Nigam et al. does not teach this limitation nor any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Claim 11 is dependent on claim 10 and is therefore allowed.
Regarding claim 12, the combination of Kwon et al. in view of Lee et al. teaches the semiconductor device of claim 7. Neither Kwon et al. nor Lee et al. teach the device wherein a width of each of the inner patterns is substantially equal to from the width of the first key pattern, when measured in the second direction. Nigam et al. does not teach this limitation nor any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Regarding claim 15, Kwon et al. teaches the semiconductor device of claim 14. Kwon et al. does not teach the device wherein a difference between the first pitch and the second pitch ranges from 4 nm to 10 nm. Lee et al. and Nigam et al. do not teach this limitation, nor do any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Regarding claim 16, Kwon et al. teaches the semiconductor device of claim 14. Kwon et al. does not teach the device wherein a distance between adjacent ones of the fine key patterns is larger than a distance between adjacent ones of the word lines. Lee et al. and Nigam et al. do not teach this limitation, nor do any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Regarding claim 17, Kwon et al. teaches the semiconductor device of claim 14, wherein each of the fine key patterns comprises a first key pattern (MP3; FIG. 3A; paragraph 0034) extending in the first direction, and a second key pattern (NP3; FIG. 3A; paragraph 0034) extending along opposite side surfaces of the first key pattern. Kwon et al. does not teach the device wherein a width of the first key pattern is larger than a distance between adjacent ones of the word lines, when measured in the second direction. Lee et al. and Nigam et al. do not teach this limitation, nor do any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Regarding claim 18, Kwon et al. teaches the semiconductor device of claim 14, further comprising: an inner pattern (ST; FIG. 3A; paragraph 0028) between adjacent ones of the fine key patterns (DP; FIG. 3A; paragraph 0034). Kwon et al. does not teach the device wherein a width of the inner pattern is larger than a distance between adjacent ones of the word lines, when measured in the second direction. Lee et al. and Nigam et al. do not teach this limitation, nor do any other sources. Therefore, it would be improper in hindsight to modify Kwon et al.
Response to Arguments
Applicant's arguments filed April 9th, 2026 have been fully considered but they are not persuasive. The arguments for claim 14 and 19 push that the gate electrodes (which act as the word line equivalents) and the patterns of Kwon et al. are demonstrated to be perpendicular as shown in FIG. 3 of Kwon et al.. However, FIG. 2A of Kwon et al. demonstrates that the patterns can face in either a first direction or a second direction, so there do exist some patterns that align with the direction of the word line equivalents in Kwon et al., as the structure of FIG. 3A is not indicative of the full product.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen (US 20190101835 A1) concerns an error measurement structure with pattern structures similar to those in the claimed invention. Ha et al. (US 20140054793 A1) concerns a COF substrate that includes geometric conductive patterns.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB ALEXANDER VLCEK/ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
Prosecution Insights