DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/3/2026 has been entered.
Response to Arguments
Applicant's arguments filed 3/3/2026 have been fully considered but they are not persuasive.
Applicant’s argument is that the reference does not disclose or suggest structure such as a timing controller that is explicitly configured to perform the claimed function.
The Examiner respectfully disagrees with Applicant’s argument.
As noted throughout prosecution, MPEP 2114 states that “apparatus claims cover what a device is, not what a device does” and “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim.
Applicants claimed “timing controller” that relate to structures are that it is item 150 in Fig. 1 which is described in paragraph 38 broadly as:
The timing controller 150 may control the pixel array 110, the row decoder 120, the analog-to-digital converter 130, the output buffer 140, and the like. To perform operations of the pixel array 110, the row decoder 120, the analog-to-digital converter 130, the output buffer 140, and the like, the timing controller 150 may supply control signals, such as clock signals and timing control signals. The timing controller 150 may include a logic control circuit, a phase locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.
Or, in paragraph 161 as:
For example, the timing controller 150 may be implemented as processing circuitry. The processing circuitry specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.
However, the claims have chosen to further limit the timing controller functionally which limitations related to how it is used to operate the image sensor. Additionally, the claim also used configured to language when limiting the timing controller functionally. The term “configured to” is not a positive recitation of occurrence.
As the claim does not include any of the described structure from the specification, the broadest reasonable interpretation of the claimed structures are that the timing controller is capable of providing timing signal to indirectly connected transistors as needed.
Oike similarily shows these same required structures in Fig. 1 as a system control section 115 which is described in paragraph 75 as:
The system control section 115 has, for example, a timing generator operable to generate a variety of timing signals, and performs drive control on the vertical drive section 112, the column processing section 113 and the horizontal drive section 114, etc. based on the various timing signals generated by the timing generator.
Therefore, the Examiner maintains that Oike discloses all the required structures of the claim and that limitations relating to a rolling shutter scheme of operation and the specific timings of driving the transistors are functional recitations related to the manner in which the device is operated that do not limit the structures of the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21 and 24-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication 2011/0241079 A1 to Oike et al.
NOTE: it is noted that "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) and "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114. Thus, the Examiner suggests any possible amendments to the claims to overcome Oike be related to structural differences.
With respect to claim 21 Oike discloses, in Fig. 1-38, an image sensor operating in a rolling shutter scheme (paragraph 63; NOTE: operating in a rolling shutter scheme is operational and does not limited the claimed structures, which are all anticipated by Oike (see below)) comprising: a plurality of first pixels arranged in a first row and configured to generate first charges in response to a first exposure (paragraph 65 and 68; where the pixels are controlled by row to make exposures); and a plurality of second pixels arranged in a second row different from the first row and configured to generate second charges in response to a second exposure different from the first exposure (paragraph 65 and 68; where the pixels are controlled by row to make exposures), wherein at least one pixel of the plurality of first pixels includes a photo diode configured to generate the first charges in response to the first exposure to an incident light (paragraph 79), a first floating diffusion area (MEM) configured to store the first charges generated by the photo diode (paragraph 82), a first transfer transistor configured to electrically connect the photo diode to the first floating diffusion area in response to a first transmission signal (paragraph 82-83), wherein a gate electrode of the first transfer transistor at least partially overlaps the first floating diffusion area in a horizontal direction (Fig. 2 or 18-19), a second floating diffusion area (FD) spaced apart from the first floating diffusion area (paragraph 77 and 84), wherein one end of the second floating diffusion area is electrically connected to a gate of a drive transistor (127) (paragraph 84-85), and a second transfer transistor configured to electrically connect the first floating diffusion area to the second floating diffusion area in response to a second transmission signal (paragraph 84), wherein the image sensor further comprises a timing controller (115) configured to cause the first transfer transistor to be turned off before the second transfer transistor is turned off during the rolling shutter scheme (paragraph 68, 75 and 83-84; where the timing controller is configured to cause this to happen by providing signals TRX and TRG; note all structure limitations are met and therefore Oike anticipates the claim as being part of a rolling shutter scheme is a manner of operating the device. See MPEP 2114), and wherein the timing controller is configured to cause the first transfer transistor and the second transfer transistor to operate such that a first period in which the first transfer transistor is turned on at least partially overlaps a second period in which the second transfer transistor is turned on (paragraph 236; where there is a state where TRX and TRG are applied at the same time, however, this limitation is still further limiting the timing controller based on its operation and does not further limit any structures).
With respect to claim 24 Oike discloses, in Fig. 1-38, the image sensor of claim 21, wherein the at least one pixel of the plurality of first pixels further comprises: a third floating diffusion area positioned between the first floating diffusion area and the second floating diffusion area and spaced from the first floating diffusion area and the second floating diffusion area; and a third transfer transistor configured to electrically connect the first floating diffusion area to the third floating diffusion area, wherein a gate electrode of the third transfer transistor overlaps the third floating diffusion area in the horizontal direction (Fig. 22; where there is an embodiment with multiple FDs thus the original FD of Fig. 2 becomes the third FD of the claim and the other would be interpreted as the second FD of the claim).
With respect to claim 25 Oike discloses, in Fig. 1-38, the image sensor of claim 21, wherein the gate electrode of the first transfer transistor includes a first gate electrode portion (122A) and a second gate electrode portion (122B), which are physically spaced from each other (Fig. 19), wherein the first gate electrode portion overlaps the photo diode in the horizontal direction (Fig. 19; where at least N type portion 134 is overlapped by 122A), and wherein the second gate electrode portion overlaps the first floating diffusion area in the horizontal direction (Fig. 19).
Allowable Subject Matter
Claims 1, 2, 10 and 14 are allowed in view of Applicant’s amendment and for reasons as made clear throughout prosecution.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M PASIEWICZ whose telephone number is (571)272-5516. The examiner can normally be reached M-F 9 AM - 5:30 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, George Eng can be reached at (571)272-7495. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL M PASIEWICZ/Primary Examiner, Art Unit 2699
April 9, 2026
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