Prosecution Insights
Last updated: April 19, 2026
Application No. 18/311,085

CHIP RESISTOR AND MOUNTING STRUCTURE THEREOF

Non-Final OA §102§103§112§DP
Filed
May 02, 2023
Examiner
LEE, KYUNG S
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co. Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
984 granted / 1129 resolved
+19.2% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
33 currently pending
Career history
1162
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
41.4%
+1.4% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1129 resolved cases

Office Action

§102 §103 §112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 46-58 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 5-6 and 13-19 of U.S. Patent No. 11,676,742. Although the claims at issue are not identical, they are not patentably distinct from each other. Similar structural limitations are found in the comparative claims listed below. Claims for Current Application Claims for US Pat. 11,676,742 Claims 46 and 47; electrode comprises a plate, the plate having a pointed portion and a curved surface spaced apart from the pointed portion in the thickness direction, and wherein the outer lateral surface of the plate is offset ahead of the resistive outer lateral surface in the first direction Claim 1; a conductive plate having a pointe portion and a curve surface spaced apart from the pointed portion in the thickness direction of the electrode, and wherein the conductive outer lateral face is offset ahead of the resistive outer lateral face in the first direction Claim 48; the pointed portion being closer to the front surface than to the rear surface, the curved surface being closer to the rear surface than to the front surface Claim 2; the pointed portion being closer to the front surface than to the rear surface, the curved surface being closer to the rear surface than to the front surface Claim 49; the pointed portion being closer to the rear surface than to the front surface, the curved surface being closer to the front surface than to the rear surface Claim 3; the pointed portion being closer to the rear surface than to the front surface, the curved surface being closer to the front surface than to the rear surface Claim 50; at least one plated layer formed in the plate Claim 5; at least one plated layer formed in the conductive plate Claim 51; a layer formed in the plate and held in contact with the resistive member Claim 6; a conductive layer formed in the plate and held in contact with the resistive member Claim 52; substrate contains glass material Claim 13; substrate contains glass material Claim 53; part of the resistive member is embedded in the substrate Claim 14; part of the resistive member is embedded in the insulative substrate Claim 54; the electrode comprises a Cu plated layer in direct contact with the plate Claim 15; the electrode comprises a Cu plated layer in direct contact with the conductive plate Claim 55; electrode comprises a Ni plated layer and a Sn plated layer, the Ni layer being disposed between the Cu layer and the Sn layer Claim 16; electrode comprises a Ni plated layer and a Sn plated layer, the Ni layer being disposed between the Cu layer and the Sn layer Claim 56; a sheet layer disposed between the resistive member and the electrode, wherein the curved surface of the electrode is exposed from the sheet layer Claim 17; a sheet layer disposed between the resistive member and the electrode, wherein the curved surface of the electrode is exposed from the sheet of insulating layer Claim 57; the sheet layer is smaller in thickness than each of the resistive member and the electrode Claim 18; the sheet layer is smaller in thickness than each of the resistive member and the electrode Claim 58; the outer lateral face of the plate is flat and directly connected to the curved surface Claim 19; the conductive outer lateral face of the plate is flat and directly connected to the curved surface Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 56-57 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 56 recites the limitation "the curved surface" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claim 56 also recites the limitation “a sheet of layer”. It is unclear what is meant by the sheet of layer.” Claim 57 depends on claim 56. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 46-53, 56, 58-59 and 63 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoneda (US Pat. 6,492,896). Regarding claims 46-47, Yoneda teaches a chip resistor (see at least col. 3, lines 45-50 and fig. 1) comprising: a substrate (insulating substrate comprising of layers 1 and 5); a resistive member (resistor body 4) supported by the substrate; an electrode (electrode 24) held in contact with the resistive member, wherein the electrode comprises a plate having an outer lateral face that faces in a first direction perpendicular to a thickness direction of the plate (plate 24 has an outer lateral face in either left to right of figure or in and out of the figure; see fig. 1), the resistive member has a resistive outer lateral face that faces in the first direction (both the resistive lateral face and the electrode lateral face are facing the first direction perpendicular to the thickness direction), and the outer lateral face of the plate (24) is offset ahead of the resistive outer lateral face in the first direction (the outer lateral face of the electrode 24 is further from the center of the device compared to the resistive member 4); and the plate (24) includes a pointed portion (lower corner pointed portion of the electrode 24) and a curved surface (opposite rounded corner surface) spaced apart from the pointed portion in the thickness direction. Regarding claim 48, Yoneda teaches the chip resistor, wherein the plate has a front surface (surface closer to the electrode 21; see fig. 1) and a rear surface (surface closer to the layer 53) that are spaced apart from each other in the thickness direction, the pointed portion being closer to the front surface than to the rear surface, the curved surface being closer to the rear surface than to the front surface. Regarding claim 49, Yoneda teaches the chip resistor, wherein the plate has a front surface (surface closer to the layer 53) and a rear surface (surface closer to the electrode 21) that are spaced apart from each other in the thickness direction, the pointed portion being closer to the rear surface than to the front surface, the curved surface being closer to the front surface than to the rear surface. Regarding claim 50, Yoneda teaches the least one plated layer formed on the plate (plating layers 25a and 25b). Regarding claim 51, a layer (electrode 21) is formed on the plate (electrode 24) and is held in contact with the resistive member (4). Regarding claims 52-53, the substrate contains a glass material (upper substrate layer 5 comprises of glass; col. 5, lines 43-54), and at least part of the resistive member is embedded in the substrate (resistive layer 4 is embedded between eh upper and lower substrate layers 1 and 5; see fig. 1). Regarding claim 56, a sheet layer (layer 52; see fig. 1) is disposed between the resistive member (4) and the electrode (24). Regarding claim 58, the outer lateral face of the plate is flat and directly connected to the curved surface (electrode 24 has a flat surface which is directly connected to the curved surface; see fig. 1). Regarding claim 59, the substrate includes a glass fiber portion and a resin portion (substrate layer 5 comprises of layers being composed of glass powder and epoxy resin; see col. 5, lines 43-59). Regarding claim 63, the plate (electrode 24) is formed of silver (col. 5, lines 5-10). Claims 46 and 54-55 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US Pub. 2009/0217511). Regarding claim 46, Chen teaches a chip resistor (see at least paragraph 0030 and fig. 21) comprising: a substrate (dielectric substrate 1; paragraph 0033); a resistor member (resistor film 606) supported by the substrate; an electrode (electrodes 604) held in contact with the resistive member; wherein the electrode comprises a plate having an outer face that faces in a first direction perpendicular to a thickness direction of the plate, the resistive member has a resistive outer lateral face that faces in the first direction (both the resistive outer lateral face and the electrode lateral face are facing the first direction; see fig. 20), and the outer lateral face of the plate being offset ahead of the resistive outer lateral face in the first direction (the lateral face of the electrode being farther from the center of the resistor device). Regarding claims 54 and 55, the electrode 604 is directly coated with copper (copper 371; see paragraph 0041), nickel and tin, respectively. Claims 46, 56-57 and 64-65 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US Pub. 2011/0057766). Regarding claim 46, Chen teaches a chip resistor (surface mount resistor 30; paragraph 0022 and fig. 7) comprising: a substrate (polyester and/or polyethylene substrate 32 on top and bottom of the resistor member 31b; paragraphs 0025 and 0037); a resistor member (resistor body 31b; paragraph 0037) supported by the substrate; an electrode (electrodes 35; paragraph 0030) held in contact with the resistive member (31b); wherein the electrode comprises a plate having an outer face that faces in a first direction perpendicular to a thickness direction of the plate (flat outer surface of the electrode 35), the resistive member has a resistive outer lateral face that faces in the first direction (both the resistive outer lateral face and the electrode lateral face are facing the first direction), and the outer lateral face of the plate being offset ahead of the resistive outer lateral face in the first direction (the lateral face of the electrode 35 being farther from the center of the resistor member 31b). Regarding claim 56, a sheet of layer (inner metal 333; refer to fig. 2 for the reference number) is disposed between the resistive member (31) and the electrode (35), wherein a curved surface of the electrode (curves surfaces; see fig. 7) is exposed from the sheet of layer. Regarding claim 57, the sheet of layer has a smaller thickness than the resistive member and the electrode (layer 333 is 2-3 micrometers, the resistive member 31 is 0.3 mm, and the electrode 35 surrounds the resistive member, the layer 333 and heat transfer portion 331; see at least paragraphs 0028, 0030-0032 and 0035). Regarding claim 64, Chen’766 teaches the electrodes 35 covering at least the resistor member 31 and the heat transfer portion 33 in the thickness direction (see at least paragraph 0030-0032). Regarding claim 65, an inner lateral surface of the electrode 35 is in direct contact with a heat conducting portion (heat transfer portions 33 and 34; paragraphs 0029-0032). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 60 is rejected under 35 U.S.C. 103 as being unpatentable over Yoneda in view of Chen et al. (US Pub. 2011/0057766). Regarding claim 60, Yoneda teaches the claimed invention, including laser trimming the resistive element, wherein the portion of the substrate (52) is filled within the grooves formed on the resistive element (col. 5, lines 43-59). Yoneda, however, does not teach the resistive element having a serpentine-shape. Chen’766 teaches a resistive device, wherein the resistive element having a serpentine-shape (see fig. 3 and paragraph 0023) formed by cutting into the resistive element for the purpose of adjusting the resistivity of the resistive element. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to combine the teachings of Chen’766 with Yoneda, since the method taught by Chen’766 allows for fine tuning and adjusting of the resistance to the device of Yoneda. Allowable Subject Matter Claims 61 and 62 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 61, the prior art does not teach or suggest the substrate having a first outer lateral surface in the first direction, and that is flush with the resistive outer lateral face. Claim 62 depends on claim 61. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYUNG S LEE/Primary Examiner, Art Unit 2833
Read full office action

Prosecution Timeline

May 02, 2023
Application Filed
Jan 29, 2026
Non-Final Rejection — §102, §103, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+4.8%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 1129 resolved cases by this examiner. Grant probability derived from career allow rate.

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