DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, species B (claims 1, 3, 13, 14 and 16) in the reply filed on 2-2-2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 13, 14, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaku (US 2013/0181353).
[claim 1] An electronic component (fig. 12-14, fig. 1-11 could also be used, note that the only difference between the two figure sets is that fig. 1-11 and fig. 12-14 is that 1-11 has one single continuous die aligning element 18 while fig. 12-14 may have it discontinuous 32, see fig. 1 and 12, [0050]) comprising: a support that includes a die-attachment surface (16, fig. 12, 14) that defines a horizontal plane (extending side to side, fig. 12), with a vertical direction (into the page in fig. 12) being perpendicular to the horizontal plane; a first die (14, fig. 12, 14) that is vertically fixed to the die-attachment surface with a die-attach material (34, fig. 12,14, see [0053] which explains the adhesive bond between the die and the substrate); and a die-aligning element (32B, 32C, fig. 12, 14) that is adjacent to the die-attachment surface and that is integral with at least one of the support or a packaging structure that is rigidly attached to the support (fig. 14, [0053]), wherein the die-aligning element comprises a first die-alignment wall that is horizontally fixed to a first side of the first die with the die-attach material (34, fig. 14, [0053]), and wherein a second side of the first die that is opposite to the first side of the first die is horizontally unfixed (unfixed from the die-aligning element, 32, fig. 12), wherein the die-attach material forms an interface layer between the first side of the first die and the first die-alignment wall (fig. 14).
[claim 3] The electronic component according to claims claim 1, wherein a vertical distance from the die-attachment surface to a bond line between the first die and the die-attach material is D (D is near zero as can be seen in fig. 14, [0053]), and a vertical height of the first die is H (side of the die 14, see fig. 14, see also fig. 5) , and wherein the first die-alignment wall has a first wall height (fig. 14, fig. 5) in the vertical direction that is greater than D and less than D + H/2 (fig. 14, fig. 5).
[claim 13] The electronic component according to claim 1, wherein the die-aligning element comprises a cuboid shape (see e.g. the example of fig. 8).
[claim 14] An electronic component (fig. 12-14, fig. 1-11 could also be used, note that the only difference between the two figure sets is that fig. 1-11 and fig. 12-14 is that 1-11 has one single continuous die aligning element 18 while fig. 12-14 may have it discontinuous 32, see fig. 1 and 12, [0050]) comprising: a support that includes a die-attachment surface (16, fig. 12, 14) that defines a horizontal plane (extending side to side, fig. 12), with a vertical direction (into the page in fig. 12) being perpendicular to the horizontal plane; a die-aligning element (32B, 32C, fig. 12, 14) that is integral with the support and that includes a first die- alignment wall that vertically extends from the die-attachment surface (fig. 14, [0053]); and a first die (14, fig. 12, 14) that is vertically fixed to the die-attachment surface with a die-attach material (34, fig. 14, [0053]) and that includes a first side that is horizontally fixed to the die-aligning element with the die- attach material (34, fig. 14, [0053]), wherein a second side of the first die that is opposite to the first side of the first die is horizontally unfixed (unfixed from the die-aligning element, 32, fig. 12), wherein the die-attach material forms an interface layer between the first side of the first die and the first die-alignment wall (fig. 14).
[claim 16] The electronic component according to claims 14. wherein a vertical distance from the die-attachment surface to a bond line between the first die and the die-attach material is D (D is near zero as can be seen in fig. 14, [0053]), and a vertical height of the first die is H (side of the die 14, see fig. 14, see also fig. 5), and wherein the first die-alignment wall has a first wall height in the vertical direction that is greater than D and less than D + H/2 (fig. 14, fig. 5).
Response to Arguments
Applicant's arguments filed 6-29-2026 have been fully considered but they are not persuasive.
Applicant argues that Yaku teaches, in [0046], direct edge to pattern contact with no interface. At the outset it is noted that paragraph refers to a different embodiment than that of fig. 12-14. Moreover, [0046] merely states that that the semiconductor device 14 abuts the pattern 18 not that that there is no adhesive therebetween. To the contrary abutment between the semiconductor device in pattern is required in order for the adhesive to work.
Applicant argues that Yaku teaches that that adhesive between the semiconductor die and pattern is a defect rather than a fixation of mechanism. That excess adhesive is evacuated from the interface between the semiconductor die and pattern and that fig. 14 depicts a contamination scenario to be avoided. To the contrary [0053] states that fig. 14 of Yaku shows how excess adhesive is removed not a defect scenario. Applicant appears to confuse the removal of excess adhesive as meaning that there is no adhesive at all. In the second drawing of fig. 14, an adhesive 34 is deposited on the substrate 16. In the next drawing the semiconductor die 14 is deposited on the adhesive 34 and substrate. As can be seen in the second to last drawing of fig. 14, the semiconductor die 14 abuts the substrate 16 after pushing the die onto the substate, this certainly does not mean that that there is no adhesive between die and substrate as this would confound the very function of the adhesive in the device. That last two drawings of fig. 14 shows the semiconductor die 14 being laterally pushed to remove excess adhesive. The effect of this would be similar to process of pushing the die onto the substrate, namely a thin adhesive between the pattern 32 and die 14, otherwise the adhesive would serve no purpose. Moreover, even assuming for the sake of argument that this was not true, excess adhesive 34 is at least present adjacent the upper sidewall of the die, this would at least be between the pattern 32 and the upper portion of the semiconductor die sidewall.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AMAR MOVVA/Primary Examiner, Art Unit 2898
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