DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “conformally depositing an insulating layer above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate” as recited in lines 9-10 of claim 1 and “the first set of connecting vias electrically connects the first metal plate to underlying structures disposed in the semiconductor substrate” as recited in lines 1-2 of claim 3 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 6-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chudzik et al. (US PAT. 7,186,625).
Chudzik et al. teach a process of making an interdigitated metal-insulator-metal capacitor, comprising: forming a first set of connecting vias (16, Fig. 4) within a first dielectric layer (14, Fig. 4) disposed above a semiconductor substrate (12, Fig. 4, col. 4, lines 11-26); depositing a first conductive material (20, Fig. 5) above the first dielectric layer, the first conductive material filling the first set of connecting vias as shown in Fig. 5 (col. 4, lines 27-39); patterning a top portion of the first conductive material to form a first set of interdigitated electrodes (18, Figs. 6-8, col. 4, line 27 to col. 5, line 3), a remaining portion (10, Figs. 6-8) of the first conductive material below the first set of interdigitated electrodes comprising a first metal plate; and conformally depositing an insulating layer (30, Fig. 9, col. 5, lines 4-17) above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate.
Re. claim 2: A second conductive material (48, Fig. 12, col. 5, lines 44-49) is deposited above the insulating layer, wherein the depositing the second conductive material forms a second set of interdigitated electrodes (36, Fig. 10) interleaved with the first set of interdigitated electrodes; and patterning a top portion of the second conductive material to form a second set of connecting vias (48, Fig. 12), a remaining portion of the second conductive material below the second set of connecting vias comprising a second metal plate as shown in Fig. 12.
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Re. claim 3: The first set of connecting vias electrically connects the first metal plate to underlying structures disposed in the semiconductor substrate as shown in Figs. 6-8.
Re. claim 6: The second set of connecting vias electrically connects the second metal plate to subsequently formed structures as shown in Fig. 12.
Re. claims 7 and 8: Chudzik et al. also teach that the electrical conductive material, which can be formed the first and second conductive materials is made of TiN, TaN, Cu, or Ta (col. 4,lines 3-4).
Re. claims 9 and 10: Chudzik et al. also teach that the insulating layer comprises a high-k dielectric material such as aluminum oxide, hafnium oxide, and tantalum oxide (col. 2, lines 24-29).
Re. claim 11: The first set of interdigitated electrodes and the second set of interdigitated electrodes have an aspect ratio of at least 1:1 for increasing a total capacitance of the metal-insulator-metal capacitor structure as shown in Fig. 12 (col. 5, lines 56-61).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chudzik et al.
Chudzik et al. teach all limitations as set forth above including, as per claim 4, the first set of interdigitated electrodes are in electrical communication with the first metal plate (col. 4, lines 27-32) and, as per claim 5, the second set of interdigitated electrodes are in electrical communication with the second metal plate, but silent the electrical communication with the first metal plate or the second metal plate increasing a charge collecting surface area of the interdigitated metal-insulator-metal capacitor. Since it has been held that where the general conditions of a claim, such as the first set of interdigitated electrodes electrical communicating with the first metal plate or the second metal plate, are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). Therefore, since such a modification, such as the electrical communication with the first metal plate or the second metal plate increasing a charge collecting surface area of the interdigitated metal-insulator-metal capacitor, would have been an obvious design consideration that is within the purview of one having ordinary skill in the art to provide the well-known benefit of obtaining desirable the interdigitated metal-insulator-metal capacitor.
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chudzik et al. as applied to claim 1 above, and further in view of Hsieh et al. (US PAT. 7,348,654).
Chudzik et al. teach all limitations as set forth above, but silent a second insulating layer disposed above the semiconductor substrate and below the first set of connecting vias. Hsieh et al. teach an interdigitated metal-insulator-metal capacitor including an insulating layer (114, col. 4, lines 41-52) disposed above a semiconductor substrate (110) and below a first set of connecting vias (such as forming a set of interdigitated electrodes 122-134, col. 5, lines 10-31) in order to isolate the substrate from a top conductive layer. Therefore, it would have been obvious to one of ordinary skill in the art, at the time of the effective filing date of the claimed invention was made, to a person having ordinary skill in the art to modify a process of fabricating the interdigitated metal-insulator-metal capacitor of Chudzik et al. by a second insulating layer disposed above the semiconductor substrate and below the first set of connecting vias as taught by Hsieh et al. in order to isolate the substrate from a top conductive layer.
However, Hsieh et al., silent nitrogen-doped silicon carbide as the second insulating layer, as per claim 13. Since it has been held that where the general condition, such as a dielectric property of the insulating layer, of a claim are disclosed in the prior art, discovering the optimum or workable rangers involves only routine skill in the art. MPEP 2144.04 (il-A). The applicant has not disclosed any criticality for the claimed limitations. It is generally known to the person skilled in the art that both materials are equivalent and can be interchanged with one another where circumstances make it desirable. It has been also held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use. In re Leshin, 125 USPQ 416 (CCPA 1960).
The Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Seidel et al. (US PAT. 10,644,099), Briggs et al. (US PAT. 9,837,485), and Hsia et al. (US PAT. 7,927,990) are cited to further show the state of the art with respect to a process of making an interdigitated metal-insulator-metal capacitor.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL D KIM whose telephone number is (571)272-4565. The examiner can normally be reached Monday-Friday: 6:00 AM-2:00 PM.
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/PAUL D KIM/Primary Examiner, Art Unit 3729