DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-16) in the reply filed on 08/14/2025 is acknowledged.
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 08/14/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3 and 11 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Lei et al. (US 2022/0157977) hereinafter “Lei”.
Regarding claim 1, Fig. 1A of Lei teaches a power semiconductor device comprising: a substrate (Item 102); a channel layer (Item 104; Paragraph 0031 where the channel is at the very top) disposed on or over the substrate (Item 102); a barrier layer (Item 106) disposed on the channel layer (Item 104); a capping layer (Item 110) disposed on the barrier layer (Item 106); a gate electrode (Item 120) disposed on the capping layer (Item 110); a source electrode (Item S) and a drain electrode (Item D) that are separated from the gate electrode (Item 120), the source electrode (Item S) and the drain electrode (Item D) forming ohmic contact regions on the barrier layer (Item 106); and an insulation film (Item 108) disposed on the barrier layer (Item 106), wherein the barrier layer (Item 106) is configured such that a first side (Top surface of Item 106 to the right of Item 110) of an upper surface of the barrier layer (Item 106) is stepped between the gate electrode (Item 120) and the drain electrode (Item D).
Regarding claim 3, Fig. 1A of Lei further teaches where the barrier layer (Item 106) comprises a first recess portion, the first recess portion being spaced apart from an edge of the drain electrode (Item D) on the upper surface of the barrier layer (Item 106) and being recessed downward.
Claim 11 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Endoh (US 2017/0263742) hereinafter “Endoh”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lei et al. (US 2022/0157977) hereinafter “Lei” in view of Chen et al. (US 2017/0338810) hereinafter “Chen”.
Regarding claim 4, Lei teaches all of the elements of the claimed invention as stated above except where the first recess portion comprises a plurality of first recess sub-recess portions and the plurality of first recess sub-portions are spaced apart from each other along an orthogonal direction.
Fig. 27 of Chen teaches where a first recess (Item 2102) comprises a plurality of first recess sub-recess portions and the plurality of first recess sub-portions are spaced apart from each other along an orthogonal direction.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first recess portion comprises a plurality of first recess sub-recess portions and the plurality of first recess sub-portions are spaced apart from each other along an orthogonal direction because the plurality of recessed regions increases the channel resistance which reduces threshold drain voltage (Chen Paragraph 0097).
Alternatively, Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Fujimoto (US 2015/0263155) hereinafter “Fujimoto” in view of Lei et al. (US 2022/0157977) hereinafter “Lei”.
Regarding claim 1, Fig. 3 of Fujimoto teaches a power semiconductor device comprising: a substrate (Item 10); a channel layer (Item 14) disposed on or over the substrate (Item 10); a barrier layer (Item 16) disposed on the channel layer (Item 14); a capping layer (Item 24) disposed on the barrier layer (Item 16); a gate electrode (Item 26) disposed on the capping layer (Item 24); a source electrode (Item 18) and a drain electrode (Item 20) that are separated from the gate electrode (Item 26), the source electrode (Item 18) and the drain electrode (Item 20) forming ohmic contact regions (Paragraph 0023) on the barrier layer (Item 16); wherein the barrier layer (Item 16) is configured such that a first side (Top surface of Item 16 to the right of Item 26) of an upper surface of the barrier layer (Item 16) is stepped (See Picture 1 below) between the gate electrode (Item 26) and the drain electrode (Item 20).
Fujimoto does not teach an insulation film disposed on the barrier layer.
Fig. 1A of Lei teaches where an insulation layer (Item 108) is disposed on a barrier layer (Item 106).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an insulation film disposed on the barrier layer because the insulation film electrically isolates the barrier layer from electrically conductive structures above it (Lei Paragraph 0029).
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Picture 1 (Labeled version of Fujimoto Fig. 3)
Alternatively, Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2020/0219987) hereinafter “Lee” in view of Yang et al. (US 2022/0238694) hereinafter “Yang”
Regarding claim 1, Fig. 3B of Lee teaches a power semiconductor device comprising: a substrate (Item 210); a channel layer (Item 230) disposed on or over the substrate (Item 210); a barrier layer (Item 240) disposed on the channel layer (Item 230); a gate electrode (Item 254); a source electrode (Item 250) and a drain electrode (Item 252) that are separated from the gate electrode (Item 254), the source electrode (Item 250) and the drain electrode (Item 252) forming ohmic contact regions (Paragraph 0051) on the barrier layer (Item 240); and an insulation film (Item 263) disposed on the barrier layer (Item 240), wherein the barrier layer (Item 240) is configured such that a first side (Top surface of Item 240 to the right of Item 254) of an upper surface of the barrier layer (Item 240) is stepped (See Picture 2 below) between the gate electrode (Item 254) and the drain electrode (Item 252).
Lee does not teach a capping layer disposed on the barrier layer nor the gate electrode disposed on the capping layer.
Fig. 10B of Yang teaches where a capping layer (Item 110) is disposed on a barrier layer (Item 106) and where an gate electrode (Item 112) is disposed on the capping layer (Item 110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a capping layer disposed on the barrier layer, where the gate electrode is disposed on the capping layer because the capping layer controls the conducting or cut-off of the 2DEG in the gate region (Yang Paragraph 0037).
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Picture 2 (Labeled version of a portion of Lee Fig. 3B)
Regarding claim 2, Fig. 3B of Lee further teaches where the barrier layer (Item 240) has a stepped structure (See Picture 2 above) in which the first side of the upper surface of the barrier layer (Item 240) is recessed downward from the gate electrode (Item 254) to the drain electrode (Item 252).
Alternatively, Claims 1, 3, 5, 6 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. (US 2015/0236095) hereinafter “Mueller” in view of Yang et al. (US 2022/0238694) hereinafter “Yang” and in further view of Lei et al. (US 2022/0157977) hereinafter “Lei”.
Regarding claim 1, Fig. 2 of Mueller teaches a power semiconductor device comprising: a substrate (Item 2); a channel layer (Item 4) disposed on or over the substrate (Item 2); a barrier layer (Item 6) disposed on the channel layer (Item 4); a gate electrode (Item 16); a source electrode (Item 12) and a drain electrode (Item 14) that are separated from the gate electrode (Item 16), the source electrode (Item 12) and the drain electrode (Item 14) forming ohmic contact regions (Paragraph 0031) on the barrier layer (Item 6); wherein the barrier layer (Item 6) is configured such that a first side (Top surface of Item 6 to the right of Item 16) of an upper surface of the barrier layer (Item 6) is stepped between the gate electrode (Item 16) and the drain electrode (Item 14).
Mueller does not teach a capping layer disposed on the barrier layer nor the gate electrode disposed on the capping layer.
Fig. 10B of Yang teaches where a capping layer (Item 110) is disposed on a barrier layer (Item 106) and where an gate electrode (Item 112) is disposed on the capping layer (Item 110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a capping layer disposed on the barrier layer, where the gate electrode is disposed on the capping layer because the capping layer controls the conducting or cut-off of the 2DEG in the gate region (Yang Paragraph 0037).
Mueller does not teach an insulation film disposed on the barrier layer.
Fig. 1A of Lei teaches where an insulation layer (Item 108) is disposed on a barrier layer (Item 106).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have an insulation film disposed on the barrier layer because the insulation film electrically isolates the barrier layer from electrically conductive structures above it (Lei Paragraph 0029).
Regarding claim 3, Fig. 2 of Mueller further teaches where the barrier layer (Item 6) comprises a first recess portion (See Picture 4 below), the first recess portion being spaced apart from an edge of the drain electrode (Item 14) on the upper surface of the barrier layer (Item 6) and being recessed downward.
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Picture 4 (Labeled version of a portion of Mueller Fig, 2)
Regarding claim 5, Fig. 2 of Mueller further teaches where the barrier layer (Item 6) further comprises a second recess portion (See Picture 4 above), the second recess portion being recessed downward between the first recess portion and the drain electrode (Item 14) on the upper surface of the barrier layer (Item 6).
Regarding claim 6, Fig. 2 of Mueller further teaches where the second recess portion has a horizontal with greater than a horizontal width of the first recess portion (See Picture 4 above).
Regarding claim 8, Fig. 2 of Mueller further teaches where a recessed depth of the second recess portion is greater than a recessed depth of the first recess portion (See Picture 4 above).
Regarding claim 9, the process limitation of “wherein the second recess portion is formed substantially simultaneously with the first recesses portion” found in product claim 9 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 9 does not require the first and second recess portions to be formed simultaneously, but simply that first and second recess portions are formed and present in the final structure.
Regarding claim 10, Fig. 2 of Mueller further teaches where the second recess portion is physically connected to the first recess portion (See Picture 4 above).
Claims 11, 13, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. (US 2015/0236095) hereinafter “Mueller” in view of Yang et al. (US 2022/0238694) hereinafter “Yang”.
Regarding claim 11, Fig. 2 of Mueller teaches a power semiconductor device comprising: a substrate (Item 2); a buffer layer (Paragraph 0030) disposed on the substrate (Item 2); a channel layer (Item 4) disposed on or over the substrate (Item 2), the channel being a nitride based semiconductor layer; a barrier layer (Item 6) disposed on the channel layer (Item 4), the barrier layer being a nitride based semiconductor layer that is different from the channel layer (Item 4); a gate electrode (Item 16); a source electrode (Item 12) and a drain electrode (Item 14) that are separated from the gate electrode (Item 16), the source electrode (Item 12) and the drain electrode (Item 14) forming ohmic contact regions (Paragraph 0031) on the barrier layer (Item 6); wherein the barrier layer (Item 6) comprises a recess portion that comprises: a narrow recess portion (labeled as 1st recess portion in Picture 4 above) positioned between the drain electrode (Item 14) and the gate electrode (Item 16); and a wide recess portion (labeled as 2nd recess portion in Picture 4 above) positioned between the narrow recess portion and the drain electrode (Item 14), the wide recess portion being connected to the narrow recess portion.
Mueller does not teach a capping layer disposed on the barrier layer nor the gate electrode disposed on the capping layer.
Fig. 10B of Yang teaches where a capping layer (Item 110) is disposed on a barrier layer (Item 106) and where an gate electrode (Item 112) is disposed on the capping layer (Item 110).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a capping layer disposed on the barrier layer, where the gate electrode is disposed on the capping layer because the capping layer controls the conducting or cut-off of the 2DEG in the gate region (Yang Paragraph 0037).
Regarding claim 13, Fig. 2 of Mueller further teaches where the narrow recess portion has a horizontal central axis that is substantially parallel to a horizontal central axis of the wide recess portion to which the narrow recess portion is connected (See Picture 4 above).
Regarding claim 14, Fig. 2 of Mueller further teaches where a recessed depth of the wide recess portion is greater than a recessed depth of the narrow recess portion, so that a first side of an upper surface of the barrier layer has a stepped structure that is recessed downward from the gate electrode to the drain electrode (See Picture 4 above).
Regarding claim 16, the process limitation of “wherein the recess portion is formed by a plasma etching process” found in product claim 16 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 16 does not require the recess portion to be formed by a plasma etching process, but simply that recess portion is formed and present in the final structure.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mueller et al. (US 2015/0236095) hereinafter “Mueller” in view of Yang et al. (US 2022/0238694) hereinafter “Yang” and in further view of Chen et al. (US 2017/0338810) hereinafter “Chen”.
Regarding claim 12, the combination of Mueller and Yang teaches all of the elements of the claimed invention as stated above except where the recess portion comprises a plurality of recess subportions, and the plurality of recess subportions are spaced apart from each other along an orthogonal direction on an upper surface of the barrier layer.
Fig. 27 of Chen teaches where a first recess (Item 2102) comprises a plurality of first recess sub-recess portions and the plurality of first recess sub-portions are spaced apart from each other along an orthogonal direction on an upper surface of a barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the recess portion comprises a plurality of recess subportions, and the plurality of recess subportions are spaced apart from each other along an orthogonal direction on an upper surface of the barrier layer because the plurality of recessed regions increases the channel resistance which reduces threshold drain voltage (Chen Paragraph 0097).
Allowable Subject Matter
Claims 7 and 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have a recessed depth of the second recess portion be greater than a recessed depth of the first recess portion along with the other limitations in claims 1, 3 and 5 from which claim 7 depends.
Regarding claim 15, the prior art does not teach, suggest or motivate one having ordinary skill in the art to have the recess portion has a pair of narrow recess portions respectively connected to a pair of wide recess portions, and wherein the recess portion has an additional narrow recess portion of an island structure, the additional narrow recess portion being positioned between the pair of narrow recess portions in an orthogonal direction thereof along with the other limitations in claim 11 from which claim 15 depends.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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