DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/27/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9, 11-19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jain (US 20220391128)
Regarding Claim 1, Jain teaches
A computing system comprising: a data storage to store data associated with a workload; (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT) [0017] use of separate bitlines and precharge circuitry for a relatively small region of a SRAM sub-array partition for storing LUT entries to be used in PIM operations. [0039] LUT compute circuitry 305 is reconfigurable and can support a large spectrum of machine learning model inference workloads) (i.e. SRAM store data associated with machine learning model workload)
and an in-memory compute core that includes: (Jain [0020] the term “memory,” as used herein in reference to performing compute-in-memory (CIM) or processor-in-memory (PIM) multiply and accumulate operations, may refer to memory 104 and/or data storage device)
a plurality of cores to receive the data associated with the workload and execute the workload to process the data and generate partial data, (Jain [0031] processor 102 may include 14 cores [0041] FIG. 5, LUT compute circuitry 305 is in circuit or coupled with sub-array 214, LUT compute circuitry 305 may receive a request to perform a MAC operation, LUT compute circuitry 305 includes compute core 506 [0050] As shown in FIG. 5, Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e., LUT circuity perform MAC operation is execute the workload, and stored partial sum(s) is partial data)
and a memory storage to store the partial data, wherein the memory storage is accessible by the plurality of cores as the workload is being executed. (Jain [0035] Sub-array 214 may be representative of SRAM circuitry … LUT dedicated rows 310 for storing LUT entries, the LUT entries may be used by logic and/or features of LUT compute circuitry 305 to execute a 4-bit×4-bit matrix multiplication. [0050] LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation) (i.e. SRAM is the memory storage to store LUT entries which has partial data, is accessible and data be used by logic of LUT compute circuitry which has cores for the MAC operation as workload is being executed)
Regarding Claim 2, Jain teaches
wherein the in-memory compute core is a single in-memory core. (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT)) (i.e., compute/processor in memory is processor and memory storage functionality in one, therefore single in-memory core)
Regarding Claim 4, Jain teaches
wherein the plurality of cores is to receive the partial data from the memory storage during execution of the workload. (Jain [0050] Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation. [0039] machine learning model inference workloads perform different operations such as MAC operations)
Regarding Claim 5, Jain teaches
further comprising control logic, implemented in one or more of configurable logic or fixed-functionality logic, to control storage of the partial data into the memory storage and accesses of the partial data stored in the memory storage. (Jain [0023] Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations …controller(s) 106 may include the example VFU 130 which may be implemented as any device or circuitry (e.g., dedicated circuitry, reconfigurable circuitry, ASIC, FPGA, etc.). Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e. control logic - configurable logic FPGA, fixed-functionality logic ASIC - subsequently access previously stored partial sum(s))
Regarding Claim 6, Jain teaches
further comprising control logic, implemented in one or more of configurable logic or fixed-functionality logic, to select one or more of the plurality of cores to execute the workload. (Jain [0023] memory 104 that includes memory media 110 and media access circuitry 108 (e.g., a device or circuitry, such as a processor, ASIC…Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations))
Regarding Claim 7, Jain teaches
wherein the workload is associated with a machine learning model. (Jain [0039] LUT compute circuitry 305 is reconfigurable and can support a large spectrum of machine learning model inference workloads)
Regarding Claim 8, Jain teaches
An in-memory compute core, the in-memory compute core comprising: a plurality of cores, (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT) [0031] processor 102 may include 14 cores)
implemented in one or more of configurable logic or fixed-functionality logic, (Jain [0023] controller(s) 106 may include the example VFU 130 which may be implemented as any device or circuitry (e.g., dedicated circuitry, reconfigurable circuitry, ASIC, FPGA, etc.) capable of offloading vector-based tasks from processor 102.) (i.e., FPGA is configurable logic, ASIC is fixed-functionality logic)
to receive data associated with a workload, and execute the workload to process the data and generate partial data; (Jain [0041] FIG. 5, LUT compute circuitry 305 is in circuit or coupled with sub-array 214, LUT compute circuitry 305 may receive a request to perform a MAC operation, LUT compute circuitry 305 includes compute core 506 [0050] As shown in FIG. 5, Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e., LUT circuity perform MAC operation is execute the workload, and stored partial sum(s) is partial data)
and a memory storage to store the partial data, wherein the memory storage is accessible by the plurality of cores as the workload is being executed. (Jain [0035] Sub-array 214 may be representative of SRAM circuitry … LUT dedicated rows 310 for storing LUT entries, the LUT entries may be used by logic and/or features of LUT compute circuitry 305 to execute a 4-bit×4-bit matrix multiplication. [0050] LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation) (i.e. SRAM is the memory storage to store LUT entries which has partial data, is accessible and data be used by logic of LUT compute circuitry which has cores for the MAC operation as workload is being executed)
Regarding Claim 9, Jain teaches
wherein the in-memory compute core is a single in-memory core. (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT)) (i.e., compute/processor in memory is processor and memory storage functionality in one, therefore single in-memory core)
Regarding Claim 11, Jain teaches
wherein the plurality of cores is to receive the partial data from the memory storage during execution of the workload. (Jain [0050] Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation. [0039] machine learning model inference workloads perform different operations such as MAC operations)
Regarding Claim 12, Jain teaches
further comprising control logic, implemented in one or more of configurable logic or fixed-functionality logic, to control storage of the partial data into the memory storage and accesses of the partial data stored in the memory storage. (Jain [0023] Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations …controller(s) 106 may include the example VFU 130 which may be implemented as any device or circuitry (e.g., dedicated circuitry, reconfigurable circuitry, ASIC, FPGA, etc.). Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e. control logic - configurable logic FPGA, fixed-functionality logic ASIC - subsequently access previously stored partial sum(s))
Regarding Claim 13, Jain teaches
further comprising control logic, implemented in one or more of configurable logic or fixed-functionality logic, to select one or more of the plurality of cores to execute the workload. (Jain [0023] memory 104 that includes memory media 110 and media access circuitry 108 (e.g., a device or circuitry, such as a processor, ASIC…Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations))
Regarding Claim 14, Jain teaches
wherein the workload is associated with a machine learning model and includes a multiply–accumulate operation. (Jain [0039] LUT compute circuitry 305 is reconfigurable and can support a large spectrum of machine learning model inference workloads [0003] Machine learning currently relies on the computation of dot-products and absolute difference of vectors, typically computed with multiply and accumulate (MAC) operations performed on the parameters, input data and weights.)
Regarding Claim 15, Jain teaches
A method comprising: receiving, with a plurality of cores of an in-memory compute core, data associated with a workload; (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT) [0039] LUT compute circuitry 305 is reconfigurable and can support a large spectrum of machine learning model inference workloads) (i.e. SRAM store data associated with machine learning model workload)
executing, with the plurality of cores, the workload to process the data and generate partial data; (Jain [0041] FIG. 5, LUT compute circuitry 305 is in circuit or coupled with sub-array 214, compute core 506 [0050] As shown in FIG. 5, Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e., LUT circuity store partial sum(s) is partial data)
and storing the partial data into a memory storage of the in-memory compute core that is accessible by the plurality of cores as the workload is being executed. (Jain [0035] Sub-array 214 may be representative of SRAM circuitry … LUT dedicated rows 310 for storing LUT entries, the LUT entries may be used by logic and/or features of LUT compute circuitry 305 to execute a 4-bit×4-bit matrix multiplication. [0050] LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation) (i.e. SRAM is the memory storage to store LUT entries which has partial data, is accessible and data be used by logic of LUT compute circuitry which has cores for the MAC operation as workload is being executed)
Regarding Claim 16, Jain teaches
wherein the in-memory compute core is a single in-memory core. (Jain [0001] a compute-in-memory (CIM) or processor-in-memory (PIM) techniques using repurposed or dedicated static random access memory (SRAM) rows of an SRAM sub-array to store a look-up-table (LUT)) (i.e., compute/processor in memory is processor and memory storage functionality in one, therefore single in-memory core)
Regarding Claim 17, Jain teaches
receiving, with the plurality of cores, the partial data from the memory storage during execution of the workload. (Jain [0050] Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation. [0039] machine learning model inference workloads perform different operations such as MAC operations)
Regarding Claim 18, Jain teaches
wherein further comprising controlling, with control logic implemented in one or more of configurable logic or fixed-functionality logic, storage of the partial data into the memory storage and accesses of the partial data stored in the memory storage. (Jain [0023] Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations …controller(s) 106 may include the example VFU 130 which may be implemented as any device or circuitry (e.g., dedicated circuitry, reconfigurable circuitry, ASIC, FPGA, etc.). Din 513 couples with operand register 504 to enable LUT compute circuitry 305 to at least temporarily store partial sum(s) or results that may be subsequently used by logic and/or features of LUT compute circuitry 305 for the MAC operation.) (i.e. control logic - configurable logic FPGA, fixed-functionality logic ASIC - subsequently access previously stored partial sum(s) to for the MAC operation)
Regarding Claim 19, Jain teaches
further comprising selecting, with control logic implemented in one or more of configurable logic or fixed-functionality logic, one or more of the plurality of cores for execution of the workload. (Jain [0023] memory 104 that includes memory media 110 and media access circuitry 108 (e.g., a device or circuitry, such as a processor, ASIC…Circuitry to implement media access circuitry 108 may be configured to selectively read from and/or write to memory media 110 in response to corresponding requests (e.g., from processor 102 which may be executing an artificial intelligence related application that may be enabled by execution of MAC operations))
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 10, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 20220391128), in view of Murphy (US 20190296892).
Regarding Claim 3, Jain teaches
Jain does not teach wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows.
However, Murphy teaches wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows. (Murphy [0006] Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). [0059] PIM capable device operations can use bit vector based operations. As used herein, the term “bit vector” is intended to mean a physically contiguous number of bits on a bit vector memory device, e.g., PIM device, whether physically contiguous in rows (e.g., horizontally oriented) or columns (e.g., vertically oriented) in an array of memory cells.) (i.e., PIM device processors are implemented directly on the same chip as the memory array. Therefore, PIM device has memory array for both processor and memory storage, so the array columns and rows are heterogeneous)
Jain and Murphy are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jain and Murphy to modify the Jain‘s compute-in-memory/processor-in-memory with Murphy’s teaching of PIM device processors implemented directly on the same chip as the memory array. The motivation for doing so would be that (Murphy [0006]) A PIM device may save time by reducing and/or eliminating external communications and may also conserve power.
Regarding Claim 10, Jain teaches
Jain does not teach wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows.
However, Murphy teaches wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows. (Murphy [0006] Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). [0059] PIM capable device operations can use bit vector based operations. As used herein, the term “bit vector” is intended to mean a physically contiguous number of bits on a bit vector memory device, e.g., PIM device, whether physically contiguous in rows (e.g., horizontally oriented) or columns (e.g., vertically oriented) in an array of memory cells.) (i.e., PIM device processors are implemented directly on the same chip as the memory array. Therefore, PIM device has memory array for both processor and memory storage, so the array columns and rows are heterogeneous)
Jain and Murphy are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jain and Murphy to modify the Jain‘s compute-in-memory/processor-in-memory with Murphy’s teaching of PIM device processors implemented directly on the same chip as the memory array. The motivation for doing so would be that (Murphy [0006]) A PIM device may save time by reducing and/or eliminating external communications and may also conserve power.
Regarding Claim 20, Jain teaches
Jain teaches the workload is associated with a machine learning model and includes a multiply–accumulate operation, (Jain [0039] LUT compute circuitry 305 is reconfigurable and can support a large spectrum of machine learning model inference workloads [0003] Machine learning currently relies on the computation of dot-products and absolute difference of vectors, typically computed with multiply and accumulate (MAC) operations performed on the parameters, input data and weights.)
Jain does not teach wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows.
However, Murphy teaches wherein the plurality of cores and memory banks of the memory storage are arranged in heterogeneous columns and rows. (Murphy []0006] Processing performance may be improved in a processor-in-memory (PIM) device, in which a processor may be implemented internal and/or near to a memory (e.g., directly on a same chip as the memory array). [0059] PIM capable device operations can use bit vector based operations. As used herein, the term “bit vector” is intended to mean a physically contiguous number of bits on a bit vector memory device, e.g., PIM device, whether physically contiguous in rows (e.g., horizontally oriented) or columns (e.g., vertically oriented) in an array of memory cells.) (i.e., PIM device processors are implemented directly on the same chip as the memory array. Therefore, PIM device has memory array for both processor and memory storage, so the array columns and rows are heterogeneous)
Jain and Murphy are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Jain and Murphy to modify the Jain‘s compute-in-memory/processor-in-memory with Murphy’s teaching of PIM device processors implemented directly on the same chip as the memory array. The motivation for doing so would be that (Murphy [0006]) A PIM device may save time by reducing and/or eliminating external communications and may also conserve power.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
LI (US 20220414444) teaches computation in memory architecture and dataflow supporting machine learning tasks.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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