DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 09/15/26.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, 6 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shiratake (USP 6,147,514).
For claim 1, Figure 12 of Shiratake teaches a dual-tail sampler comprising: a first stage (Mp1-Mp5, Mn1-Mn2, Mn4-Mn6, MX1-MX2) comprising: an input pair of transistors (Mn1-Mn2) having inputs (Q, /Q) connected to gates of the input pair of transistors (Mn1-Mn2); a cross-coupled load circuit (Mp4-Mn4, Mp4-Mn5) having gates (Mp4-Mn4, Mp4-Mn5) directly connected to drain nodes of the input pair of transistors (drains of Mn1-Mn2); and at least one pass-gate switch (Mp3) between the input pair of transistors (Mn1-Mn2) and the cross-coupled load circuit (Mp4-Mn4, Mp4-Mn5) and coupled to a first clock signal (Clk); and a precharge device (Mp1, Mp2) connected between the drain nodes of the input pair of transistors (Mn1-Mn2) and coupled to a second clock signal (Clk, because, for broadest reasonable interpretation, the claim does not specifically recited that the first and second clock signals are different).
For claim 3, Figure 12 of Shiratake teaches wherein the gates of the cross-coupled load circuit (Mp4-Mn4, Mp4-Mn5) are connected to the drain nodes of the input pair of transistors (Mn1-Mn2) rather than to output nodes of the first stage.
For claim 4, Figure 12 of Shiratake teaches wherein the first stage (Mp1-Mp5, Mn1-Mn2, Mn4-Mn6, MX1-MX2) comprises an amplification stage (Mp1-Mp5, Mn1-Mn2, Mn4-Mn6, MX1-MX2).
For claim 6, Figure 12 of Shiratake teaches a second stage (I11, I21) coupled to the first stage (Mp1-Mp5, Mn1-Mn2, Mn4-Mn6, MX1-MX2).
For claim 7, Figure 12 of Shiratake teaches wherein the second stage (I11, I21) comprises an amplification stage (I11, I21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shiratake (USP 6,147,514) in view of Eum (US 2001/0005150).
For claim 8, Shiratake (Figure 12) teaches a dual-tail sampler includes all the limitations of this claim as discussed in the 102 rejection above except for “wherein the at least one pass-gate switch comprises a pair of complementary pass-gate switches”. However, Figure 5 of Eum teaches a device including a pass-gate switch (34, also see [0046]-[0047]) wherein the switch that comprises a pair of complementary pass-gate switches (P15 and N17). Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the dual-tail sampler in Shiratake (Figure 12) to replace the broad pass-gate switch (Mp3) with a specific switch (34) that comprises a pair of complementary pass-gate switches (P15 and N17) as taught in Figure 5 of Eum for the purpose of improving the passing of the signals since it is old and well known in the art that the use of a transmission gate (switch) comprises a pair of complementary pass-gate switches (connected in parallel) is more effective and stable in passing the signal than a single switch. Note that, in the combination/modification as discussed above (to replace the broad pass-gate switch (Mp3) with a specific switch (34) that comprises a pair of complementary pass-gate switches (P15 and N17) as taught in Figure 5 of Eum), the gate of P15 that receives first clock signal (sac1) would be the clock signal (Clk) in the modification/combination, and the gate of N17 that receives second clock signal (sac1b, which is inverted clock of the first clock sac1) would be the inverted clock signal Clkb of the first clock signal (Clk) in the modification/combination.
For claim 21, the combination/modification as discussed in claim 2 above also teach all the limitation of claim 21, i.e., wherein the second clock signal corresponds to an inverse of the first clock signal. Note that, in the combination/modification as discussed above (to replace the broad pass-gate switch (Mp3) with a specific switch (34) that comprises a pair of complementary pass-gate switches (P15 and N17) as taught in Figure 5 of Eum), the gate of P15 that receives first clock signal (sac1) would be the clock signal (Clk) in the modification/combination, and the gate of N17 that receives second clock signal (sac1b, which is inverted clock of the first clock sac1) would be the inverted clock signal Clkb of the first clock signal (Clk) in the modification/combination.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Shiratake (USP 6,147,514) in view of Mohan (USP 7,800,411).
For claim 8, Shiratake (Figure 12) teaches a dual-tail sampler includes all the limitations of this claim as discussed in the 102 rejection above except for “the dual-tail sampler further comprising a set-reset latch that encodes a sampled signal from the second stage as a bit”. However, Figure 4 of Mohan teaches a set-reset latch (420, 430) that encodes a sampled signal from the second stage (410, 430) as a bit. Therefore, it would have been obvious to one having ordinary skilled in the art at the time before the invention was effectively filed to modify the dual-tail sampler in Shiratake (Figure 12) to include a set-reset latch (420, 430), as taught in Figure 4 of Mohan, that encodes a sampled signal from the second stage as a bit for the purpose to hold the output values during reset for improve the performance of the dual-tail sampler circuitry (Mohan, Col. 1, lines 25-33; and Col. 4, lines 19-35).
Allowable Subject Matter
Claims 9-20 are allowed.
Claims 9 and 18, as amended (see amendment 11/14/25), are allowed because applicant’s arguments are found persuasive that the closet prior art of record, Dong (US 2022/0191069) and Ainspan (USP 9,699,009), taken alone or in combination (see Applicant’s Remarks 11/14/25), fails to teach or suggest the limitations “the high, middle, and low dual-tail samplers are configured to operate at least partially asynchronously with each other such that at least one of the high, middle, and low dual-tail samplers is decoupled from operating simultaneously with a remainder of the high, middle, and low dual-tail samplers; and an output of the at least one of the high, middle, and low dual-tail samplers decouples the remainder of the high, middle, and low dual-tail samplers” in combination with other limitations as recited in claim 9; and “wherein at least one of the high, middle, and low dual-tail samplers is decoupled from operating simultaneously with a remainder of the high, middle, and low dual-tail samplers; and wherein an output of the at least one of the high, middle, and low dual-tail samplers decouples the remainder of the high, middle, and low dual-tail samplers” in combination with other limitations as recited in claim 18.
Claims 10-17 and 19-20 are allowed because they depend on claims 9 and 18, respectively.
Response to Arguments
Applicant's arguments filed 09/15/26 have been fully considered but they are not persuasive.
Applicant argues that “Shiratake, even assuming, ad arguendo, that Mp3 of Shiratake suggests "at least one pass-gate switch" recited in claim 1, and Mpl-Mp2 suggests "a precharge device" recited in claim 1, every figure of Shiratake with the asserted configuration (e.g., FIGS. 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 17) all illustrate Mpl-Mp2 and Mp3 being connected to the same Clk signal. Accordingly, Shiratake fails to disclose or suggest at least the amended features”. However, the above arguments are not persuasive because claim 1 does not specifically recite that the second clock signal and the second clock signal are different clock signals. Therefore, for broadest reasonable interpretation, the first clock signal and the second clock signal can be the same clock signal (because claim 1 does not require that the first clock signal and the second clock signal are different from each other). Further, if the claim recited the first and second clock signals are different clock signals then the combination/modification of Shiratake in view of Eum as discussed in claims 2 and 21 above would also meet the first and second clock signals are different clock signals.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
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/Long Nguyen/
Primary Examiner
Art Unit 2836
